KR19990002374U - 3-Channel S Compensation Capacitor Switching Circuit for Monitors - Google Patents

Abstract

The present invention relates to a three-channel S correction capacitor switching circuit for improving the linearity of the horizontal deflection in a multi-sync monitor.

The circuit of the present invention has a basic capacitor C10 and a plurality of capacitors connected thereto, so that the S correction capacitance can be adjusted according to the horizontal synchronizing frequency to improve the linearity of the horizontal deflection. In the capacitor switching circuit, the first switching unit 111 operates by receiving the first mode control signal CS0 from a microcomputer (not shown) and receives the first mode control signal CS1 from the microcomputer (not shown). The second switching unit 112 is operated, and the third switching unit 113 is operated by receiving the first mode control signal CS2 from the microcomputer (not shown), thereby reducing the manufacturing cost with a simple configuration The linearity of the horizontal output can be improved by adjusting the S correction capacitance by the switching operation according to the mode.

Description

3-Channel S Compensation Capacitor Switching Circuit for Monitors

The present invention relates to a circuit for switching parameters according to a mode in the horizontal deflection of a multi-sync monitor, and more particularly to a circuit consisting of three channels of the S correction capacitor switching circuit.

In general, multi-sync monitors are monitors that can vary in resolution by accepting various horizontal and vertical sync frequencies depending on the video card they support. For example, the resolution is 640 x 480 in VGA mode and the horizontal synchronization frequency is 31.5KHz, the resolution is 800 x 600 in SVGA mode, and 1024 x 768 or 1280 x 1024 in XGA mode. As the resolution changes according to the mode as described above, the horizontal and vertical synchronizing frequencies vary accordingly, and accordingly, various parameter values of the monitor need to be adjusted.

1 is a partial circuit diagram of a monitor including a general S correction capacitor switching circuit.

Referring to FIG. 1, a H. drive signal output from a horizontal oscillation IC (not shown) turns on the horizontal driving transistor Q1 and the base terminal of the horizontal output transistor Q2 through the horizontal driving transformer HDT. Supply current to

When the horizontal output transistor Q2 is turned on by the H. drive signal, current flows through the horizontal deflection coil H.DY to the horizontal output transistor Q2. Thus, during the period in which the horizontal output transistor Q2 is turned on, it corresponds to the second half of the effective scanning period of the horizontal sawtooth wave, and when the horizontal output transistor Q2 is rapidly turned off according to the horizontal drive signal, the horizontal deflection coil H. The current accumulated in DY causes the retrace capacitor (ie, resonant capacitor Cr) to charge. Subsequently, when the retrace capacitor Cr is completely charged, the discharge capacitor is discharged back to the horizontal deflection coil H. DY. Accordingly, total energy is accumulated in the horizontal deflection coil H. DY.

In this way, the entire period of the charging and discharging of the retrace capacitor Cr determines the retrace period.

Subsequently, when all the energy is accumulated in the horizontal deflection coil H.DY, and the voltage of the horizontal deflection coil H.DY is such that the forward bias is applied to the damper diode Dd, the damper diode Dd becomes conductive. The current flowing through the horizontal deflection coil (H.DY) gradually returns to zero.

As such, when the current reaches zero, the horizontal output transistor Q1 is turned on again by the H. drive signal, and the horizontal sawtooth current flows through the horizontal deflection coil H.DY while repeating the above process. Deflection is achieved. At this time, the horizontal output unit is connected to the FBT (not shown), the B + voltage applied from the SMPS is applied to the FBT.

In addition, the horizontal deflection coil (H.DY) is connected to the S correction capacitor (Cs), the damping resistor (R2) and the horizontal linearity coil (L1) for the 'S' correction to improve the linearity of the horizontal deflection. .

That is, the oscillation frequency of the sawtooth wave and the sawtooth current are controlled by the horizontal linearity coil L1 for balancing the horizontal width symmetrically and the S correction capacitor Cs for flowing the S-shaped sawtooth wave to prevent the horizontal scan from sagging. The size is determined to maintain the linearity of the screen.

As is well known, S correction is used to compensate for the periphery of the left and right sides of the receiving tube extending from the center even when a deflection current having linearity is applied when the horizontal deflection angle is large. Injecting the peripheral part by spilling means that the deflection angle is smaller than the center. Thus, the S correction capacitor switching unit 110 receives a plurality of mode control signals CS according to the horizontal frequency from the microcomputer 100 to adjust the S correction capacitance.

However, in the related art, the S correction capacitor switching circuit includes four switching transistors, four field effect transistors, and four S correction capacitors, so that four S parallel connected to S correction capacitors basically provided according to four mode control signals are provided. By selecting the S correction capacitors, the capacitance is changed to adjust the magnitude of the sawtooth current, but the S correction capacitor switching circuit having the above structure has a complicated configuration.

In order to solve the above problems, the present invention is designed to solve the above problems. In the multi-sync monitor, it is possible to improve the linear deflection linearity by adjusting the S correction capacitance while reducing the manufacturing cost by simplifying the circuit configuration. The objective is to provide a three-channel S-correction capacitor switching circuit for the monitor.

The circuit of the present invention for achieving the above object, a multi-sink having a basic capacitor and a plurality of capacitors connected thereto, to improve the linear deflection of the horizontal deflection by adjusting the S correction capacitance according to the horizontal synchronization frequency In the S correction capacitor switching circuit of the monitor, a first switching unit operating by receiving a first mode control signal from a microcomputer (not shown) and a second switching unit operating by receiving a second mode control signal from a microcomputer (not shown) And a third switching unit operating by receiving a third mode control signal from a microcomputer (not shown).

1 is a partial circuit diagram of a monitor including a typical S correction capacitor switching circuit,

Figure 2 is a circuit diagram showing a three-channel S correction capacitor switching circuit of the multi-sync monitor according to the present invention.

＊ Explanation of symbols for main parts of drawing

100: micom 110: S correction capacitor switching unit

111: first switching unit 112: second switching unit

113: third switching unit H.DY: horizontal deflection coil

Q1: horizontal drive transistor Q2: horizontal output transistor

Q1A, Q2A, Q3A: Switching Transistor Q1B, A2B, Q3B: Field Effect Transistor

Dd: Damping Diode Cr: Return Capacitor

C10, C11, C12, C13: S correction capacitor L1: Horizontal linearity coil

R1, R2, R3, R4, R5, R6, R7, R8: Resistance

Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram showing a three-channel S correction capacitor switching circuit of the multi-sync monitor according to the present invention.

As shown in FIG. 2, the three-channel S correction capacitor switching circuit according to the present invention includes a horizontal driving transistor Q1, a horizontal output transistor Q2, a horizontal deflection coil H.DY, and an S correction capacitor switching unit 110. ), And so on.

In addition, the S correction capacitor switching unit 110 is composed of a first switching unit 111, a second switching unit 112, and a third switching unit 113, each switching unit is the same configuration 3 It consists of three switching transistors, three field effect transistors, three capacitors, and the like.

Multi-sync monitors are also commonly referred to as multi-scanning monitors, which can be displayed in any mode if the frequency to be displayed is within the product's operating range. Such a multi-sync monitor is provided with a microcomputer for determining the use mode and adjusting the screen size and the like, and by this microcom, various parameters are set automatically according to the mode. For example, recently produced multi-sync monitor products can support the horizontal frequency from 31KHz to 69KHz, and the vertical frequency can support from 30Hz to 150Hz.

Mode control signal outputted to adjust the parameters after determining the mode according to the horizontal synchronization signal (H.sync) and vertical synchronization signal (V.sync) according to the present invention (100, shown in Figure 1) CS0 to CS2) are as follows.

TABLE 1

As shown in Table 1, when the horizontal frequency is 31KHz to 33KHz, the mode control signals CS0 to CS2 are all low (L). When the horizontal frequency is 34KHz to 45KHz, the mode control signal CS0 is' high (H). And the remaining mode control signals CS1 and CS2 are all high.

If the horizontal frequency is 31KHz to 33KHz, since the mode control signals CS0 to CS2 are all low, the first switching transistor Q1A connected to the first mode control signal CS0 at the base end is turned off. Accordingly, the voltage divided by the resistors R3 and R4 is applied to the gate terminal of the first field effect transistor Q1B to turn on the first field effect transistor Q1B. Therefore, the first capacitor C11 connected to the drain terminal of the first field effect transistor Q1B is connected in parallel to the basic capacitor C10.

In addition, since the second mode control signal CS1 and the third mode control signal CS2 are 'low', the second field effect transistor Q2B and the third field effect transistor Q3B are turned on by the above operation. The second capacitor C12 and the third capacitor C13 are connected in parallel to the basic capacitor C10.

Therefore, the total S correction capacitance is determined and increased by the sum of the capacitors C11 to C13 and the basic capacitor C10 connected in parallel as described above.

If the horizontal frequency is 61KHz to 69KHz, as shown in Table 2, since all of the mode control signals CS0 to CS2 are 'high', the switching transistors Q1A to Q3A are turned on so that the field effect transistor is turned on. A low is applied to the gate ends of the gates Q1B to Q3B to turn off. Therefore, the capacitors C11 to C13 connected to the drain terminals of the field effect transistors Q1B to Q3B are separated from the basic capacitor C10 so that the total S correction capacitance is determined only by the basic capacitor C10.

That is, the horizontal frequency is less capacitor at high frequency and the capacitor is used at low frequency, the charge and discharge curve is changed according to the capacity of the total S correction capacitor.

As described above, the circuit of the present invention can simplify the structure by changing the capacitance of the entire S correction capacitor according to the three mode control signals, thereby reducing the manufacturing cost and improving the linearity of the horizontal deflection.

Claims (4)

In the S correction capacitor switching circuit of a multi-sink monitor having a basic capacitor (C10) and a plurality of capacitors connected thereto to adjust the S correction capacitance according to the horizontal synchronizing frequency to improve the linearity of the horizontal deflection. A first switching unit 111 which operates by receiving a first mode control signal CS0 from a microcomputer; A second switching unit 112 which operates by receiving a second mode control signal CS1 from a microcomputer; And A three-channel S correction capacitor switching circuit of the multi-sync monitor, characterized in that consisting of a third switching unit 113 for receiving and operating a third mode control signal (CS2) from the microcomputer. The method of claim 1, wherein the first switching unit 111 is turned on when the base terminal is connected to the first mode control signal CS0 and the first mode control signal CS0 is 'high' and is turned 'low'. A first switching transistor Q1A that is turned off; When the first switching transistor Q1A is turned on, 'low' is applied to the gate terminal and turned on. When the first switching transistor Q1A is turned off, the divided voltage is applied through the resistors R3 and R4 to be turned off. A first field effect transistor Q1B; And a first S correction capacitor C11 connected in series with a drain terminal of the first field effect transistor Q1B and connected in parallel with a basic capacitor C10. S correction capacitor switching circuit. The method of claim 1, wherein the second switching unit 112 is turned on when the base terminal is connected to the second mode control signal CS1 and the second mode control signal CS1 is 'high' and is turned 'low'. A second switching transistor Q2A that is turned off; When the second switching transistor Q2A is turned on, 'low' is applied to the gate terminal and turned on. When the second switching transistor Q2A is turned off, the divided voltage is applied through the resistors R5 and R6 to turn off. A second field effect transistor Q2B; And a second S correction capacitor C12 connected in series with the drain terminal of the second field effect transistor Q2B and connected in parallel with the basic capacitor C10. S correction capacitor switching circuit. The method of claim 1, wherein the third switching unit 113 is turned on when the base terminal is connected to the third mode control signal CS2 and the third mode control signal CS2 is 'high' and 'low'. A third switching transistor Q3A that is turned off; When the third switching transistor Q3A is turned on, 'low' is applied to the base terminal and turned on. When the third switching transistor Q3A is turned off, the divided voltage is applied through the resistors R7 and R8 to turn off. A third field effect transistor Q3B; And a third S correction capacitor (C13) connected in series with the drain terminal of the third field effect transistor (Q3B) and connected in parallel with the basic capacitor (C10) of the multi-sink monitor. S correction capacitor switching circuit.