JPH0993457A - Horizontal deflection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To correct intermediate pin cushion distortion in an excellent way with a circuit configuration of one stage. SOLUTION: The circuit is provided with a transistor(TR) controlled by a horizontal period signal. A diode D and a resonance capacitor CC are connected in parallel between a collector and an emitter of the TR. Furthermore, a series circuit consisting of a horizontal deflection coil DY and an S-shape correction capacitor CS and a series circuit consisting of a coil HOL and a power supply VCC modulated by a parabolic wave of a vertical period are connected in parallel between the collector and the emitter of the TR. A series circuit consisting of capacitors C1 , C2 providing capacitive components is connected in parallel with the S shape correction circuit CS. A parallel circuit consisting of a diode D2 and a MOS switch element SW is connected between the capacitor C1 and ground, that is, in parallel with the capacitor C2 . Or the capacitor C2 may be replaced with other component as a resistor or may not be in use.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a horizontal deflection circuit suitable for use in an image display device for displaying, for example, a television signal or an image signal from a personal computer.

[0002]

2. Description of the Related Art For example, in an image display device for displaying a television signal, a horizontal deflection circuit as shown in A of FIG. 6 is basically used. That is, in FIG. 6A, when the transistor Tr is turned on, the resonance capacitor Cc
Are short-circuited, and a current having a constant gradient flows from the power supply Vcc to the horizontal deflection coil DY. Next, the transistor Tr
When is turned off, the resonance capacitor Cc and the horizontal deflection coil DY resonate, and the current flowing through the horizontal deflection coil DY becomes a sine wave.

When this current reaches a negative maximum value, that is, when the potentials across the horizontal deflection coil DY drop below 0 potential, the diode D is turned on. As a result, a current having a constant gradient flows again in the horizontal deflection coil DY, and when the collector voltage of the transistor Tr becomes higher than ground, the diode D is turned off. Therefore, if the transistor Tr is turned on before the diode D is turned off, the current flows in the opposite direction without interruption, and the above operation is repeated. This is one cycle of horizontal deflection.

However, if the beam is scanned at a constant speed in one period of such horizontal deflection, the images at the left and right ends will be elongated near the center of the tube surface. FIG.
As shown in B of FIG. 5, a capacitor Cs is added in series to the horizontal deflection coil DY to make the waveform of the deflection current dull, thereby slowing down the scanning speed of the beam at the left and right ends of the horizontal scanning line, and It is being done to eliminate the growth of.
This is S-shaped correction, and the above-mentioned capacitor Cs is an S-shaped correction capacitor.

On the other hand, considering the case where scanning is performed from the top to the bottom of the screen, the image of the image is displayed above and below the tube surface because the path difference of the beam current from the deflection center is geometrically long above and below the tube surface. It grows at and shrinks at the center. This is image distortion called pin distortion. Therefore, in order to correct such image distortion, the voltage of the S-shaped correction capacitor Cs is modulated in a parabolic shape so as to be small at the beginning and end of the vertical cycle and large at the middle thereof. This is pin distortion correction.

In an actual circuit, for example, as shown in FIG. 6B, the power source Vcc is modulated into a parabolic shape with a vertical cycle,
This power supply Vcc is supplied to the horizontal deflection coil D via the coil LOC.
It is connected in parallel to the series circuit of Y and the S-shaped correction capacitor Cs. As a result, the power source voltage applied to the S-shaped correction capacitor Cs is modulated in a parabolic shape, and the above-mentioned pin distortion correction is realized. In this way, the above-described S-shaped correction and pin distortion correction can be performed in the horizontal deflection circuit of the image display device.

However, even if such a correction is made,
For example, considering the case where scanning is performed from the top to the bottom of the screen as described above, the path difference of the beam current from the deflection center is geometrically different on the tube surface.
The horizontal deflection angle is different between the upper and lower ends of the tube surface and the X-axis, and the S-shaped correction amount of the deflection current is also different accordingly. That is, the center having a larger deflection angle than the upper and lower ends of the tube surface requires a stronger S-shaped correction amount.

Therefore, in the case where the S-shaped correction amount is the same on the entire screen, the S-shaped correction amount becomes smaller near the center of the screen compared to the upper and lower ends, and even if the left and right pin distortion correction is performed, it is shown in FIG. As described above, the vertical line between the left and right ends and the Y axis draws a convex arc toward the center. This image distortion is referred to as "intermediate pin distortion", and this distortion tends to appear stronger than that formed on a spherical surface, especially in a cathode ray tube having a cylindrical tube surface. Also, the distortion becomes significant when the deflection angle is increased.

On the other hand, for example, as shown in FIG.
The circuit of B in FIG. 6 described above is configured in two stages, and the S in the lower stage is further configured.
The position of the capacitor Cs2 corresponding to the character correction capacitor is moved.

That is, in this circuit, the capacitor C
By changing the voltage across s2, the capacitor Cs2
The current flowing through can be changed. That is, since the apparent capacitance value of the capacitor Cs2 can be changed, the horizontal deflection coil DY and the S-shaped correction capacitor Cs can be changed.
1, the resonance frequency of Cs2 will change. As a result, the S-shaped correction amount can be changed, so that the power source Vcc can be modulated in the vertical cycle to correct the intermediate pin distortion.

[0011]

However, as shown in FIG.
In the circuit of FIG. 2, a horizontal deflection coil DY, an S-shaped correction capacitor Cs, a diode D, etc. are provided for correction.
I need it heavily. In addition, since a large deflection current flows especially in the horizontal deflection coil DY and the S-shaped correction capacitor Cs, a device having a large current capacity is required. Therefore, the circuit scale of the deflection circuit becomes large, and the power consumption also greatly increases.

Further, in the circuit shown in FIG. 8, the horizontal frequency applied for correction using resonance of the horizontal deflection coil DY and the S-shaped correction capacitors Cs1 and Cs2 is limited. Therefore, for example, a circuit using a standard television signal cannot be applied to an image signal from a so-called HDTV or a high-resolution personal computer. Therefore, when applied to these, the circuit scale is further increased by providing means for further switching.

This application has been made in view of such a point, and the problem to be solved is that the circuit of the conventional two-stage structure requires two circuit elements and the circuit scale is large. As the size increases, the power consumption also increases. In addition, the horizontal frequency used is limited and cannot be applied to various video signals. However, for circuits other than the above-described two-stage configuration, no means for satisfactorily correcting the intermediate pin distortion has been proposed.

[0014]

Therefore, in the present invention, a capacitance component, a switch element, and a diode are provided in parallel with the S-correction capacitor, and the switch element is turned off in a predetermined period for each horizontal deflection. According to this, it is possible to configure the circuit in one stage, and it is possible to correct the intermediate pin distortion satisfactorily even for various video signals with low power consumption.

[0015]

That is, in the present invention, an S-shaped correction capacitor is connected in series to a horizontal deflection coil, and a series circuit including a capacitance component is connected in parallel to the S-shaped correction capacitor. A parallel circuit of a switch element and a diode is connected between the capacitive component and the ground, and the switch element is turned off in a predetermined period for each horizontal deflection.

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an example of a horizontal deflection circuit according to the present invention.

In FIG. 1, a transistor Tr controlled in a horizontal cycle is provided. This transistor Tr
A diode D and a resonance capacitor Cc are connected in parallel between the collector and the emitter of the. Further, a series circuit of a horizontal deflection coil DY and an S-shaped correction capacitor Cs and a series circuit of a coil HOL and a power source Vcc modulated by a parabolic wave having a vertical period are connected in parallel between the collector and the emitter of the transistor Tr. .

Further, a series circuit of capacitors C1 and C2, which are capacitance components, is connected in parallel to the S-shaped correction capacitor Cs. And, between this capacitor C1 and the ground, that is, in parallel with the capacitor C2, the diode D2
And a MOS switch element SW are connected in parallel. The capacitor C2 is provided for dividing the voltage generated in the capacitors Cs and C1 to prevent a high voltage when it is turned off, and is for the purpose of protection. Therefore, another element such as a resistor may be used, or it may not be provided at all.

Therefore, in this circuit, when the MOS switch element SW is on, the value of the capacitor C1 is added to the value of the S-correction capacitor Cs, and the added value and the resonance frequency of the horizontal deflection coil DY determine the value. The deflection current is passed through the horizontal deflection coil DY. On the contrary,
When the MOS switch element SW is off, a deflection current determined by the resonance frequency of the S-shaped correction capacitor Cs and the horizontal deflection coil DY is supplied to the horizontal deflection coil DY as in the conventional case.

That is, in this circuit, the value of the S-correction capacitor can be set to (= Cs + C1) when the MOS switch element SW is on, and (≈Cs) when the MOS switch element SW is off. As a result, the waveform of the deflection current becomes, for example, as shown in FIG. 2 when the MOS switch element SW is on, and becomes as shown when it is off. Therefore, by switching the MOS switch element SW from ON to OFF, the waveform is changed from to, and the inclination of the deflection current can be steeply controlled.

Further, FIG. 3 shows potential waveforms at various parts. In FIG. 3, A is a gate control signal of the MOS switch element SW, B is a drain voltage of the MOS switch element SW,
C indicates the voltage across the S-correction capacitor Cs. Accordingly, at the timing t1 when the MOS switch element SW is turned off by the gate control signal (A), the MOS switch element SW becomes high impedance and the drain voltage (B) of the MOS switch element SW rises as shown.

The rising peak point of the drain voltage (B) is the point where the deflection current of the horizontal deflection coil DY becomes zero, and then the polarity of the deflection current changes from negative to positive, and the drain voltage (B). Descends as shown. When the drain voltage (B) further drops below ground (0 V) and exceeds the on-voltage of the diode D, the diode D turns on. Therefore, in this circuit, the MOS switch element SW
From the timing t1 when the diode is turned off to the peak point of the drain voltage (B), and the diode D from this peak point.
The times until the timing t2 at which the switch turns on are almost the same.

Further, this operation is performed by the S-shaped correction capacitor C.
What is indicated by the voltage across s is the potential waveform shown in C of FIG. That is, in FIG. 3C, the MOS
OFF period of switch element SW and diode D (t1 →
At t2), the capacitance of the capacitor C1 decreases. At this time, the resonance frequency of the S-correction capacitor Cs + C1 and the horizontal deflection coil DY simultaneously increases, so that the resonance voltage of the S-correction capacitor Cs also sharply changes.

By the way, in the above-described correction of the intermediate pin distortion, the S-shaped correction capacitor C is provided at the center of the screen as described above.
It is necessary to reduce the value of s and partially make the deflection current steep. Therefore, in the circuit of FIG. 1 described above, the MOS switch element SW
By turning off, the inclination of the deflection current can be made steep at this portion, and the waveform shaping of the deflection current can be realized.

Therefore, in this circuit, a capacitance component, a switch element, and a diode are provided in parallel with the S-shaped correction capacitor, and the switch element is turned off during a predetermined period for each horizontal deflection, so that the deflection current of this period is reduced. The slope can be made steep, and the waveform shaping of the deflection current can be realized.

Thus, according to the present invention, it is possible to form a circuit having a two-stage structure in the past from a single-stage circuit, which consumes less power and is controlled by switching. Therefore, it is possible to satisfactorily correct the intermediate pin distortion even for various video signals.

However, in the actual correction of the intermediate pin distortion, if the inclination of the deflection current is made partially steep, the time for one horizontal deflection is shortened. On the other hand, this contradiction can be resolved by increasing the overall pin distortion correction amount and increasing the overall current amplitude value.

Further, FIG. 4 shows an example of the actual off timing. In FIG. 4, the shaded area on the left side of the screen is MOS.
The ON period of the switch element SW, the shaded area on the right is the ON period of the diode D. Then, these are turned off in the intermediate white background portion, and the capacitance value of the S-shaped correction capacitor is reduced.

Therefore, as is clear from FIG. 4, there is no horizontal period in which the entire period is on, and there is always an off timing in order to correct the intermediate pin distortion. However, the invention of the present application does not limit such a control method,
A circuit structure capable of dynamically modulating the S-curve correction amount described above is a first gist.

A specific example of switching will be described below. In FIG. 5, A corresponds to the upper end of the screen, B corresponds to the center, and C corresponds to the lower end, and sawtooth waves having a horizontal cycle are drawn. On the other hand, D indicates a parabolic wave used for pin distortion correction of the vertical period. Then, by inputting these waveforms to the comparator, PWM control signals as shown by A'to C'are formed.

That is, in FIG. 5, the slice level for the sawtooth waves A to C is changed by the parabolic wave D. As a result, the timing of turning off the MOS switch element is controlled. Then, as described above, the diode D is turned on at a timing symmetrical with respect to the off timing with respect to the center of the screen (center of horizontal deflection).

Therefore, in this circuit, the on-timing of the diode D is automatically controlled by accurately controlling the off-timing of the above-mentioned MOS switch element, and the PWM as shown in the above A'-C '. The control signal of is accurately formed. By performing the control shown in FIG. 4 using the PWM control signal, it is possible to excellently correct the intermediate pin distortion.

Thus, according to the horizontal deflection circuit described above, the S-correction capacitor is connected in series to the horizontal deflection coil, and the series circuit including the capacitance component is connected in parallel to the S-correction capacitor. A parallel circuit of a switch element and a diode is connected between the capacitance component and ground,
By turning off the switch element during a predetermined period for each horizontal deflection, it is possible to correct the intermediate pin distortion even with respect to various video signals with a simple configuration and low power consumption. .

[0034]

According to the present invention, a capacitance component, a switch element, and a diode are provided in parallel with the S-shaped correction capacitor, and the switch element is turned off during a predetermined period for each horizontal deflection. The inclination of the deflection current can be made steep, and the waveform shaping of the deflection current can be realized.

Thus, according to the present invention, it is possible to form a circuit having a two-stage configuration in the past from a one-stage circuit, which consumes less power and is controlled by switching. Therefore, it is possible to satisfactorily correct the intermediate pin distortion even for various video signals.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an example of a horizontal deflection circuit to which the present invention is applied.

FIG. 2 is a diagram for explaining the operation.

FIG. 3 is a diagram for explaining the operation.

FIG. 4 is a diagram for explaining the operation.

FIG. 5 is a diagram for explaining the operation.

FIG. 6 is a configuration diagram of a conventional horizontal deflection circuit.

FIG. 7 is a diagram for explaining intermediate pin distortion.

FIG. 8 is a configuration diagram of a conventional horizontal deflection circuit.

[Explanation of symbols]

 Tr Transistor controlled by horizontal cycle D, D2 diode Cc Resonant capacitor DY Horizontal deflection coil Cs S-correction capacitor HOL coil Vcc Power supply modulated by parabolic wave of vertical cycle C1 Capacitor C2 Capacitor SW MOS switch element

Claims (4)

[Claims] 1. A horizontal deflection coil is connected in series with an S-shaped correction capacitor, and a series circuit including a capacitance component is connected in parallel to the S-shaped correction capacitor, and between this capacitance component and ground. A horizontal deflection circuit characterized in that a parallel circuit of a switch element and a diode is connected to, and the switch element is turned off in a predetermined period for each horizontal deflection. 2. The horizontal deflection circuit according to claim 1, wherein the timing of turning off the switch element is delayed in the vicinity of the upper and lower ends in the vertical deflection direction and is advanced in the middle portion of the vertical deflection direction. And horizontal deflection circuit. 3. The horizontal deflection circuit according to claim 1, wherein the switch element is turned off by a rectangular wave in which a sawtooth wave having a horizontal period is discriminated by a parabolic wave having a vertical period. Horizontal deflection circuit. 4. The horizontal deflection circuit according to claim 1, wherein the diode is turned on at a timing symmetrical with respect to a timing of turning off the switch element with respect to a center of the horizontal deflection. .