KR19980082289A - Polycrystalline Silicon Thin Film Transistor and Manufacturing Method Thereof - Google Patents
Polycrystalline Silicon Thin Film Transistor and Manufacturing Method Thereof Download PDFInfo
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- KR19980082289A KR19980082289A KR1019970017101A KR19970017101A KR19980082289A KR 19980082289 A KR19980082289 A KR 19980082289A KR 1019970017101 A KR1019970017101 A KR 1019970017101A KR 19970017101 A KR19970017101 A KR 19970017101A KR 19980082289 A KR19980082289 A KR 19980082289A
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- 239000010409 thin film Substances 0.000 title claims abstract description 49
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title abstract description 7
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 12
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 11
- 239000010408 film Substances 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 238000010956 selective crystallization Methods 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 238000000206 photolithography Methods 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 238000001179 sorption measurement Methods 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- 239000011521 glass Substances 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims description 2
- 239000010453 quartz Substances 0.000 claims description 2
- 239000012212 insulator Substances 0.000 claims 1
- 239000011229 interlayer Substances 0.000 claims 1
- 238000002834 transmittance Methods 0.000 abstract description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000009832 plasma treatment Methods 0.000 description 3
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
- H01L29/78666—Amorphous silicon transistors with normal-type structure, e.g. with top gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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Abstract
본 발명은 기존의 다결정 실리콘 박막트랜지스터에서의 누설전류를 감소시키는 새로운 구조의 다결정 실리콘 박막트랜지스터와 그 제조방법에 관한 것이다.The present invention relates to a polycrystalline silicon thin film transistor having a novel structure for reducing leakage current in an existing polycrystalline silicon thin film transistor and a method of manufacturing the same.
다결정 박막트랜지스터의 단점은 OFF 상태에서 누설전류가 크고 불균일하다는데 있다. 이를 개선하기 위하여 기존에는 트랜지스터 구조에서 드레인과 채널 사이에 오프셋(offset) 저항구조를 이용하였으나 이 경우 누설전류와 ON 전류가 함께 낮아지는 결과가 야기된다. 또 다른 구조는 다결정 박막트랜지스터를 두개이상 직립연결하는 멀티게이트(multi gate) 구조나 멀티게이트와 오프셋의 혼용구조로 이 경우 광투과 개구율이 낮아지는 단점이 있다. 본 발명에서는 박막 채널에 다결정 박막을 채우고 드레인과 드레인 부근에서 비정질 박막으로 구성하여 채널 영역에 비정질과 다결정을 동시에 이용함으로써 누설전류를 비정질 박막트랜지스터 수준에 가깝게 낮추면서도 ON 전류를 다결정 박막트랜지스터 수준으로 높게 유지시키는 새로운 박막트랜지스터 구조를 발명하였다.The disadvantage of polycrystalline thin film transistors is that the leakage current is large and uneven in the OFF state. In order to improve this, in the conventional transistor structure, an offset resistance structure is used between the drain and the channel, but in this case, the leakage current and the ON current are lowered together. Another structure is a multi-gate structure in which two or more polycrystalline thin film transistors are connected upright, or a mixed structure of multi-gate and offset, in which case the light transmittance is lowered. In the present invention, the thin film channel is filled with a polycrystalline thin film and is composed of an amorphous thin film near the drain and the drain, thereby simultaneously using amorphous and polycrystalline in the channel region, thereby reducing the leakage current close to the amorphous thin film transistor level while increasing the ON current to the polycrystalline thin film transistor level. A new thin film transistor structure is maintained.
Description
본 발명은 기존의 다결정 실리콘 박막트랜지스터에서의 누설전류를 감소시킴을 목적으로 하는 새로운 구조의 다결정 실리콘 박막트랜지스터 및 그 제조방법에 관한 것이다.The present invention relates to a polycrystalline silicon thin film transistor having a new structure, and a method of manufacturing the same, for the purpose of reducing leakage current in an existing polycrystalline silicon thin film transistor.
일반적으로 다결정 박막트랜지스터는 도 3과 같은 구조로 이루어져 있으며 현재 소자로써의 가장 큰 문제는 누설전류가 매우 크면서 그 크기가 재현성이 나쁘다는데 있다. 반면에 비정질 실리콘 박막 트랜지스터는 Avitive Matrix Liquid Crystal Display(AMLCD)에 이미 상용화 되어 있으나 동작 상태의 전류(on-current)가 낮아 트랜지스터 면적이 커야 하기 때문에 상대적으로 개구율이 낮아진다.In general, the polycrystalline thin film transistor has a structure as shown in FIG. 3, and the biggest problem as the current device is that the leakage current is very large and its size is poor in reproducibility. Amorphous silicon thin film transistors, on the other hand, are already commercially available in an Avitive Matrix Liquid Crystal Display (AMLCD).
FR-2191578(1994)은 누설전류를 줄이기 위하여 게이트(gate)의 길이를 채널(channel) 길이에 비하여 작게하여 오프셋(offset) 식각을 이용하는 방법에 관한 것이고, JP07022627(1995) 멀티게이트(multi gate)를 이용하여 누설전류를 줄이는 방법에 관한 것이다.FR-2191578 (1994) relates to a method of using offset etching by reducing the length of the gate compared to the channel length in order to reduce the leakage current, JP07022627 (1995) multi-gate It relates to a method of reducing the leakage current by using.
Fabrication of the laser annealed poly-Si TFT with vertical a-Si:H offest layer, 이경하 등 The 4th Koean Conference on Semiconductors, p.201은 step coverage가 뛰어난 화학증착법을 이용하여 도우핑이 안된 a-Si:H와 n+ a-Si:H를 순차적으로 증착함으로써 드레인(drain)과 채널 간에 비정질 Si 오프셋 구조를 도입하여 저항을 높여 누설전류의 감소를 꾀한 TFT의 방법에 관한 것이다.Fabrication of the laser annealed poly-Si TFT with vertical a-Si: H offest layer, Lee Kyung-ha et al. The 4th Koean Conference on Semiconductors, p.201, is an undoped a-Si: H method using chemical vapor deposition with excellent step coverage. The present invention relates to a TFT method in which an amorphous Si offset structure is introduced between a drain and a channel by sequentially depositing and n + a-Si: H to increase resistance and reduce leakage current.
다결정 박막트랜지스터와 비정질트랜지스터의 일반적인 전류-전압 특성은 도 4와 같다. 다결정 트랜지스터의 누설전류는 드레인과 다결정실리콘 채널 사이의 공핍층에서의 결함에 의해 전자-정공의 생성으로 야기되며 이를 감소시키기 위해 드레인과 다결정실리콘 채널사이에 다결정 박막이 저항형식으로도 도입되기도 하고 (오프셋 구조), 게이트 여러개를 직렬로 연결한 멀티게이트(multi gate)를 개발하기도 한다.General current-voltage characteristics of the polycrystalline thin film transistor and the amorphous transistor are shown in FIG. 4. The leakage current of the polycrystalline transistor is caused by the generation of electron-holes by the defect in the depletion layer between the drain and the polysilicon channel, and in order to reduce the polycrystalline thin film is introduced in the resistive form between the drain and the polysilicon channel ( Offset structure), and multi-gates in which several gates are connected in series.
다결정 박막트랜지스터의 단점은 OFF 상태에서 누설전류가 크고 불균일하다는데 있다. 이를 개선하기 위하여 기존에는 트랜지스터 구조에서 드레인과 채널 사이에 오프셋 저항구조를 이용하였으나 이 경우 누설전류와 ON 전류가 함께 낮아지는 결과가 야기된다. 또다른 구조는 다결정 박막트랜지스터를 두개이상 직렬 연결하는 멀티 게이트 구조나 멀티게이트와 오프셋의 혼용구조로 이 경우 광투과 개구율이 낮아지는 단점이 있다. 본 발명에서는 채널 영역에 비정질과 다결정을 동시에 이용함으로써 누설전류를 비정질 박막트랜지스터 수준에 가깝게 낮추면서도 ON 전류를 다결정 박막트랜지스터의 수준으로 높게 유지시키는 새로운 박막트랜지스터 구조를 착안하여 본 발명을 완성하였다.The disadvantage of polycrystalline thin film transistors is that the leakage current is large and uneven in the OFF state. In order to improve this, in the conventional transistor structure, an offset resistance structure is used between the drain and the channel, but in this case, the leakage current and the ON current are lowered together. Another structure is a multi-gate structure in which two or more polycrystalline thin film transistors are connected in series, or a mixed structure of multi-gate and offset, in which case the light transmittance is lowered. In the present invention, by using the amorphous and polycrystalline at the same time in the channel region, a novel thin film transistor structure that maintains the ON current at the level of the polycrystalline thin film transistor while maintaining the leakage current close to the amorphous thin film transistor level, the present invention was completed.
도 1은 본 발명의 다결정 실리콘 박막트랜지스터의 구조1 is a structure of a polycrystalline silicon thin film transistor of the present invention
도 2는 본 발명의 다결정 실리콘 박막트랜지스터의 제조 공정도2 is a manufacturing process chart of the polycrystalline silicon thin film transistor of the present invention
도 3은 종래의 다결정 실리콘 박막트랜지스터의 구조3 is a structure of a conventional polycrystalline silicon thin film transistor
도 4는 다결정 박막 트랜지스터와 비정질 박막트랜지스터의 일반적인 전류, 전압특성4 shows general current and voltage characteristics of a polycrystalline thin film transistor and an amorphous thin film transistor.
앞 도 3과 같이 다결정 박막 트랜지스터 드레인과 다결정실리콘 채널 사이에 오프셋 다결정 박막저항이 도입될 경우 필연적으로 누설전류는 약간 감소하기는 하나 감소폭이 크지 않고, 재현성이 없으며 동작전류(on-current)가 크게 감소하게 된다. 반면에 비정질 실리콘은 누설전류가 아주 낮고 재현성이 좋은 장점을 갖고 있다. 본 발명에서는 다결정실리콘의 누설전류를 비정질 실리콘의 수준으로 감소시키는 방안으로서 도 1과 같이 그 구조를 구성하게 되면 누설전류를 감소시킬 수 있다.As shown in FIG. 3, when an offset polycrystalline thin film resistor is introduced between the polycrystalline thin film transistor drain and the polysilicon channel, the leakage current necessarily decreases slightly, but the reduction is not large, the reproducibility is high, and the on-current is large. Will decrease. On the other hand, amorphous silicon has the advantage of very low leakage current and good reproducibility. In the present invention, as a method of reducing the leakage current of polysilicon to the level of amorphous silicon, as shown in FIG. 1, the leakage current can be reduced.
도 1에서는 소스영역과 소스 영역을 포함한 대부분의 채널은 다결정 실리콘 박막으로 구성되어 있으며 드레인과 드레인부근에서의 채널 일부는 비정질 실리콘 박막으로 구성된 구조이다. 이 경우 드레인 영역 부근에서 생기는 누설전류를 비정질 박막 트랜지스터의 일부를 적용함으로써 비정질 트랜지스터의 값 부근까지 낮출 수 있게 될 것이다. 채널의 일부가 비정질로 구성되어 있어 동작전류는 떨어질 수 있으나 다결정 트랜지스터에서는 오프셋 구조저항이 존재하기 때문에 오프셋 저항이 있는 구조와 비교하면 동작전류는 크게 감소하지는 않을 것으로 기대된다.In FIG. 1, most of the channel including the source region and the source region is composed of a polycrystalline silicon thin film, and a portion of the channel near the drain and the drain is composed of an amorphous silicon thin film. In this case, by applying a part of the amorphous thin film transistor to the leakage current generated near the drain region, it will be possible to lower the vicinity of the value of the amorphous transistor. Because some of the channels are amorphous, the operating current may drop. However, because the offset structure resistance exists in the polycrystalline transistor, the operating current is not expected to decrease significantly compared to the structure having the offset resistance.
이 구조는 사용함으로써 박막 트랜지스터외 특성이 안정화되고 재현성이 있을 것으로 기대되며 그 결과 pixel에서의 트랜지스터뿐만 아니라 안정된 주변회로용 트랜지스터로도 적용이 가능할 것으로 기대된다. 도 2는 본 발명의 박막 트랜지스터구조인 도 1을 제조하는 방법을 도시적으로 나타낸 것이다. 제조방법은 SiO2마스크를 비정질 박막위에 형성하여 자기정렬 방식에 의해 선택 결정화시키는 방법을 제안하였다.By using this structure, it is expected that the characteristics other than the thin film transistor will be stabilized and reproducible, and as a result, it can be applied not only to the transistor in the pixel but also to the transistor for the stable peripheral circuit. FIG. 2 illustrates a method of manufacturing FIG. 1, which is a thin film transistor structure of the present invention. In the manufacturing method, a method of forming a SiO 2 mask on an amorphous thin film and performing selective crystallization by a self-aligning method has been proposed.
[제1공정: 비정질 Si, SiO2증착][First Step: Deposition of Amorphous Si, SiO 2 ]
유리, 석영, 실리콘상의 열적산화물(thermal oxide:SiO2)위에 비정질 실리콘 박막을 중착하고 그 위에 실리콘 산화막을 증착한다.A thin film of amorphous silicon is deposited on thermal oxide (SiO 2 ) on glass, quartz, and silicon, and a silicon oxide film is deposited thereon.
[제2공정: 선택 결정화 영역 정의][Step 2: Define Selective Crystallization Region]
결정화시키는 영역율 실리콘 산화막외 사진식각공정을 이용하여 정의한다.It is defined using the area ratio silicon oxide film etch process which crystallizes.
[제3공정: 금속흡착 또는 Oxygen Plasma 처리][3rd step: metal adsorption or Oxygen Plasma treatment]
금속흡착은 금속율 spin coating을 이용해서 표면에 흡착시킨다. 이때 Si 표면에는 흡착이 되고 SiO2위에는 흡착이 되지 않는다.Metal adsorption is adsorbed on the surface by using a metal spin coating. At this time, adsorption is performed on the surface of Si and not on SiO 2 .
Oxygen plasma 처리는 oxygen plasma에 노출시킨다. 그러면 Si 표면은 plasma에 노출되나 SiO2가 위에 있는 경우는 plasma에 노출되지 않는다.Oxygen plasma treatment is exposed to oxygen plasma. The Si surface is then exposed to the plasma, but not on the plasma if SiO 2 is on top.
[제4공정: 선택적 결정화][Step 4: Selective Crystallization]
금속이 흡착된 상태로 열처리를 하면, 금속이 흡착된 영역은 결정화가 되어 다결정 실리콘이 되고, 금속이 흡착되지 않은 영역은 결정화가 되지 않아 비정질이 된다.When the heat treatment is performed in a state in which the metal is adsorbed, the region where the metal is adsorbed is crystallized to form polycrystalline silicon, and the region where the metal is not adsorbed is not crystallized and becomes amorphous.
Oxygen plasma 처리를 하면 plasma에 노출된 부분은 결정화가 되고, 노출되지 않은 부분은 결정화가 되지 않는다.Oxygen plasma treatment results in crystallization of the exposed part of the plasma and no crystallization of the unexposed part.
[제5공정: 소자 활성화영역 정의][Step 5: Defining device activation region]
사진식각공정을 이용하여 소자 활성영역을 정의한다. 이때 다결정 실리콘영역과 비정질 실리콘영역이 함께 포함되도록 한다.A photolithography process is used to define the device active region. In this case, the polycrystalline silicon region and the amorphous silicon region are included together.
[제6공정: 게이트 산화물(SiO2), 게이트 실리콘(Si) 증착][Sixth Step: Gate Oxide (SiO 2 ), Gate Silicon (Si) Deposition]
게이트 산화물(SiO2)과 게이트용 다결정 실리콘(Si)을 증착한다Deposit gate oxide (SiO 2 ) and polycrystalline silicon (Si) for the gate
[제7공정: 게이트 n+ 주입][7th Step: Gate n + Injection]
게이트의 저항을 낮추기 위해 이온주입이나 이온샤워 방법을 이용해 P나 As를 주입한다.In order to lower the resistance of the gate, P or As is injected by using an ion implantation or an ion shower method.
[제8공정: 게이트 정의][Step 8: Gate Definition]
사진식각방법을 이용해 게이트를 정의한다. 이때 대부분은 다결정 실리콘 위에 형성되고 드레인끝 일부분만 비정질 실리콘 위에 형성한다.The gate is defined using photolithography. At this time, most of them are formed on the polycrystalline silicon and only a part of the drain end is formed on the amorphous silicon.
[제9공정: S/D 주입][Step 9: S / D Injection]
S/D의 저항을 낮추기 위해 이온주입이나 이온샤워 방법을 이용해 P나 As를 주입한다.In order to lower the resistance of S / D, P or As is injected by using ion implantation or ion shower method.
[제10공정: 산화물 증착][Step 10: Oxide Deposition]
표면보호(passivation)용 산화물을 증착하고 사진식각방법을 이용하여 금속접촉을 형성시킨다.Oxides for passivation are deposited and metal contacts are formed using photolithography.
본 발명은 다결정 박막트랜지스터의 가장 큰 문제점인 누설전류를 박막트랜지스터의 드레인 영역을 비정질로 구성하여 누설전류를 감소시킬 수 있다. 본 발명을 이용하면 비정질 박막트랜지스터와 거의 비슷한 누설전류로 다결정 박막트랜지스터의 높은 이동도를 얻을 수 있어 다결정 박막트랜지스터의 장점인 주변회로의 내장과, 박막트랜지스터의 소형화물, 오프셋 구조에서의 ON 전류감소나 멀티 게이트에서의 크기 증가와 같은 문제없이, 실현시킬 수 있을 것으로 기대된다.The present invention can reduce the leakage current by configuring the leakage current, which is the biggest problem of the polycrystalline thin film transistor, as the amorphous drain region of the thin film transistor. According to the present invention, the high mobility of the polycrystalline thin film transistor can be obtained with a leakage current almost similar to that of the amorphous thin film transistor, so that the built-in peripheral circuit, which is an advantage of the polycrystalline thin film transistor, and the ON current reduction in the small size and offset structure of the thin film transistor It is expected that it can be realized without problems such as the size increase in the multi gate.
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| US9391132B2 (en) | 1999-10-26 | 2016-07-12 | Semiconductor Energy Laboratory Co., Ltd. | Light emitting device |
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| KR101774478B1 (en) | 2010-10-22 | 2017-09-05 | 삼성디스플레이 주식회사 | Thin film transistor and manufacturing method thereof |
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| US9391132B2 (en) | 1999-10-26 | 2016-07-12 | Semiconductor Energy Laboratory Co., Ltd. | Light emitting device |
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