KR19980078285A - Sort method - Google Patents

Abstract

The present invention relates to a method of aligning a semiconductor device, comprising: a first step of forming a first measurement pattern on a peripheral region around a device region on a substrate; Forming a first insulating film on the substrate so that the first measuring pattern is covered; and having a smaller shape and smaller shape than the first measuring pattern in the first measuring pattern on the first insulating film; Forming a second process; And a third step of performing the second step a plurality of times. Therefore, since the measurement patterns are formed in the previous measurement patterns, the size of the chip can be reduced by suppressing an increase in the area of the peripheral region except the device region.

Description

Sort method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an alignment method of a semiconductor device, and more particularly, to an alignment method of measuring alignment by forming a measurement pattern in a peripheral region when forming a transistor in an element region.

As semiconductor devices become more integrated and denser, the size of the unit element is reduced, and as a result, the line width of the conducting wire is reduced. Therefore, accurate mask alignment is required in the manufacturing process of the semiconductor device. Mask alignment aligns the mask to the previous pattern formed on the substrate, affecting the reliability and production yield of the device.

When the thin film or the pattern is formed in the device region of the substrate, the mask is aligned based on a measurement pattern for measuring the alignment degree previously formed in the scribe line, which is a peripheral region excluding the device region.

1A to 1C are process charts showing the alignment method of a semiconductor device according to the prior art.

Referring to FIG. 1A, a material for forming a pattern on the substrate 11, for example, a conductive material such as a metal, such as polycrystalline silicon or aluminum doped with impurities, or insulation such as silicon oxide Deposit the material. Subsequently, the material for forming the pattern is patterned by photolithography to form a pattern in the device region (not shown), thereby forming the first measurement pattern 13 on the surrounding scribe line. At this time, the first measurement pattern 13 is formed to have a rectangular band shape.

Referring to FIG. 1B, the first insulating layer 15 is formed on the substrate 11 to cover the pattern on the device region and the first measurement pattern 13 on the scribe line, which is a peripheral region. Then, the second measurement patterns 17 and 18 are formed by depositing and patterning a conductive material such as a metal such as polycrystalline silicon or aluminum doped with impurities. The second measurement pattern 17 is formed in a rectangular parallelepiped shape and is positioned at the center of the first measurement pattern 13 having a rectangular band shape to measure an alignment degree by measuring a separation distance. In addition, the second measurement pattern 18 is formed in the same square band shape next to the first measurement pattern 13.

Referring to FIG. 1C, a second insulating film 19 is formed on the first insulating film 15 to cover the pattern on the device region and the second measurement pattern 17 and 18 on the scribe line, which is a peripheral region. . In addition, a third measurement pattern 21 or 22 is formed by depositing and patterning a conductive material such as a metal such as polycrystalline silicon or aluminum doped with impurities. The third measurement pattern 21 is formed in a rectangular parallelepiped shape in the same manner as the second measurement pattern 17 and is positioned at the center of the second measurement pattern 18 having a rectangular band shape to measure the distance of alignment. do. In addition, the third measurement pattern 22 is formed in the same rectangular band shape as the first and second measurement patterns 13 and 18.

The third measurement pattern 22 formed above is used when measuring the degree of alignment of a measurement pattern (not shown) to be formed later in the central portion. Then, the above-described process is repeated to measure the degree of alignment of the measurement patterns to be formed later.

However, the conventional method of aligning the semiconductor device described above has a problem in that the size of the chip is increased because the number of measurement patterns increases as the stacked layers increase, requiring a peripheral area having a large area.

Accordingly, an object of the present invention is to provide an alignment method capable of reducing the size of a chip by suppressing an increase in the area of a peripheral area even when a plurality of layers are stacked to increase the number of measurement patterns.

An alignment method according to the present invention for achieving the above object comprises a first step of forming a first measurement pattern on the peripheral region around the element region on the substrate; Forming a first insulating film on the substrate so that the first measuring pattern is covered; and having a same shape and a smaller shape than the first measuring pattern in the first measuring pattern on the first insulating film; Forming a second process; And a third step of performing the second step a plurality of times.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 (A) to (C) are process charts showing the alignment method of a semiconductor device according to the prior art.

2A to 2C are process charts showing the alignment method of the semiconductor device according to the present invention.

* Brief description of symbols for main parts of the drawings

31 substrate, 33 first measurement pattern, 35 first insulating film, 37 second measurement pattern, 39 second insulating film, 41 third measurement pattern

2A to 2C are process charts showing the alignment method of the semiconductor device according to the present invention.

Referring to FIG. 2A, a material for forming a pattern on the substrate 31, for example, a conductive material such as a metal, such as polycrystalline silicon or aluminum doped with impurities, or insulation such as silicon oxide Deposit the material. Then, the deposited material for forming the pattern is patterned by photolithography to form a pattern in the device region (not shown), thereby forming the first measurement pattern 33 on the surrounding scribe line. At this time, the first measurement pattern 33 is formed to have a square band shape.

Referring to FIG. 2B, the first insulating layer 35 is formed on the substrate 31 to cover the pattern on the device region and the first measurement pattern 33 on the scribe line, which is a peripheral region. In addition, a second measurement pattern 37 is formed by depositing and patterning a conductive material such as a metal such as polycrystalline silicon or aluminum doped with impurities. The second measurement pattern 37 has a rectangular band shape having a size smaller than that of the first measurement pattern 33 and is positioned in the first measurement pattern 33 to measure the degree of alignment. In the above, the alignment degree of the second measurement pattern 37 is measured by measuring the separation distance between the first measurement pattern 33 and the second measurement pattern 37, which is a reference for the measurement.

Referring to FIG. 2C, a second insulating layer 39 is formed on the first insulating layer 35 to cover the pattern on the element region and the second measurement pattern 37 on the scribe line, which is a peripheral region. In addition, a conductive material such as a metal such as polysilicon or aluminum doped with impurities is deposited and patterned to form the first measurement pattern 41 in the second measurement pattern 37. In the above, the third measurement pattern 41 is formed in a rectangular band shape of a small size to be located in the second measurement pattern 37. In the above, the alignment measurement of the third measurement pattern 41 is the same as the alignment measurement of the second measurement pattern 37 between the second measurement pattern 37 and the third measurement pattern 41 which are a reference when measuring This is achieved by measuring the separation distance of. In the above, the second measurement pattern 37 not only measures the degree of alignment of itself based on the first measurement pattern 33, but also serves as a reference for measuring the degree of alignment of the third measurement pattern 41. Accordingly, a pattern for measuring the alignment of the second measurement pattern 37 by measuring the separation distance from the first measurement pattern 33 and a pattern used as a reference for measuring the alignment of the third measurement pattern 41 thereafter. Since it is not formed separately, the area of the peripheral area is suppressed from increasing.

Then, the above-described process is repeated to measure the degree of alignment of the measurement patterns to be formed later.

Therefore, since the present invention forms the measurement patterns in the previous measurement patterns, the size of the chip can be reduced by suppressing an increase in the area of the peripheral region except the device region.

Claims (2)

A first step of forming a first measurement pattern on a peripheral region around the element region on the substrate; Forming a first insulating film on the substrate so that the first measuring pattern is covered; and having a smaller shape and smaller shape than the first measuring pattern in the first measuring pattern on the first insulating film; Forming a second process; And a third step of performing the second step a plurality of times. The method according to claim 1, And aligning the first and second measurement patterns into a rectangular band shape.