KR19980067614A - Network Collision Signal Detector - Google Patents

Abstract

The present invention relates to an apparatus for detecting network collision signals, which requires at least 512 bit time x 16 times = 8192 bit time to detect network faults. The problem was that it took a lot of time to get there.

Accordingly, the present invention has been made to solve the above-mentioned problems, and provides a circuit for generating and transmitting a link pulse by using a collision signal of a network, and determining a failure by detecting the transmitted link pulse. Detecting whether a failure is detected by detecting the transmitted link pulse, there is an effect that the time for detecting the failure is shortened.

Description

Network Collision Signal Detector

The present invention relates to a network collision signal detection device, and more particularly, to a network collision signal detection device that detects a network signal in a shortest time and generates an error signal when the network is physically disconnected and cannot be transmitted or received. .

1 is a block diagram of a conventional network collision signal detection circuit, comprising: a detection circuit unit 10 for detecting the beginning or the end of a network collision signal as shown therein; A quaternary counter circuit unit 11 for counting the number of network collisions; A delay circuit section 12 for delaying at least 512 bit time after the collision of the network; The conventional operating process configured as described above is configured by the retry circuit unit 13 which automatically retransmits when the NACK signal is received or the ACK signal is not sent even after a certain time has elapsed. .

The detection circuit unit 10 detects the start or end of a collision signal on the network, and the quaternary counter circuit unit 11 counts how many collisions have occurred and generates a network fault signal when 16 consecutive collisions occur. The delay circuit section 12 delays a minimum 512-bit time from the start or end of the collision signal detected by the detection circuit section 10 to the retry circuit section 13, and the retry circuit section 13 The collision signal is retransmitted until 16 consecutive collisions occur and the network fault signal is generated in the quaternary counter circuit unit 11.

As described above, the conventional device takes at least 512 bit time x 16 = 8192 bit time until the network fault is detected. Therefore, in the high-speed network operation, a long time is required to detect a fault signal of the network. There was a problem.

Accordingly, the present invention has been made to solve the above-mentioned problems, and provides a circuit for generating and transmitting a link pulse using a collision signal of a network, and for determining a failure by detecting the transmitted link pulse. There is a purpose.

1 is a block diagram of a conventional network collision signal detection circuit

2 is a block diagram of a network collision signal detection device of the present invention

3 is a configuration diagram of a link pulse generator of the present invention;

4 is an output waveform diagram of a link pulse generator;

Explanation of symbols on the main parts of the drawings

10 detecting circuit portion 11: quaternary counter circuit portion

12 delay circuit unit 13 retry circuit unit

20: link pulse generator 21: link pulse detection circuit

22: Multiplexer 23: Buffer

The configuration of the present invention for achieving the above object comprises: a detection circuit unit for detecting the start or end of the network collision signal; A link pulse generator for generating a link pulse from a start point and an end point of a network collision and transmitting the link pulse to a network medium; A link pulse detection circuit section for receiving a link pulse transmitted from a network medium; It is composed of a multiplexer for determining whether a network fails by the link detection signal, which will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram of the network collision signal detecting apparatus of the present invention. As shown in FIG. 2, the detection circuit unit 10 detects the start or end of a collision signal on a network, and the link pulse generator 20 Generates a link pulse from the beginning and the end of a network collision to transmit the link pulse to a network medium, and detects the link pulse transmitted from the network medium by the link pulse detection circuit 21 to detect a signal (fault). Or transmission) to the multiplexer 22, and the multiplexer 22 determines whether or not the network is broken by the detection signal, and if the failure is determined, the network operation is stopped.

FIG. 3 is a block diagram of a link pulse generator of the present invention, and FIG. 4 is an output waveform diagram of the link pulse generator. As shown in FIG. 4, the link pulse generator includes a combination of odd N NAND gates. The process of NAND combining the first input (A) and performing the NAND combination again is the N-1th process, and the Nth NAND gate is the first input of the output (A ') of the N-1th NAND gate. Outputs by combining NAND.

As described above, the network collision signal detecting apparatus of the present invention generates and transmits a link pulse using a collision signal of a network, and determines whether or not a failure is detected by detecting the transmitted link pulse, thereby reducing the time for detecting the failure. It works.

Claims (2)

Detection circuitry for detecting the start or end of a network collision signal; A link pulse generator for generating a link pulse from a start point and an end point of a network collision and transmitting the link pulse to a network medium; A link pulse detection circuit section for receiving a link pulse transmitted from a network medium; An apparatus for detecting network collision signals, comprising a multiplexer for determining whether a network has failed by a link detection signal. The network collision signal detection apparatus according to claim 1, wherein the link pulse generator comprises a combination of odd (N) NAND gates.