JP2533228B2 - Operation unit control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention controls the driving of a plurality of display elements provided in an operation unit by a dynamic scan method by transmitting data between a main control unit and the operation unit. Operation unit control device.

[Conventional technology]

In copying machines, facsimiles, etc., the display of various data and the input with operation keys, etc. are performed by the operation unit. Also, this operation unit can be used by the microprocessor (hereinafter referred to as CPU) of the main control unit of the main body of the device. The display elements are sequentially driven and controlled by a dynamic scan method for dynamic display.

By the way, if noise etc. occurs during the transmission of data from the main control unit to the operation unit, incorrect data will be displayed, and the operation unit will receive an error (reception error).
The presence or absence of is detected and the detection result is transmitted to the main control unit. Then, the main control unit confirms the above detection result, and if the data is normally transmitted, the next data is transmitted, while if the data is not normally transmitted, the data is retransmitted. .

[Problems to be Solved by the Invention]

In the above device, the main control unit determines whether to transmit the next data after retransmitting the data after waiting for the detection result of whether or not the transmission data has been transmitted without error. Therefore, it took time to transmit the data. Therefore, in the dynamic scan method, display flicker and a delay in response to key operation occur, and these problems become remarkable especially when the number of displays and operation keys is large.

The present invention has been made in view of the above problems, and the main control unit retransmits data in which a reception error occurs at the time of subsequent data transmission so that the data transmission is not interrupted and the transmission rate is lowered as a whole. SUMMARY OF THE INVENTION It is an object of the present invention to provide an operation unit control device which prevents the problem of display flicker and a delay in response to key operation and prevents erroneous display in the case of a reception error.

[Means for solving the problem]

In order to achieve the above object, the present invention provides an operation unit control device for controlling the driving of a plurality of display elements provided in the operation unit by a dynamic scan method by sequentially transmitting data from the main control unit side to the operation unit side. In the operation part side,
Judgment means for judging the presence or absence of a reception error for the reception data, reception error signal transmission means for receiving the presence or absence of the reception error for the previous reception data at the main control unit side at the time of the current data reception, and A display element drive stopping means for stopping the display of the display element for the received data is provided, and the main control section side receives the receiving error signal from the storage means for storing the previous transmitted data and the operation section side. Receiving means, judging means for judging the presence or absence of a receiving error based on the receiving error signal during the current data transmission, and if there is the receiving error, retransmits the previously stored transmitted data at the time of the next data transmission. And a resending means.

[Action]

According to the operation unit control device having the above configuration, the presence or absence of the reception error for the previously received data is transmitted from the operation unit side to the main control unit side at the time of the current data reception. On the main control side,
The previous transmission data is stored, the reception error signal from the operation unit side is received, the presence or absence of the reception error is judged during the current data transmission, and if there is no reception error, the current data transmission Then, the next data is transmitted. On the other hand, if there is the reception error, the previous transmission data is retransmitted at the next data transmission.

Further, if there is the reception error, the driving of the display element provided in the operation unit is stopped, and the display of the received data is stopped.

〔Example〕

FIG. 1 is a block diagram showing a configuration of a main control unit side of an operation unit control device to which the present invention is applied.

The CPU 1 controls the operation of the entire device. The interface circuit 2 guides the display data from the CPU 1 to the display memory 3 and the key data from the key input memory 4 to the CPU 1. The display memory 3 stores the display data from the interface circuit 2. The address generator 5 outputs an address for writing or reading data in the display memory 3 or the key input memory 4. Further, the address generator 5 stores the address corresponding to the previous transmission data as described later. The shift register 6 serially transmits display data and the like from the display memory 3 to the shift register 31 (FIG. 3). The timing generation unit 7 generates a clock signal or the like to generate the shift register 6, the address sequential control unit 8, the error processing unit 9, and the timing controller 33 (the third
Output).

The address sequential control unit 8 selectively sets whether to advance the address output from the address generation unit 5 or to return to the previously transmitted address that has been error-transmitted, according to the error signal from the error processing unit 9. The error processing unit 9 determines the presence or absence of a reception error on the side of the operation unit based on the reception error signal from the shift register 10, and if a reception error occurs, outputs the operation unit reception error signal to the address sequence control unit 8 and Whether or not there is an error in the key data or the like is judged, and if there is a reception error, the main control unit reception error signal is output to the address sequence control unit 8.

The shift register 10 returns serial data such as key data in parallel to output to the key input memory 4 and outputs a reception error signal from the operation unit side to the error processing unit 9. The key input memory 4 temporarily stores the key data from the shift register 10 in association with the address from the address generator 5. The stored key data is read by the address from the address generator 5 and output to the interface circuit 2.

Next, an example of a specific circuit configuration of the address generator 5 and the address order controller 8 will be described with reference to FIG.

OR circuit 11, AND circuit 12, and D flip-flop
Reference numeral 13 constitutes a judgment circuit for judging the presence / absence of a reception error on the operation unit side and the main control unit side. That is, the OR circuit 11
Is an AND circuit that outputs an output corresponding to the main control unit reception error signal d or the operation unit reception error signal e from the error processing unit 9.
It is sent to one input terminal of 12. The AND circuit 12 receives the timing signal c from the timing generator 7 and the OR circuit 11
The output corresponding to the output from is output to the D flip-flop 13. The D flip-flop 13 outputs the output from the AND circuit 12 to the address counter 14 and the address selector 15 at the rising edge of the clock signal a.

The address counter 14 counts the output pulse f of the D flip-flop 13 and outputs an address signal composed of a 3-digit binary code to the input terminals 1B, 2B, 3B of the address selector 15. The address selector 15 displays the address signal from the address counter 14 when the output pulse f from the D flip-flop 13 is high and the address signal from the following D flip-flops 19 to 21 when the output pulse f is low. 3 and the key input memory 4.

The D flip-flops 16 to 18 receive the address signals from the output terminals 1Y, 2Y, 3Y of the address selector 15 as timing signals c.
L flip-flop 19 for one cycle of
Output to ~ 21. D flip-flops 19-21
Is to latch (store) the address signal from the D flip-flops 16 to 18 for one cycle of the timing signal c and output it to the input terminals 1A, 2A, 3A of the address selector 15. That is, the D flip-flops 19-21 output the previous address to the address selector 15.

Next, the block configuration of the operation unit control device according to the present invention on the operation unit side will be described with reference to FIG.

The shift register 31 synchronizes the serial data from the shift register 6 on the main control unit side with the synchronization signal from the timing controller 33 and outputs the parallel display data to the display driver 32. The display driver 32 sequentially drives display elements such as a plurality of 7-segments and LEDs (not shown) based on the address from the address decoder 37 to dynamically display the display data from the shift register 31.

The timing controller 33 generates a synchronization signal or the like based on the clock signal or the like from the timing generator 7 and outputs it to the shift registers 31, 35, the address latch 36 and the error processor 38. The address latch unit 36 generates a scan address from the data from the shift register 31 and outputs it to the address decoder 37. The address decoder 37 designates a display element such as 7 segment or LED to be driven based on the scan address from the address latch section 36.

The error processing unit 38 determines the presence or absence of a reception error for the received data based on the data from the shift register 31,
The presence or absence of this reception error is transmitted as a reception error signal to the main control unit side through the shift register 35, and when there is a reception error, a control signal is output to the display driver 32 to stop the driving of the display element and the received data. I'm trying to stop the display of.

The key input buffer 34 detects the operation state of the operation key and outputs it to the shift register 35 as key data. The shift register 35 converts the key data from the key input buffer 34 and the reception error signal described above into serial data in synchronization with the clock signal from the timing controller 33, and serially transmits the serial data to the shift register 10 on the main control unit side. is there.

Next, the operation of the above configuration will be described with reference to the timing charts of FIGS. 4 and 5. It is assumed that the display data j in each address 0 to 7 is formed of 24 bits B _{0 to} B ₂₃ .

That is, as shown in FIG. 5, when the display data J ₀ at the address 0 is transmitted to the operation unit side, the operation unit side responds to the display data J ₀ at the reception timing of the next display data (address 1) J ₁ . A data signal L ₀ including the presence / absence of a reception error is transmitted to the main control unit side. The data signal L ₀
In response, if there is no reception error, the display data J ₂ of address 2 is transmitted to the operation unit side following the transmission of the display data J ₁ . On the other hand, if there is the above reception error, the above display data
Following the transmission of J ₁ , the display data J ₀ of address ₀ is retransmitted,
After this, the display data J ₂ of address 2 is transmitted.

Next, detailed operation of the main control unit side will be described.

That is, when there is no reception error with respect to the display data J ₀ of the address 0 and when the main control unit side normally receives the data, the display data J ₁ of the address 1 is stored in the shift register 6 by time t _1. The data is transferred and transmitted to the operation unit side, and as shown in FIG. 5, the key data for the previous address 0 and the data signal L ₀ with no reception error are received by the main control unit side. Then, at time t _1, as shown in FIG. 4, the main control unit reception error signal d from the error processing unit 9 remains high, and the operation unit reception error signal e
Remains low. Therefore, the OR circuit 11 outputs a low signal to the AND circuit 12, the AND circuit 12 outputs a high signal to the D flip-flop 13 at time t ₁ when the timing signal c becomes low, and the D flip-flop 13 outputs the clock signal a. The pulse F ₁ is output to the address counter 14 at the time point t ₂ of the rising edge of.

Therefore, the address counter 14 counts the pulse F ₁ and advances the address from address 1 to address 2. On the other hand, when the pulse F ₁ is input to the address selector 15 and the input terminals 1B, 2B, 3B are connected to the output terminals 1Y, 2Y, 3Y, the address signal G ₁ (address 2) from the address counter 14 becomes the address. Instead of 0, it is output from the output terminals 1Y, 2Y, 3Y to the display memory 3. Then, the display data corresponding to the address 2 is read from the display memory 3, transferred to the shift register 6 and converted into serial data h. The transmission of the serial data h starts at time t ₃ when the timing signal c becomes high, that is, the frame sync signal i becomes low during the pulse F ₁ , and the bit B ₀ is synchronized with the serial clock b. It is adapted to be transmitted sequentially from the.

Then, at time t ₄ , the output f of the D flip-flop 13 returns to low. Therefore, the address selector 15 has the input terminal 1
A, 2A, 3A are connected to the output terminals 1Y, 2Y, 3Y, and the previous address 1 from the D flip-flops 19 to 21 is selected by the address selector 15
In order to output to the key input memory 4 through the key input memory 4, the key data corresponding to the address 1 received from the operation unit side is stored in the key input memory 4.

That is, when both the data on the main control unit side and the data on the operation unit side are normally received, the address output from the address selector 15 to the display memory 3 advances by one each time the timing signal c becomes low. .

On the other hand, when there is a reception error for the display data J ₀ of the address 0 and when the main control unit side normally receives the error, the error processing unit 9 outputs only the operation unit reception error signal e, as shown in FIG. Invert to high, as shown by the dashed line E ₁ . Therefore, the OR circuit 11 outputs a high signal, and the AND circuit 12 outputs a low signal. Therefore, the output f of the D flip-flop 13 remains low at the time points t ₂ to t _4, as shown by the chain double-dashed line F ₂ in FIG. Therefore, the address selector 15 converts the input terminals 1A, 2A, 3A into the output terminals 1Y, 2Y,
The address signal G ₂ of the previous address 0 from the D flip-flops 19 to 21 remains output terminals 1Y, 2Y,
3Y is output to the display memory 3, data from the previously transmitted address 0 is transferred from the display memory 3 to the shift register 6, converted into serial data h, and sequentially transmitted to the operation unit side.

When the operation unit side determines a reception error of the display data J ₀ of address 0, the display is stopped to prevent erroneous display.

On the other hand, when the main control unit side determines that there is a reception error, the main control unit reception error signal d becomes low as shown by the chain double-dashed line D ₁ in FIG.
That is, the OR circuit 11 outputs a low signal to the AND circuit 12 regardless of whether the operation unit reception error signal e is high or low. Therefore, the address counter 14 advances the address and outputs it to the display memory 3, as in the case where both the main control unit side and the operation unit side normally receive the data. That is, the serial data h is transmitted to the operation unit side in the address order.

In this way, when the main control unit side determines that there is a reception error, the address is advanced, so there is a reception error on the operation unit side due to a reception error on the main control unit side even though the operation unit side normally receives. Therefore, it can be prevented that the data is retransmitted.

To determine whether there is a reception error, for example, a parity bit may be added when transmitting data, and a parity (reception error) check may be performed based on this parity bit. Data for detection may be added, and determination may be made based on whether or not the error detection data matches on the receiving side, or another method may be used. Further, the present invention can be applied to the case where display data and the like are transmitted in parallel.

Further, since the address and the transmission data are uniquely specified, the address is regarded as the retransmission data and stored in this embodiment, but the same effect can be obtained by storing the data itself.

〔The invention's effect〕

According to the present invention, the main control unit determines whether there is a reception error for the previous transmission during the current data transmission, and if there is a reception error, retransmits the previous transmission data at the time of the next data transmission.
Data transmission from the main control unit side is not interrupted, and the data transmission time can be shortened. For this reason,
In particular, it is possible to reduce the flickering of the display and the response delay to the key operation in the dynamic scan method.

Further, according to the present invention, when there is a reception error, the display of the display element for the received data is stopped, so that an erroneous display in the case of a reception error can be prevented.

Further, even if periodic noise occurs in the dynamic scan method, the data scanning period changes due to the data retransmission, so that only the data of the same address is not destroyed, and the influence of noise can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a main control unit side of an operation unit control device according to the present invention, FIG. 2 is a concrete circuit diagram of an address generation unit and an address order control unit according to the present invention, and FIG. A block diagram of the operation unit side of the operation unit control device, and FIGS. 4 and 5 are timing charts for explaining the operation. 1 ... CPU, 2 ... interface circuit, 3 ... display memory, 4 ... key input memory, 5 ... address generator, 6,10,31,35 ... shift register, 7 ... timing generator, 8 ... Address sequence control section, 9,38 ... Error processing section, 11 ... OR circuit, 12 ... AND circuit, 13,16-21
...... D flip-flop, 14 ...... Address counter, 15
...... Address selector, 32 …… Display driver, 33 …… Timing controller, 34 …… Key input buffer, 36…
… Address latch, 37 …… Address decoder.

Claims (1)

(57) [Claims] 1. An operating section control device for controlling the driving of a plurality of display elements provided in the operating section by a dynamic scan method by sequentially transmitting data from the main control section side to the operating section side, wherein the operating section side comprises: Judgment means for judging the presence or absence of a reception error for the reception data, reception error signal transmission means for transmitting the presence or absence of the reception error for the previous reception data to the main control section side at the time of receiving the current data, and A display element drive stopping means for stopping the display of the display element for the received data is provided, and the main control section side receives the receiving error signal from the storage means for storing the previous transmitted data and the operation section side. Receiving means, judging means for judging the presence or absence of a receiving error based on the receiving error signal during the current data transmission, and the next data if there is the receiving error. Operating unit control device being characterized in that a retransmission means for retransmitting the previous transmission data described above stored at Shin.