KR19980066324A - Method for manufacturing bicymos device - Google Patents

Abstract

The present invention relates to a method for fabricating a bicymos device capable of reducing a collector resistance value of a bipolar transistor, and the method for manufacturing a bicymos device is provided on a semiconductor layer of a first conductive type in order to lower the collector resistance of a bipolar transistor. Growing a buried layer of a high concentration of the second conductive compound and patterning the same; forming a semiconductor substrate applying the buried layer to a predetermined thickness by growing the same material as the semiconductor layer; Defining an active region and an inactive region in the substrate, and forming a device isolation layer, and forming a MOS transistor and a bipolar transistor on the active region.

Description

Method for manufacturing bicymos device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly to a method for manufacturing a BiCMOS device.

In general, BiCMOS technology has widened its application range in ultra-fast, high-performance semiconductor integrated circuits because of its ability to overcome the output limitations of CMOS.

The bicymos circuit is usually composed of a cimos-oriented circuit that maximizes the performance of the cimos.

Therefore, the manufacturing process is comprised of the method of adding and optimizing the necessary bipolar process on the basis of the Seamos process.

In combining different processes of SeaMoose and Bipolar, there is a limit in improving the performance of both devices because the degree of freedom of the process is reduced, but in some cases, one particular process may be advantageous for the other. have.

A good example is the buried layer. 1 is a cross-sectional view of a typical bicymoss device.

Referring to FIG. 1, a bicymoss device is formed between a PMOS transistor T1 and a bipolar transistor T2 between field oxides 104 formed on an inactive region.

The PMOS transistor T1 includes a drain region 105, a source region 106, and a gate electrode 108.

The bipolar transistor T2 includes a base 110, an emitter 112, and a collector 109.

On the other hand, the high concentration en-type buried layers 102A and 102B are generally used in the bipolar process, and are introduced to minimize the resistance of the collector 109 of the bipolar transistor T2.

However, when the buried layers 102A and 102B are provided under the N type well 103A having the PMOS transistor T1, the resistance to latch-up is improved, so the buried layers 102A and 102B are made by In the MOS device, not only the bipolar transistor T2 but also the PMOS transistor T1 plays an important role.

Since the current path of the bipolar transistor T2 is long, a collector 109, which is a high concentration of en-type impurity region in contact with the upper end of the buried layer 103B, is formed to reduce the collector resistance.

However, with the development of the fastest information processing devices, semiconductor devices, which are the core components, are also aiming at high speeds. With the development of technology, semiconductor devices using silicon have recently reached the physical limits of materials. .

An object of the present invention for solving the above problems is to provide a method for manufacturing a bi-CMOS device that can reduce the collector resistance value of the bipolar transistor.

Another object of the present invention is to provide a method for manufacturing a bicymos device that can improve the performance of the device.

1 is a process cross-sectional view of a general bicymos device,

2A through 2D are sequential process cross-sectional views for manufacturing a bicymos device according to an embodiment of the present invention.

According to the technical idea of the present invention for achieving the above object, in order to reduce the collector resistance of the bipolar transistor, a buried material made of a high concentration of the second conductive compound on the first conductive semiconductor layer Patterning a layer after growing the layer, forming a semiconductor substrate on which the same material as the semiconductor layer is grown to apply the buried layer to a predetermined thickness, and defining active and inactive regions on the semiconductor substrate. And forming a separator and forming a MOS transistor and a bipolar transistor on the active region.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In addition, it should be noted that like elements and parts in the drawings represent the same numerals wherever possible.

2 is a sequential process cross-sectional view for manufacturing a bicymos device according to an embodiment of the present invention.

Referring to FIG. 2, first, as shown in FIG. 2A, a high concentration of Y-type Si _1-X Ge _x (0 X d 1) is grown on epitaxial silicon substrate 201, followed by photolithography. A predetermined pattern is formed.

Next, the same conductivity type silicon as in the substrate 201 is crystal-grown, and high concentration en-type buried layers 202A and 202B are applied as shown in FIG. 2B.

Thereafter, as shown in FIG. 2C, an active region and an inactive region are defined on the substrate 201 through a local oxidation process (LOCOS) to form a field oxide layer 204 in the inactive region, and between the field oxide layers 204. En-type wells 103A and 103B are formed in the trenches.

2D, the source region 205, the drain region 206, and the gate electrode 208 of the MOS transistor T1 are formed.

In the region where the bipolar transistor T2 is to be formed, all the manufacturing processes are completed by forming the collector 209, the base 210, and the emitter 212, and then forming a bicymos device and then forming an electrode (not shown). .

Reference numeral 207 denotes a gate oxide film, and spacers are formed on sidewalls of the gate electrode 208.

In the present invention, the buried layers 202A and 202B made of Si _1-X Ge _x (0 Xd 1) are used in place of the conventional en-type buried layers 102A and 102B.

In other words, Ge is mobility of electrons 3900cm ² / Vs of charge, the hole is 1900cm ² / as Vs, more than a compound with Si SiGe is charge mobility of Si even (respectively, 1500cm ² / Vs and 450cm ² / Vs) It has a fast charge mobility characteristic.

Therefore, the buried layers 202A and 202B made of Si _1-X Ge _x (0 Xd 1) can make the collector resistance lower than when using pure Si buried layers 102A and 102B.

In addition, since SiGe has an energy band gap of 1.21.7 eV, which is smaller than the value of Si, SiGe has a carrier confinement effect.

Therefore, the charge via the base 210 flows in the SiGe buried layers 202A and 202B efficiently, as in the HEMT (High Electron Mobility Transistor), so the effect is maximized.

As described above, the present invention has the advantage of reducing the collector resistance of the bipolar transistor, and also has the advantage of improving the performance of the bicymos device.

Claims (5)

A method for fabricating a bicymos device, comprising the steps of: growing a buried layer of a high concentration of a second conductive compound on a first conductive semiconductor layer to pattern the collector resistance of the bipolar transistor; Forming a semiconductor substrate to grow the same material as the semiconductor layer and coating the buried layer to a predetermined thickness, defining an active region and an inactive region on the semiconductor substrate, and forming an isolation layer; Forming a morph transistor and a bipolar transistor on the phase. The method of claim 1 wherein the compound is a compound of silicon and germanium. The method of claim 2, wherein the mixed ratio of germanium is 0 X 1. The method of claim 1, wherein the device isolation layer is a field oxide. The method of claim 1, wherein when the first conductive type is a conductive type made of an impurity, the second conductive type is a conductive type made of an en-type impurity.