KR19980058692A - Morse transistor and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a MOS transistor capable of improving the electrostatic discharge characteristics of the drain region and a manufacturing method thereof, the MOS transistor comprising: a semiconductor substrate; An isolation region formed on the semiconductor substrate by defining an active region and an inactive region; The semiconductor substrate may further include: a gate insulating layer formed to form a trench by etching a channel region of the MOS transistor of the active region to a predetermined thickness, the gate insulating layer including a bottom surface and a sidewall of the trench to partially overlap the active region at both ends of the trench; An n--type low concentration impurity region formed in one side active region of the trench; An n− type first low concentration impurity region formed in the other active region of the trench; An n− type second low concentration impurity region formed in the n− type low concentration impurity region; A gate electrode formed on the gate insulating film while filling the trench; An n + type first high concentration impurity region formed in the n− type first low concentration impurity region; And a structure including an n + type second high concentration impurity region formed in the n− type second low concentration impurity region. By such an apparatus and a manufacturing method, the junction curvature of the n-type source / drain region can be ensured, so that breakdown at a low voltage level can be prevented, and as the junction depth of the drain region becomes deep, drain The electrostatic discharge characteristic of the region is improved.

Description

MOS transistor and method of fabricating the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS transistor and a method for manufacturing the same, and more particularly, to a MOS transistor for improving the electrostatic discharge characteristics of a drain region and a method for manufacturing the same.

Driver ICs are widely used in liquid crystal displays, micoms, and output driver ICs for driving devices in various industries.

Morse transistors are the most commonly used devices for such driver ICs. In order to be used as driver IC devices, MOS transistors have high breakdown voltage, high driver current, and low operating resistance. low on state resistance) is required.

1A to 1D sequentially illustrate a method of manufacturing a MOS transistor for a conventional driver IC as described above.

First, referring to FIG. 1A, a pad oxide layer 12 is formed on a semiconductor substrate 10, and then an active region a and an inactive region b are defined on the pad oxide layer 12 to form a nitride layer pattern. (14) is formed.

Next, in FIG. 1B, the nitride film pattern 14 is used as a mask, and the pad oxide film 12 is oxidized to form a field oxide film 16, and then the nitride film pattern 14 and the field are formed. The pad oxide film on the active region a between the oxide films 16 is removed.

The n-type source / drain regions 18a and 18b are formed by defining regions where the source and drain of the active region a of the semiconductor substrate 10 are to be formed and implanting low concentrations of n-type impurity ions. .

Subsequently, photolithography techniques, which are well known in the art, are performed to form the gate oxide film 20 and the gate electrode 22 on the active region of the semiconductor substrate 10 as shown in FIG. 1C.

Finally, after implanting a high concentration of n + type impurity ions into the region where the source drain of the active region a of the semiconductor substrate 10 is to be formed, and then performing a subsequent thermal process, as shown in FIG. / Drain regions 18a and 18b and n + type source / drain regions 24a and 24b in the n− type source / drain regions 18a and 18b are formed.

However, according to the above-described MOS transistor, the junction depth of the n− type source / drain regions 18a and 18b surrounding the n + type source / drain regions 24a and 24b is not very deep, and also n is used. Since the junction curvature of the type source / drain regions 18a and 18b is small, a problem occurs that causes breakdown at low voltage levels.

In addition, since the junction depth of the drain region is not sufficiently deep, there arises a problem that the electrostatic discharge characteristics of the drain region are degraded when static electricity is applied from the outside.

SUMMARY OF THE INVENTION The present invention proposed to solve the above-mentioned problems is an object of the present invention to provide a MOS transistor and a manufacturing method thereof capable of improving the electrostatic discharge characteristics of the drain region.

1A to 1D are process diagrams sequentially showing a manufacturing method of a conventional MOS transistor.

2 is a cross-sectional view schematically showing the structure of a MOS transistor according to an embodiment of the present invention;

3A through 3D are views sequentially showing a method of manufacturing a MOS transistor according to an embodiment of the present invention.

* Explanation of symbols on the main parts of the drawing

10 semiconductor substrate 12 pad oxide film

14 nitride film pattern 16: field oxide film

18a: n-source region 18b: n-drain region

20 gate oxide film 22 gate electrode

24a: n + source region 24b: n + drain region

(Configuration)

According to the present invention for achieving the above object, a morph transistor includes a semiconductor substrate; An isolation region formed on the semiconductor substrate by defining an active region and an inactive region; The semiconductor substrate may further include: a gate insulating layer formed to form a trench by etching a channel region of the MOS transistor of the active region to a predetermined thickness, the gate insulating layer including a bottom surface and a sidewall of the trench to partially overlap the active region at both ends of the trench; An n--type low concentration impurity region formed in one side active region of the trench; An n− type first low concentration impurity region formed in the other active region of the trench; An n− type second low concentration impurity region formed in the n− type low concentration impurity region; A gate electrode formed on the gate insulating film while filling the trench; An n + type first high concentration impurity region formed in the n− type first low concentration impurity region; And an n + type second high concentration impurity region formed in the n− type second low concentration impurity region.

In a preferred embodiment of the device, the n− type first low concentration impurity region and the n + type first high concentration impurity region are source regions.

In a preferred embodiment of the device, the n− type low concentration impurity region, the n− type second low concentration impurity region, and the n + type second high concentration impurity region are drain regions.

In a preferred embodiment of this device, the n-type low concentration impurity region is formed to a depth in the range of 1.0-1.5 μm.

In a preferred embodiment of this device, the n-type first and second low concentration impurity regions are formed to a depth in the range of 0.5-1.0 mu m.

In a preferred embodiment of this device, the trench is formed to a depth in the range of 0.5-1.0 μm.

In a preferred embodiment of the device, the gate insulating film is formed in the range of 500-1500 kV.

According to the present invention for achieving the above object, a method of manufacturing a MOS transistor, the method comprising: forming a field oxide film by defining an active region and an inactive region of a semiconductor substrate; Implanting n-type impurity ions into one of the active regions of the semiconductor substrate to form an n-type low concentration impurity region; Forming a trench by etching the channel region of the MOS transistor of the active region of the semiconductor substrate to a predetermined thickness; Forming a gate insulating film on the active region, including a bottom surface and a sidewall of the trench so as to overlap a predetermined portion of the active region at both ends of the trench; Filling the trench to form a gate electrode on the gate insulating film; Implanting n-type impurity ions into the active region on one side of the gate electrode to form an n-type first low concentration impurity region; Implanting n-type impurity ions into the n--type impurity region to form an n-type second low concentration impurity region; Implanting n + type impurity ions into the n− type first low concentration impurity region to form an n + type first high concentration impurity region; And implanting n + type impurity ions into the n− type second low concentration impurity region to form an n + type second high concentration impurity region.

In a preferred embodiment of this method, the n− type first low concentration impurity region and the n + type first high concentration impurity region are source regions.

In a preferred embodiment of this method, the n-type impurity region, the n-type second low concentration impurity region, and the n + type second high concentration impurity region are drain regions.

In a preferred embodiment of this method, the n-type impurity ion is phosphorus.

In a preferred embodiment of this method, the n-type impurity ions are implanted in the range of 150-300 keV.

In a preferred embodiment of this method, the n-type impurity ions have a concentration in the range of 1.0E12-1.0E13 ions / cm ² .

In a preferred embodiment of this method, the n--type low concentration impurity region is formed to a depth in the range of 1.0-1.5 μm.

In a preferred embodiment of this method, the n-type impurity ion is phosphorus.

In a preferred embodiment of this method, the n-type impurity ions are implanted in the range of 50-180 keV.

In a preferred embodiment of this method, the n-type impurity ions have a concentration in the range of 3.0E12-1.0E13 ions / cm ² .

In a preferred embodiment of this method, the n-type first and second impurity regions are formed to a depth in the range of 0.5-1.0 μm.

In a preferred embodiment of this method, the n + type impurity ion is arsenic.

In a preferred embodiment of this method, the n + type impurity ions are implanted in the range of 40-100 KeV.

In a preferred embodiment of this method, the n + type impurity ions have a concentration in the range of 2.0E15-6.0E15 ions / cm ² .

In a preferred embodiment of this method, the trench is formed to a depth in the range of 0.5-1.0 μm.

In a preferred embodiment of this method, the gate insulating film is formed in the range of 500-1500 kV.

(Action)

By such an apparatus and a manufacturing method, it is possible to secure the junction curvature of the n-type source / drain region, thereby preventing breakdown at a low voltage level.

In addition, as the junction depth of the drain region is deepened by the n--type impurity region, the electrostatic discharge characteristics of the drain region are improved.

(Example)

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described in detail based on FIG. 2 and FIG.

In Figs. 2 and 3, the same reference numerals are given to components that perform the same functions as those of the MOS transistors shown in Figs. 1A to 1D.

2 schematically illustrates the structure of a MOS transistor according to an embodiment of the present invention.

Referring to FIG. 2, a MOS transistor according to an exemplary embodiment of the present invention includes a semiconductor substrate 10 and an isolation region formed by defining an active region a and an inactive region b on the semiconductor substrate 10. In the semiconductor substrate 10, the channel region c of the MOS transistor of the active region a is etched to a predetermined thickness to form a trench 15, and a bottom surface of the trench 15 and A gate insulating film 20 formed to overlap a predetermined portion with the active region a across the trench 15, including a sidewall, and an n--type low concentration impurity region formed in one active region a of the trench 15. (17), an n− type first low concentration impurity region 18a formed in the other active region a of the trench 15, and an n − type second concentration formed in the n− type low concentration impurity region 17. Formed on the gate insulating film 20 while filling the low concentration impurity region 18b and the trench 15. The n + type first high concentration impurity region 24a formed in the gate electrode 22, the n− type first low concentration impurity region 18a, and the n + type agent formed in the n− type second low concentration impurity region 18b. It has a structure including two high concentration impurity regions 24b.

Here, the n− type first low concentration impurity region 18a and the n + type first high concentration impurity region 24a are source regions, and the n− type low concentration impurity region 17 and the n− type second region The low concentration impurity region 18b and the n + type second high concentration impurity region 24b are drain regions. The n-type low concentration impurity region 17 is formed to a depth within the range of 1.0-1.5 μm, and the n-type first and second low concentration impurity regions 18a and 18b have a depth within the range 0.5-1.0 μm. Is formed. Further, the trench 15 is formed to a depth within a range of 0.5-1.0 mu m, and the gate insulating film 20 is formed within a range of 500-1500 kPa.

3A to 3D sequentially illustrate a method of manufacturing a MOS transistor according to an embodiment of the present invention. Referring to this, the method of manufacturing a MOS transistor as described above is as follows.

First, referring to FIG. 3A, the nitride layer pattern 14 is formed on the semiconductor substrate 10 by defining an active region a and an inactive region b with the pad oxide layer 12 interposed therebetween.

Next, in FIG. 3B, the field oxide layer 16 is formed by using the nitride layer pattern 14 as a mask and performing a LOCOS process of the pad oxide layer 12 across the nitride layer pattern 14.

In addition, an n--type impurity ion is implanted into one side of the active region a of the semiconductor substrate 10 to form an n--type low concentration drain region 17. In this case, the n-type impurity ion is phosphorus, is ion implanted in the range of about 150-300 keV, and has a concentration in the range of about 1.0E12-1.0E13 ions / cm ² . The n-type low concentration drain region 17 is formed to a depth within the range of about 1.0-1.5 μm.

Subsequently, as shown in FIG. 3C, the trench 15 is etched by etching the semiconductor substrate 10 in the region where the channel c of the MOS transistor is to be formed in the active region a of the semiconductor substrate 10. ). At this time, the trench 15 is formed to a depth within the range of about 0.5-1.0 μm.

The gate insulating film 20 is formed within a range of about 500-1500 Å so as to overlap a predetermined portion of the trench 15 with the bottom and sidewalls of the trench 15. 15, a gate electrode 22 is formed on the gate insulating film 20.

Next, n-type impurity ions are implanted into the active region a on one side of the gate electrode 22 to form an n-type low concentration source region 18a, and in the n--type impurity region 17. Similarly, n-type impurity ions are implanted to form n-type low concentration drain region 18b.

At this time, the n-type impurity ion is phosphorus, and the n-type impurity ion is implanted in the range of about 50-180 keV, and has a concentration in the range of about 3.0E12-1.0E13 ions / cm ² . The n-type low concentration source / drain regions 18a and 18b are also formed at depths in the range of about 0.5-1.0 μm.

Finally, n + type impurity ions are implanted into the n− type low concentration source region 18a to form an n + type high concentration source region 24a. When implanted to form the n + type high concentration drain region 24b, a MOS transistor as shown in FIG. 3D is formed.

Wherein the n + type impurity ions are arsenic, and the n + type impurity ions are implanted in the range of about 40-100 KeV and have a concentration in the range of about 2.0E15-6.0E15 ions / cm ² .

With the above-described MOS transistor and its manufacturing method, the junction curvature of the n-type source / drain region can be ensured, so that breakdown at a low voltage level can be prevented, and the n--type impurity region As the junction depth of the drain region becomes deeper, the electrostatic discharge characteristics of the drain region are improved.

Claims (23)

A semiconductor substrate 10; An isolation region 16 formed on the semiconductor substrate 10 by defining active regions a and inactive regions b; In the semiconductor substrate 10, the trench 15 is formed by etching the channel region c of the MOS transistor of the active region a to a predetermined thickness. A gate insulating film 20 including a bottom surface and sidewalls of the trench 15 so as to overlap a predetermined portion with the active region a at both ends of the trench 15; An n-type low concentration impurity region (17) formed in one side active region (a) of the trench (15); An n− type first low concentration impurity region 18a formed in the other active region a of the trench 15; An n− type second low concentration impurity region 18b formed in the n− type low concentration impurity region 17; A gate electrode 22 formed on the gate insulating film 20 while filling the trench 15; An n + type first high concentration impurity region 24a formed in the n− type first low concentration impurity region 18a; A morph transistor comprising an n + type second high concentration impurity region (24b) formed in the n− type second low concentration impurity region (18b). The method of claim 1, And the n− type first low concentration impurity region (18a) and the n + type first high concentration impurity region (24a) are source regions. The method of claim 1, And the n− type low concentration impurity region (17), the n− type second low concentration impurity region (18b), and the n + type second high concentration impurity region (24b) are drain regions. The method of claim 1, And the n-type low concentration impurity region 17 is formed to a depth within a range of 1.0 to 1.5 μm. The method of claim 1, And the n-type first and second low concentration impurity regions (18a, 18b) are formed to a depth within a range of 0.5-1.0 mu m. The method of claim 1, The trench (15) is a morph transistor having a depth in the range of 0.5 to 1.0 ㎛. The method of claim 1, The gate insulating film 20 is a MOS transistor formed in the range of 500-1500 Å. Defining the active region (a) and the inactive region (b) of the semiconductor substrate 10 to form the field oxide film 16; Implanting n-type impurity ions into one inner side of the active region (a) of the semiconductor substrate (10) to form an n-type low concentration impurity region (17); Etching the channel region (c) of the MOS transistor of the active region (a) of the semiconductor substrate (10) to a predetermined thickness to form a trench (15); Forming a gate insulating film (20) on the active region (a) to partially overlap the active region (a) across the trench (15), including the bottom and sidewalls of the trench (15); Filling the trench (15) to form a gate electrode (22) on the gate insulating film (20); Implanting n-type impurity ions into the active region (a) on one side of the gate electrode (22) to form an n-type first low concentration impurity region (18a); Implanting n-type impurity ions into the n-type impurity region (17) to form an n-type second low concentration impurity region (18b); Implanting n + type impurity ions into the n− type first low concentration impurity region (18a) to form an n + type first high concentration impurity region (24a); And implanting n + type impurity ions into the n− type second low concentration impurity region (18b) to form an n + type second high concentration impurity region (24b). The method of claim 8, And the n− type first low concentration impurity region (18a) and the n + type first high concentration impurity region (24a) are source regions. The method of claim 8, And the n− type impurity region (17), the n− type second low concentration impurity region (18b), and the n + type second high concentration impurity region (24b) are drain regions. The method of claim 8, And n-type impurity ions are phosphorus. The method of claim 8, And the n--type impurity ions are implanted in the range of 150-300 keV. The method of claim 8, Wherein said n--type impurity ions have a concentration within the range of 1.0E12-1.0E13 ions / cm ² . The method of claim 8, The n-- type low concentration impurity region (17) is formed with a depth within a range of 1.0-1.5 mu m. The method of claim 8, And n-type impurity ions are phosphorus. The method of claim 8, And n-type impurity ions are implanted in the range of 50-180 keV. The method of claim 8, Wherein the n-type impurity ion has a concentration in the range of 3.0E12-1.0E13 ions / cm ² . The method of claim 8, And the n-type first and second impurity regions (18a, 18b) are formed to a depth within a range of 0.5-1.0 mu m. The method of claim 8, And arsenic is used as the n + type impurity ion. The method of claim 8, The n + type impurity ions are implanted in the range of 40-100 KeV. The method of claim 8, The n + type impurity ions have a concentration in the range of 2.0E15-6.0E15 ions / cm ² range. The method of claim 8, The trench (15) is a method of manufacturing a MOS transistor formed to a depth in the range of 0.5-1.0 ㎛. The method of claim 8, The gate insulating film (17) is formed in the range of 500-1500 GHz MOS transistor manufacturing method.