KR19980055947A - Method for forming charge storage electrode of semiconductor device - Google Patents
Method for forming charge storage electrode of semiconductor device Download PDFInfo
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- KR19980055947A KR19980055947A KR1019960075184A KR19960075184A KR19980055947A KR 19980055947 A KR19980055947 A KR 19980055947A KR 1019960075184 A KR1019960075184 A KR 1019960075184A KR 19960075184 A KR19960075184 A KR 19960075184A KR 19980055947 A KR19980055947 A KR 19980055947A
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- polysilicon layer
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- charge storage
- storage electrode
- semiconductor device
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
본 발명은 반도체 소자의 전하저장전극 형성 방법에 관한 것으로, 콘택홀을 형성하는 과정에서 발생되는 실리콘 기판의 손실 및 불순물 이온의 하부 확산으로 인한 접합부의 크기 증가를 방지하기 위하여 콘택홀을 2단계 식각법으로 형성하고 폴리실리콘층을 2단계 증착법으로 형성하므로써 소자의 신뢰성이 향상될 수 있도록 한 반도체 소자의 전하저장전극 형성 방법에 관한 것이다.The present invention relates to a method for forming a charge storage electrode of a semiconductor device, wherein the contact hole is etched in two steps in order to prevent an increase in the size of the junction due to the loss of the silicon substrate and the lower diffusion of impurity ions generated during the formation of the contact hole. The present invention relates to a method for forming a charge storage electrode of a semiconductor device, which is formed by a method and a polysilicon layer is formed by a two-step deposition method so that reliability of the device can be improved.
Description
본 발명은 반도체 소자의 전하저장전극 형성 방법에 관한 것으로, 특히 누설전류의 발생으로 인한 소자의 신뢰성 저하를 방지할 수 있도록 한 반도체 소자의 전하저장전극 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a charge storage electrode of a semiconductor device, and more particularly, to a method of forming a charge storage electrode of a semiconductor device, which can prevent a decrease in reliability of a device due to generation of leakage current.
일반적으로 캐패시터는 하부전극과 상부전극으로 이루어지며 하부전극과 상부전극의 사이에는 유전체막이 형성된다. 그러면 캐패시터의 하부전극으로 이용되는 종래 반도체 소자의 전하저장전극 형성 방법을 도 1A 및 도 1B를 통해 설명하면 다음과 같다.In general, a capacitor includes a lower electrode and an upper electrode, and a dielectric film is formed between the lower electrode and the upper electrode. Next, a method of forming a charge storage electrode of a conventional semiconductor device used as a lower electrode of a capacitor will be described with reference to FIGS. 1A and 1B.
도 1A 및 도 1B는 종래 반도체 소자의 전하저장전극 형성 방법을 설명하기 위한 소자의 단면도로서,1A and 1B are cross-sectional views of a device for describing a method of forming a charge storage electrode of a conventional semiconductor device.
도 1A는 접합부(2)가 형성된 실리콘 기판(1)상에 절연막(3)을 형성한 후 상기 접합부(2)가 노출되도록 상기 절연막(3)을 패터닝하여 콘택홀(4)을 형성한 상태의 단면도인데, 상기 콘택홀(4)을 형성하기 위한 식각 공정시 상기 실리콘 기판(1)상 상기 절연막(3)이 잔류되지 않도록 과도 식각을 실시하기 때문에 상기 접합부(2)의 표면이 손실된다.1A shows a state in which a contact hole 4 is formed by forming an insulating film 3 on a silicon substrate 1 on which a junction part 2 is formed, and then patterning the insulating film 3 so that the junction part 2 is exposed. In cross-sectional view, the surface of the junction part 2 is lost because the etching process is performed so that the insulating film 3 does not remain on the silicon substrate 1 during the etching process for forming the contact hole 4.
도 1B는 상기 콘택홀(4)이 매립되도록 전체 상부면에 폴리실리콘층(5)을 형성한 상태의 단면도인데, 이때 언도프(Undope) 폴리실리콘을 증착한 후 불순물 이온을 주입하는 방법 또는 도프(Doped) 폴리실리콘을 증착하는 방법중 어느 하나의 방법을 이용하여 상기 폴리실리콘층(5)을 형성한다. 이후 상기 폴리실리콘층(5)을 패터닝하여 전하저장전극을 형성하고 상기 전하저장전극상에 유전체막 및 상부 전극을 순차적으로 형성하여 캐패시터의 형성을 완료한다. 그런데 상기와 같은 방법을 이용하는 경우 상기 콘택홀(4)을 형성하는 과정에서 발생된 상기 실리콘 기판(1)의 손실 및 후속 열처리 공정시 상기 폴리실리콘층(5)에 주입된 불순물 이온의 하부 확산에 의한 상기 접합부(2)의 크기 증가에 의해 소자의 동작시 누설전류가 발생되며, 이에 의해 메모리 소자의 리프래쉬(Refresh) 특성이 저하된다.FIG. 1B is a cross-sectional view of the polysilicon layer 5 formed on the entire upper surface of the contact hole 4 so as to fill the contact hole 4. In this case, a method or dope in which impurity ions are implanted after depositing undoped polysilicon (Poped) The polysilicon layer 5 is formed by using any one of the methods of depositing polysilicon. Thereafter, the polysilicon layer 5 is patterned to form a charge storage electrode, and a dielectric film and an upper electrode are sequentially formed on the charge storage electrode to complete formation of a capacitor. However, in the case of using the method as described above, the loss of the silicon substrate 1 generated in the process of forming the contact hole 4 and the lower diffusion of impurity ions implanted into the polysilicon layer 5 during the subsequent heat treatment process. Due to the increase in the size of the junction portion 2, a leakage current is generated during operation of the device, thereby lowering the refresh characteristics of the memory device.
따라서 본 발명은 콘택홀을 2단계 식각법으로 형성하고 폴리실리콘층을 2단계 증착법으로 형성하므로써 상기한 단점을 해소할 수 있는 반도체 소자의 전하저장전극 형성 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a charge storage electrode of a semiconductor device which can solve the above-mentioned disadvantages by forming a contact hole by a two-step etching method and forming a polysilicon layer by a two-step deposition method.
상기한 목적을 달성하기 위한 본 발명은 접합부가 형성된 실리콘 기판상에 절연막을 형성한 후 콘택 마스크를 이용하여 상기 절연막을 소정 깊이 1차 식각하는 단계와, 상기 단계로부터 나머지 두께의 상기 절연막을 2차 식각하여 상기 접합부가 노출되도록 콘택홀을 형성하는 단계와, 상기 단계로부터 상기 콘택홀이 매립되도록 전체 상부면에 언도프 폴리실리콘층 및 도프 폴리실리콘층을 순차적으로 형성하는 단계와, 상기 단계로부터 상기 도프 폴리실리콘층 및 언도프 폴리실리콘층을 순차적으로 패터닝하는 단계로 이루어지는 것을 특징으로 하며, 상기 언도프 폴리실리콘층은 10 내지 50nm의 두께로 형성되고 상기 도프 폴리실리콘층은 40 내지 200nm의 두께로 형성되는 것을 특징으로 한다. 또한 상기 언도프 폴리실리콘층 및 도프 폴리실리콘층은 인-시투로 형성되며, 상기 언도프 폴리실리콘층은 550 내지 620℃ 온도에서 SiH4및 Si2H6중 어느 하나의 가스를 이용하여 형성하고, 상기 도프 폴리실리콘층은 550 내지 620℃ 온도에서 PH3와 SiH4및 PH3와 Si2H6중 어느 하나의 혼합 가스를 이용하여 형성하는 것을 특징으로 한다.The present invention for achieving the above object is to form an insulating film on a silicon substrate formed with a junction, and then first etching the insulating film by a predetermined depth using a contact mask, and the second insulating film of the remaining thickness from the step Forming a contact hole to be etched to expose the junction, and sequentially forming an undoped polysilicon layer and a dope polysilicon layer on the entire upper surface such that the contact hole is embedded from the step; Patterning the dope polysilicon layer and the undoped polysilicon layer sequentially, wherein the undoped polysilicon layer is formed to a thickness of 10 to 50nm and the dope polysilicon layer is to a thickness of 40 to 200nm. It is characterized by being formed. In addition, the undoped polysilicon layer and the dope polysilicon layer is formed in-situ, the undoped polysilicon layer is formed using any one of SiH 4 and Si 2 H 6 at a temperature of 550 to 620 ℃ The dope polysilicon layer is formed using a mixed gas of any one of PH 3 and SiH 4 and PH 3 and Si 2 H 6 at a temperature of 550 to 620 ℃.
도 1A 및 도 1B는 종래 반도체 소자의 전하저장전극 형성 방법을 설명하기 위한 소자의 단면도.1A and 1B are cross-sectional views of a device for explaining a method of forming a charge storage electrode of a conventional semiconductor device.
도 2A 내지 도 2D는 본 발명에 따른 반도체 소자의 전하저장전극 형성 방법을 설명하기 위한 소자의 단면도.2A to 2D are cross-sectional views of a device for explaining a method of forming a charge storage electrode of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1 및 11 : 실리콘 기판2 및 12 : 접합부1 and 11: silicon substrate 2 and 12: junction
3 및 13 : 절연막4 및 14 : 콘택홀3 and 13 insulating film 4 and 14 contact hole
5 : 폴리실리콘층15A : 언도프 폴리실리콘층5: polysilicon layer 15A: undoped polysilicon layer
15B : 도프 폴리실리콘층15B: Doped Polysilicon Layer
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 2A 내지 도 2D는 본 발명에 따른 반도체 소자의 전하저장전극 형성 방법을 설명하기 위한 소자의 단면도로서,2A to 2D are cross-sectional views of a device for explaining a method of forming a charge storage electrode of a semiconductor device according to the present invention.
도 2A는 접합부(12)가 형성된 실리콘 기판(11)상에 절연막(13)을 형성한 후 콘택 마스크(도시안됨)를 이용하여 상기 절연막(13)을 소정 깊이 1차 식각한 상태의 단면도로서, 이때 잔류되는 상기 절연막(13)의 두께는 1 내지 5nm 정도가 되도록 한다.2A is a cross-sectional view of the insulating film 13 formed on the silicon substrate 11 on which the junction part 12 is formed, and then the insulating film 13 is firstly etched to a predetermined depth using a contact mask (not shown). At this time, the thickness of the insulating layer 13 remaining is about 1 to 5nm.
도 2B는 나머지 두께의 상기 절연막(13)을 2차 식각하여 상기 접합부(12)가 노출되도록 콘택홀(14)을 형성한 상태의 단면도로서, 상기 1차 식각 공정은 상기 2차 식각 공정보다 식각 속도가 높은 식각 방법을 이용하며, 상기 2차 식각은 HF 또는 BOE 용액을 이용한 습식으로 실시하여 상기 실리콘 기판(11)의 손실을 방지한다.2B is a cross-sectional view of a state in which the contact hole 14 is formed by second etching the insulating layer 13 having the remaining thickness to expose the junction 12, and the first etching process is more etched than the second etching process. A high-speed etching method is used, and the secondary etching is performed by using a wet solution of HF or BOE to prevent loss of the silicon substrate 11.
도 2C는 550 내지 620℃ 온도이 반응로내에서 SiH4또는 Si2H6가스를 이용한 증착 공정으로 상기 콘택홀(14)이 매립되도록 전체 상부면에 언도프 폴리실리콘층(15A)을 10 내지 50nm의 두께로 형성한 상태의 단면도이고, 도 2D는 인-시투(In-Situ)로 PH3와 SiH4또는 PH3와 Si2H6가 혼합된 가스를 이용하여 상기 언도프 폴리실리콘층(15A)상에 도프 폴리실리콘층(15B)을 40 내지 200nm의 두께로 형성한 상태의 단면도이다. 이후 상기 도프 폴리실리콘층(15B) 및 언도프 폴리실리콘층(15A)을 순차적으로 패터닝하여 전하저장전극을 형성하고 상기 전하저장전극상에 유전체막 및 상부전극을 형성하여 캐패시터의 형성을 완료한다.FIG. 2C shows a undoped polysilicon layer 15A on the entire upper surface of the undoped polysilicon layer 15A so that the contact hole 14 is buried in a deposition process using SiH 4 or Si 2 H 6 gas at a temperature of 550 to 620 ° C. a cross-sectional view of a state formed with a thickness of, 2D is in-situ (in-situ) as PH 3 and SiH 4 or PH 3, and Si 2 H 6 is the undoped polysilicon layer (15A, using the mixed gas ) Is a cross-sectional view of the dope polysilicon layer 15B having a thickness of 40 to 200 nm. Thereafter, the dope polysilicon layer 15B and the undoped polysilicon layer 15A are sequentially patterned to form a charge storage electrode, and a dielectric film and an upper electrode are formed on the charge storage electrode to complete formation of a capacitor.
상기와 같은 방법을 이용하면 상기 콘택홀(14)을 형성하는 과정에서 상기 실리콘 기판(11)의 손실이 발생되지 않으며, 또한 후속 열처리 공정시 상기 도프 폴리실리콘층(15B)에 함유된 불순물 이온이 하부 확산되더라도 상기 언도프 폴리실리콘층(15A)을 통해 상기 실리콘 기판(11)까지 확산되지 못한다.By using the above method, no loss of the silicon substrate 11 occurs in the process of forming the contact hole 14, and impurity ions contained in the dope polysilicon layer 15B are not included in the subsequent heat treatment process. Even if diffused downward, the silicon substrate 11 may not be diffused through the undoped polysilicon layer 15A.
상술한 바와 같이 본 발명에 의하면 콘택홀을 형성하는 과정에서 발생되는 실리콘 기판의 손실을 방지하며 후속 열처리 공정시 불순물 이온의 하부 확산으로 인한 접합부의 크기 증가를 방지하므로써, 소자의 동작시 누설전류가 발생되지 않으며, 따라서 리프래쉬 특성 및 신뢰성이 향상될 수 있는 효과가 있다.As described above, according to the present invention, the leakage current during the operation of the device is prevented by preventing the loss of the silicon substrate generated during the formation of the contact hole and preventing the increase in the size of the junction due to the lower diffusion of the impurity ions during the subsequent heat treatment process. There is no effect, and thus there is an effect that the relash characteristics and reliability can be improved.
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| KR100446316B1 (en) * | 2002-03-30 | 2004-09-01 | 주식회사 하이닉스반도체 | Method for forming a contact plug in semiconductor device |
| KR100447107B1 (en) * | 2001-06-29 | 2004-09-04 | 주식회사 하이닉스반도체 | The structure of plug poly silicon layer in semiconductor device |
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| KR101598834B1 (en) * | 2010-02-17 | 2016-03-02 | 삼성전자주식회사 | Method for manufacturing semiconductor device having contact plug |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100447107B1 (en) * | 2001-06-29 | 2004-09-04 | 주식회사 하이닉스반도체 | The structure of plug poly silicon layer in semiconductor device |
| KR100446316B1 (en) * | 2002-03-30 | 2004-09-01 | 주식회사 하이닉스반도체 | Method for forming a contact plug in semiconductor device |
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