KR19980055901A - Nested vernier - Google Patents

Abstract

FIELD OF THE INVENTION The present invention relates to overlapping verniers, wherein the overlay accuracy with an under layer in a photolithography process for forming a pattern for a barrier to an implant process. In order to more easily measure alignment by improving the vernier for measuring), a plurality of square box-shaped parent verniers are inserted into the scribe area of the first mask to form the lower layer, and A box-in-box shaped vernier number of verniers is inserted into the scribe area of the second mask for injection, and as a result of the process using these two masks, the vernier and the vernier Obtain a plurality of overlapping patterns, and the values of the positions where the parent vernier pattern and the child vernier pattern are exactly overlapped among the plurality of overlapping patterns are related to the overlapping vernier indicating the degree of alignment. Is described.

Description

Nested vernier

FIELD OF THE INVENTION The present invention relates to overlapping verniers, in particular overlapping with an under layer in a photolithography process to form a pattern for the barrier for the implantation process. It is about an overlapping vernier that can measure alignment degree more easily by improving the vernier for measuring accuracy.

As semiconductor devices become highly integrated and miniaturized, the overlapping alignment between the lower layer and the upper layer or the lower layer and the impurity diffusion layer is an important factor in the reliability of the device. Therefore, a vernier is inserted in the scribe area of the mask used for the manufacturing process of a semiconductor element, and the superposition alignment degree is measured.

FIG. 1 is a view illustrating a conventional overlapping vernier, in which a plurality of parent vernier patterns 2 are superposed on each of a plurality of parent vernier patterns 1. This overlapping vernier has a large error according to the measuring person, and when the difference in topology between the parent vernier pattern (1) and the child vernier pattern (2) is severe, it is difficult to measure the focusing in the optical microscope. It is difficult and the size of the parent vernier pattern 1 and the child vernier pattern 2 is small, and in the case of poor adhesion, the child vernier pattern 2 is separated from the parent vernier pattern 2 and becomes a particle source. easy.

Accordingly, the present invention improves the vernier for measuring the overlap alignment with the lower layer in the photolithography process for forming the barrier pattern for the ion implantation process to provide an overlap vernier that can easily measure the alignment. The purpose is.

The present invention for achieving this object is used in the photolithography operation of a number of moberia inserted into the scribe line of the first mask for forming the lower layer during the manufacturing process of the semiconductor device, and all processes not subjected to the etching process The degree of alignment is measured using a plurality of ruler vernier and the parent vernier and the ruler vernier inserted into the scribe line of the second mask.

1 shows a conventional overlapping vernier;

2 is a view showing a first mask inserted with a vernier according to an embodiment of the present invention.

3 is a view showing a second mask having a vernier vernier inserted therein according to an embodiment of the present invention;

4 (a) is an enlarged view of a parent vernier.

Fig. 4B is an enlarged view of the ruler vernier.

Figure 4 (c) is a superposition of the parent vernier pattern and the child vernier pattern formed corresponding to the parent vernier and the child vernier.

Explanation of symbols on the main parts of the drawings

1, 140: vernier pattern 2, 240: purple vernier pattern

11, 21: mask 12, 22: product die

13, 23: scribe line 14: vernier

24: vernier

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a view showing a first mask 11 in which a mother vernier 14 is inserted according to an embodiment of the present invention. The first mask 11 consists of a plurality of product dies 12 and a scribe line 13 separating these producer dies 12 and a plurality of mother dies on the scribe line 13. Vernier 14 is inserted. The first mask 11 is for forming a lower layer (not shown) during the manufacturing process of the semiconductor device.

The parent vernier 14 has a square box shape as shown in FIG. 4 (a), and at least three such parent verniers 14 are inserted into the scribe line 13, and each parent vernier 14 has a predetermined interval. Is formed.

3 is a view illustrating a second mask 21 into which a magnetic vernier 24 is inserted according to an embodiment of the present invention. The second mask 21 consists of a plurality of product dies 22 and a scribe line 23 that separates the producer dies 22 and a plurality of rulers on the scribe lines 23. Vernier 24 is inserted. The second mask 21 is for forming an ion implantation layer (not shown) during the manufacturing process of the semiconductor device.

The ruler vernier 24 has a box-in-box shape as shown in Fig. 4 (b), and the ruler vernier 24 is inserted into the scribe line 23 by the number of parent verniers 14, and each ruler Vernier 24 is formed at regular intervals.

In the above, the parent vernier located in the center of the plurality of parent vernier 14 in the initial design for inserting the plurality of parent vernier 14 and the plurality of child vernier 24 in the first and second masks 11 and 21 Each parent vernier 14B, 14C formed so as to be accurately overlapped with the parent vernier 24A of the portion corresponding thereto, and the mother vernier 14A and the child vernier 24A positioned at the center. Wafer vernier 24B, 24C is designed to be misaligned continuously by a certain distance, e. That is, when the mother vernier 14A and the child vernier 24A positioned in the center overlap, the child vernier 24A is exactly overlapped in the mother vernier 14A, and the mother vernier 14B and the child vernier of the immediately adjacent part are overlapped. (24B) is misaligned by ± 0.05 mu m, and the parent vernier 14C and the child vernier 24C of the next part are misaligned by ± 0.10 mu m.

When the above-described first and second masks 11 and 21 are applied to the manufacturing process of the semiconductor device, as shown in FIG. 4 (c) when first applying the first mask 11 to form a lower layer on the semiconductor wafer. The parent vernier patterns 140 are formed on a portion of the semiconductor wafer corresponding to the parent vernier 14 of the first mask 11. The parent vernier patterns 140 are formed of the same material as the lower layer. Then, the second mask 21 is applied to form a photoresist pattern as an ion implantation mask layer on the semiconductor wafer on which the lower layer is formed, wherein the ruler vernier of the second mask 21 is shown in FIG. The vernier patterns 240 are formed in a portion of the semiconductor wafer corresponding to the field 24. Of course, the vernier patterns 240 are formed of a photosensitive material.

As a result of the manufacturing process of the semiconductor device to which the first and second masks 11 and 21 are applied, the child vernier patterns 240 are superposed one by one on the parent vernier patterns 140. As shown in FIG. 4 (c), the values of the positions where the parent vernier pattern 140 and the child vernier pattern 240 are exactly overlapped among the plurality of overlapped patterns represent alignment. That is, when the overlapping patterns corresponding to the parent vernier 14A and the child vernier 24A positioned at the center are exactly overlapped, the alignment is in good condition, and when the other overlapping patterns are exactly overlapped, the alignment is poor. It is a state.

As described above, when the alignment degree is measured using the overlapping pattern, when the photoresist pattern is removed, the self vernier patterns 240 are also removed, leaving only the parent vernier patterns 140, and in the subsequent process, the parent vernier patterns 140. Can be used to measure the degree of alignment again. Therefore, since the vernier patterns 140 can be used again, the size of the area occupied by the vernier for the alignment measurement can be reduced, so that the size of the vernier can be made large, and the vernier patterns formed in one process can be used continuously. As a result, the alignment degree can be measured by inserting only the vernier in the mask applied to the photolithography process of all processes that do not undergo the etching process.

As described above, the present invention can measure the alignment more easily and accurately, and because only one parent vernier is used, the area occupied by the pattern for the alignment measurement in the scribe line can be reduced, and the size of the pattern increases, so the pattern You can prevent this from falling off.

Claims (6)

A plurality of parent vernier inserted in the scribe line of the first mask for forming the lower layer during the manufacturing process of the semiconductor device; It consists of multiple ruler verniers inserted into the scribe line of the second mask used for photolithography of all processes without etching The overlapping vernier, characterized in that for measuring the degree of alignment using the parent vernier and the child vernier. The method of claim 1, The parent vernier is a square box shape, the vernier is overlapping, characterized in that the box-in-box shape. The method of claim 1, And at least three parent vernier and the child vernier are inserted into a scribe line of each mask. The method of claim 1, When the first mask and the second mask are superimposed, the parent vernier positioned in the center of the plurality of vernier and the child vernier of the corresponding part thereof overlap precisely, and Each of the parent vernier and the vernier vernier formed on both sides are overlapping vernier, characterized in that misaligned by a predetermined distance in succession. The method of claim 4, wherein When the centrally located parent vernier and the child vernier are exactly overlapped, the superimposed parent vernier and the child vernier are misaligned by ± 0.05 μm, and the superimposed parent vernier and the child vernier are ± Overlapping vernier, characterized in that misaligned by 0.10㎛. The method of claim 1, When the first and second masks are applied to a manufacturing process of a semiconductor device, a mother vernier pattern formed to correspond to the parent vernier is formed of the same material as the lower layer, and the child vernier pattern formed to correspond to the child vernier is photosensitive. Overlapping vernier, characterized in that formed of a material.