KR19980052473A - Wiring Formation Method of Semiconductor Device - Google Patents

Wiring Formation Method of Semiconductor Device Download PDF

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Publication number
KR19980052473A
KR19980052473A KR1019960071462A KR19960071462A KR19980052473A KR 19980052473 A KR19980052473 A KR 19980052473A KR 1019960071462 A KR1019960071462 A KR 1019960071462A KR 19960071462 A KR19960071462 A KR 19960071462A KR 19980052473 A KR19980052473 A KR 19980052473A
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insulating film
wiring
forming
trench
wiring layer
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KR1019960071462A
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Korean (ko)
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KR100209596B1 (en
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권태석
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문정환
엘지반도체 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체소자의 배선에 관한 것으로 특히, 배선라인의 표면적 증가로 인한 열 방출 효과와 힐록 발생을 최소화하기에 적당한 반도체소자의 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to wiring of semiconductor devices, and more particularly, to a method of forming a wiring of a semiconductor device suitable for minimizing heat dissipation effect and hillock generation due to an increase in surface area of wiring lines.

본 발명에 따른 반도체소자의 배선 형성방법은 반도체기판상에 제 1 절연막을 형성하는 단계, 상기 제 1 절연막에 디메신 구조의 트랜치를 형성하는 단계, 상기 트랜치를 포함한 제 1 절연막 전면에 밀착용 메탈과 상기 밀착용 메탈상에 배선층과 상기 배선층상에 반사방지막을 트랜치와 제 1 절연막 표면을 따라서 형성하는 단계, 상기 반사방지막, 배선층 그리고 밀착용 메탈을 연마하여 제 1 절연막의 상층면을 노출시키는 단계, 상기 제 1 절연막을 포함한 배선층 전면에 제 2 절연막을 형성하는 단계를 포함하여 배선층에서 발생하는 열을 효과적으로 방출하여 일렉트로마이크레이션 방지와 힐록의 발생을 억제할 수 있는 반도체소자의 배선 형성방법을 제공할 수 있는 효과가 있다.In the method for forming a wiring of a semiconductor device according to the present invention, the method includes forming a first insulating film on a semiconductor substrate, forming a trench having a demesin structure on the first insulating film, and contacting metal on the entire surface of the first insulating film including the trench. And forming an anti-reflection film on the adhesion metal along the trench and the first insulating film surface along the trench and the surface of the first insulating film, and polishing the anti-reflection film, the wiring layer and the adhesion metal to expose the upper surface of the first insulating film. And forming a second insulating film over the entire wiring layer including the first insulating film, thereby effectively dissipating heat generated from the wiring layer to prevent electromigration and to suppress the occurrence of hillock. It can work.

Description

반도체소자의 배선 형성방법Wiring Formation Method of Semiconductor Device

본 발명은 반도체소자의 배선에 관한 것으로 특히, 열방출 효과 및 힐록으로 인한 배선 불량을 최소화하기에 적당한 반도체소자의 배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to wiring of semiconductor devices, and more particularly, to a method of forming wirings of semiconductor devices suitable for minimizing wiring defects due to heat dissipation effects and hillocks.

집적회로의 배선재료에는 전류를 전송한다는 성질이외에 미세한 배선 패턴을 저코스트로 효율적으로 제조하고 또한 장시간의 사용에 대해서 단선 등의 고장이 생겨서는 안된다는 것등 제조 및 신뢰성면에 대해 여러 가지 조건이 필요하다.In addition to the nature of transmitting current, the wiring material of the integrated circuit requires various conditions for manufacturing and reliability, such as the efficient manufacture of fine wiring patterns at low cost and the failure of disconnection for long time use. Do.

그와 같은 여러조건은 염가의 고순도 재료, 전기전도율이 높을 것, 레지스트와의 선택비가 높을 것과 미세 가공이 가능할 것 등이다. 상기한 바와 같은 여러조건에 가장적합한 것으로 알려져 배선재료로 많이 사용되는 물질이 알루미늄(Al)인데 이와 같은 알루미늄도 일렉트로마이그레이션(electromigration)이 발생하기 쉽다는 등의 문제점이 있다. 이때, 전기적 이동도를 뜻하는 상기 일렉트로마이크레이션은 갖가지 금속에서 발생하는 현상으로 일반적으로 반도체소자의 배선재료로 사용하는 알루미늄 배선층에서도 알루미늄 배선층에 장시간 전류를 계속 흘리면 전자의 흐름에 의해 알루미늄 이온이 움직이는 것을 말하는 것으로 이러한 현상이 장시간 지속될 경우 보이드(void)나 크랙(crack)이 발생하게 되어 배선층이 단선하게 된다. 그러므로, 알루미늄을 합금막으로하며, 그와 같은 알루미늄 합금막의 수명을 미리 예측해서 고장이 발생하지 않는 전류밀도가 되도록 배선 패턴에 대한 설계를 해야 한다.Such conditions include low cost, high purity materials, high electrical conductivity, high selectivity with resist, and fine processing. Aluminum (Al), which is known to be most suitable for various conditions as described above, is widely used as a wiring material, and there is a problem such that aluminum is also likely to cause electromigration. In this case, the electromigration, which refers to electrical mobility, is a phenomenon occurring in various metals. In the aluminum wiring layer, which is generally used as a wiring material of a semiconductor device, aluminum ions move due to the flow of electrons when a current is continuously flowed in the aluminum wiring layer for a long time. If this phenomenon persists for a long time, voids or cracks are generated and the wiring layer is disconnected. Therefore, the wiring pattern should be designed so that aluminum is used as the alloy film and the current density of the aluminum alloy film is predicted in advance, so that the current density does not occur.

이와 같은 종래 반도체소자의 배선 형성방법을 첨부된 도면을 참조하여 설명하기로 한다.Such a method of forming a wiring of a conventional semiconductor device will be described with reference to the accompanying drawings.

도 1a 내지 도 1d는 종래 반도체소자의 배선 형성공정 단면도이다.1A to 1D are cross-sectional views of a wiring forming process of a conventional semiconductor device.

먼저, 도 1a에 나타낸 바와 같이, 반도체기판(1)전면에 제 1 산화막(2), Ti/TiN층(3), 알루미늄층(4) 그리고, TiN층(5)을 차례로 형성한다. 이때, 상기 Ti/TiN층(3)과, TiN(5)은 고융점 금속(refractory metal)로 통상적으로 알루미늄 층을 이용한 배선공정의 전후 공정중에서 증착하여 다층전도체(multilayer conductor)를 이루어 일렉트로마이크레이션(electromigration) 불량을 최소화시킨다.First, as shown in FIG. 1A, a first oxide film 2, a Ti / TiN layer 3, an aluminum layer 4, and a TiN layer 5 are sequentially formed on the front surface of the semiconductor substrate 1. At this time, the Ti / TiN layer 3 and TiN (5) is a high melting point metal (refractory metal) is deposited in the before and after process of the wiring process using a conventional aluminum layer to form a multilayer conductor (electromagnetic migration) (electromigration) minimizes defects.

도 1b에 나타낸 바와 같이, 상기 TiN층(5)상에 감광막(PR)을 도포한후 노광 및 현상공정으로 배선라인 형성영역을 정의하여 상기 감광막(PR)을 패터닝(patterning)한다.As shown in FIG. 1B, after the photoresist film PR is applied onto the TiN layer 5, a wiring line formation region is defined by an exposure and development process to pattern the photoresist film PR.

도 1c에 나타낸 바와 같이, 패터닝된 상기 감광막(PR)을 마스크로 이용한 식각공정으로 상기 TiN층(5), 알루미늄층(4) 그리고, Ti/Tin층(3)을 선택적으로 제거하여 배선라인(4a)을 형성한다. 그다음, 상기 감광막(PR)을 제거한다.As shown in FIG. 1C, the TiN layer 5, the aluminum layer 4, and the Ti / Tin layer 3 are selectively removed by an etching process using the patterned photoresist PR as a mask. 4a). Then, the photoresist film PR is removed.

도 1d에 나타낸 바와 같이, 상기 배선라인(4a)을 포함한 제 1 산화막(2)전면에 제 2 산화막(6)을 형성한다.As shown in Fig. 1D, a second oxide film 6 is formed on the entire surface of the first oxide film 2 including the wiring line 4a.

종래 반도체소자의 배선 형성방법에 있어서는 다음과 같은 문제점이 있었다.The conventional method for forming a wiring of a semiconductor device has the following problems.

첫째, 알루미늄 배선층이 상층면 및 하층면에만 고융점금속이 형성되어 있어 측면으로의 힐록(hillock)발생 방지나, 산화막의 수분이나 불순물이나 배선층의 측면 결합으로 인한 불량발생 가능성이 높아 배선으로서의 신뢰성에 문제점이 있었다.First, high-melting-point metal is formed only on the upper and lower layers of the aluminum wiring layer, which prevents hillocks from occurring on the side surfaces, and is likely to cause defects due to moisture or impurities in the oxide film or side bonding of the wiring layers. There was a problem.

둘째, 건식식각시 고융점금속과 알루미늄 배선층과의 식각율이 달라 배선층이 역사다리 꼴 모양으로 형성되어 배선공정후 산화막의 완전한 갭 필링(gap filling)이 안될수 있어 배선으로서의 신뢰도를 저하시켰다.Second, because the etching rate between the high melting point metal and the aluminum wiring layer is different in dry etching, the wiring layer is formed in an inverted trapezoidal shape, and thus, the gap gap of the oxide film may not be fully filled after the wiring process, thereby reducing the reliability of the wiring.

본 발명은 상기한 바와 같은 종래 반도체소자의 배선 형성방법에 있어서의 문제점을 해결하기 위하여 안출한 것으로 특히, 디메신(demascene)구조를 이용한 배선층 형성공정으로 배선라인의 표면적을 증가시켜 증가시켜 열방출 효과를 높임과 동시에 배선층의 힐록발생을 최소화할 수 있는 반도체소자의 배선 형성방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the problems in the conventional method for forming a wiring of a semiconductor device as described above. In particular, the heat dissipation is increased by increasing the surface area of the wiring line in a wiring layer forming process using a demascene structure. An object of the present invention is to provide a method for forming a wiring of a semiconductor device which can increase the effect and minimize the occurrence of hillock in the wiring layer.

도 1a 내지 도 1d는 종래 반도체소자의 배선 형성공정 단면도1A to 1D are cross-sectional views of a wiring forming process of a conventional semiconductor device.

도 2a 내지 도 2e는 본 발명의 반도체소자의 배선 형성공정 단면도2A to 2E are cross-sectional views of a wiring forming process of a semiconductor device according to the present invention.

*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

10 : 반도체기판11 : 제 1 절연막10 semiconductor substrate 11: first insulating film

12 : 트랜치13 : 밀착용 메탈12: trench 13: contact metal

14 : 배선층15 : 반사방지막14 wiring layer 15 antireflection film

16 : 제 2 절연막16: second insulating film

본 발명에 따른 반도체소자의 배선 형성방법은 반도체기판상에 제 1 절연막을 형성하는 단계, 상기 제 1 절연막에 디메신 구조의 트랜치를 형성하는 단계, 상기 트랜치를 포함한 제 1 절연막 전면에 밀착용 메탈과 상기 밀착용 메탈상에 배선층과 상기 배선층상에 반사방지막을 트랜치와 제 1 절연막 표면을 따라서 형성하는 단계, 상기 반사방지막, 배선층 그리고 밀착용 메탈을 연마하여 제 1 절연막의 상층면을 노출시키는 단계, 상기 제 1 절연막을 포함한 배선층 전면에 제 2 절연막을 형성하는 단계를 포함한다.In the method for forming a wiring of a semiconductor device according to the present invention, the method includes forming a first insulating film on a semiconductor substrate, forming a trench having a demesin structure on the first insulating film, and contacting metal on the entire surface of the first insulating film including the trench. And forming an anti-reflection film on the adhesion metal along the trench and the first insulating film surface along the trench and the surface of the first insulating film, and polishing the anti-reflection film, the wiring layer and the adhesion metal to expose the upper surface of the first insulating film. And forming a second insulating film on the entire wiring layer including the first insulating film.

이와 같은 본 발명 반도체소자의 배선 형성방법을 첨부된 도면을 참조하여 설명하기로 한다.Such a wiring forming method of the semiconductor device of the present invention will be described with reference to the accompanying drawings.

도 2a 내지 도 2d는 본 발명 반도체소자의 배선 형성공정 단면도이다.2A to 2D are cross-sectional views of a wiring forming process of the semiconductor device of the present invention.

먼저, 도 2a에 나타낸 바와 같이 반도체기판(10)상에 제 1 절연막(11)과 감광막(PR)을 차례로 형성한다. 그다음, 노광 및 현상공정으로 배선형성영역을 정의하여 감광막(PR)을 패터닝한다. 이때, 상기 제 1 절연막(11)은 산화막과 질화막중 어느 하나로 형성한다.First, as shown in FIG. 2A, the first insulating film 11 and the photoresist film PR are sequentially formed on the semiconductor substrate 10. Then, the wiring forming region is defined by the exposure and development processes to pattern the photosensitive film PR. In this case, the first insulating film 11 is formed of one of an oxide film and a nitride film.

도 2b에 나타낸 바와 같이, 상기 패터닝된 감광막(PR)을 마스크로 이용한 식각공정으로 제 1 절연막(11)을 선택적으로 제거하여 트랜치(12)을 형성한다. 이때, 상기 트랜치(12)의 상층면이 라운드(round)형상으로 형성하도록 한다. 또는, 상기 트랜치를 수직으로 형성하거나 또는 약간 기울게(slope)형성할 수도 있다. 그다음, 상기 감광막(PR)을 제거한다.As shown in FIG. 2B, a trench 12 is formed by selectively removing the first insulating layer 11 by an etching process using the patterned photoresist PR as a mask. In this case, the upper layer surface of the trench 12 is formed in a round shape. Alternatively, the trench may be formed vertically or slightly sloped. Then, the photoresist film PR is removed.

도 2c에 나타낸 바와 같이, 상기 트랜치(12)를 포함한 제 1 절연막(11)표면을 따라서 밀착용 메탈(13)을 형성한다. 그다음, 상기 밀착용 메탈(13)전면에 배선층(14)을 형성한다. 이때, 상기 밀착용 메탈(13)은 Ti/TiN층으로 형성하고, 배선층(14)은 알루미늄(Al)으로 형성한다. 그리고, 상기 Ti/TiN층과 배선층(14)사이에 Ti층을 형성할 수 있다. 또한, 상기 Ti/TiN층이나 알루미늄층의 형성방법은 물리기상증착법(PVD : Physical Vapor Deposition)이나 화학기상증착법(CVD : Chemical Vapor Deposition)을 사용하여 형성한다. 이어서, 상기 배선층(14)을 리플로우(reflow)시킨다. 이때, 상기 트랜치(12)의 상층면에서 완전히 채워지지 않도록 한다. 그다음, 상기 배선층(14)상에 반사방지막(15)을 형성한다. 이때, 상기 반사방지막(15)은 TiN으로 형성한다.As shown in FIG. 2C, the adhesion metal 13 is formed along the surface of the first insulating film 11 including the trench 12. Next, the wiring layer 14 is formed on the entire surface of the contact metal 13. At this time, the adhesion metal 13 is formed of a Ti / TiN layer, the wiring layer 14 is formed of aluminum (Al). In addition, a Ti layer may be formed between the Ti / TiN layer and the wiring layer 14. In addition, the Ti / TiN layer or the aluminum layer is formed using physical vapor deposition (PVD) or chemical vapor deposition (CVD). Subsequently, the wiring layer 14 is reflowed. At this time, the upper layer of the trench 12 is not completely filled. Next, an antireflection film 15 is formed on the wiring layer 14. At this time, the anti-reflection film 15 is formed of TiN.

도 2d에 나타낸 바와 같이, 상기 반사방지막(15), 배선층(14) 그리고, 밀착용 메탈(13)을 화학기계적경면연마(CMP : Chemical Mechanical Polishing)법을 이용하여 상기 제 1 절연막(11)의 상층면이 노출될 때 까지 연마한다. 즉, 상기 밀착용 메탈(13), 배선층(14) 그리고, 상기 반사방지막(15)을 트랜치(12)내에만 남도록 연마하는 것이다.As shown in FIG. 2D, the anti-reflection film 15, the wiring layer 14, and the adhesion metal 13 may be chemically polished using a chemical mechanical polishing (CMP) method. Polish until the top surface is exposed. That is, the adhesion metal 13, the wiring layer 14, and the anti-reflection film 15 are polished so as to remain in the trench 12 only.

도 2e에 나타낸 바와 같이, 상기 트랜치(12)의 밀착용 메탈(13), 배선층(14) 그리고 반사방지막(15)을 포함한 제 1 절연막(11)전면에 제 2 절연막(16)을 형성한다. 이때, 상기 제 2 절연막(16)은 산화막과 질화막중 어느 하나로 형성한다.As shown in FIG. 2E, a second insulating film 16 is formed on the entire surface of the first insulating film 11 including the metal 13 for contacting the trench 12, the wiring layer 14, and the anti-reflection film 15. In this case, the second insulating layer 16 is formed of one of an oxide film and a nitride film.

본 발명 반도체소자의 배선 형성방법에 있어서는 다음과 같은 효과가 있다.The wiring forming method of the semiconductor device of the present invention has the following effects.

첫째, 디메신 구조의 트랜치의 표면을 따라서 다층전도층으로 배선층이 형성되어 상대적으로 배선층의 노출면이 적어 힐록(hillock)발생 가능성을 최대한 억제할 수 있고, 표면의 노출이 적음에 따라 산화막의 수분이나 불순물등과 배선층의 결합 또는 억제하여 불량 발생 가능성이 적다. 또한, 배선 형성공정 완료후 절연막의 완전한 갭 필링(gap filling)이 가능하여 배선으로서 신뢰도가 향상된다.First, a wiring layer is formed of a multi-layer conductive layer along the surface of the trench of the dimesin structure, so that the exposed surface of the wiring layer is relatively small, so that the possibility of hillock occurrence can be suppressed as much as possible. Less likely to cause defects by combining or suppressing impurities or wiring layers. In addition, complete gap filling of the insulating film is possible after the wiring forming process is completed, thereby improving reliability as wiring.

둘째, 종래에 비해 상대적으로 동일 공간에서 배선층의 면적이 넓어지므로 배선에서 발생하는 저항과 열 성분의 감소로 일렉트로 마이크레이션 현상을 최대한 억제할 수 있다.Second, since the area of the wiring layer is wider in the same space as compared with the related art, the electro-polation phenomenon can be suppressed to the maximum by reducing the resistance and thermal components generated in the wiring.

Claims (6)

반도체기판상에 제 1 절연막을 형성하는 단계;Forming a first insulating film on the semiconductor substrate; 상기 제 1 절연막에 디메신 구조의 트랜치를 형성하는 단계;Forming a trench of a dimesin structure in the first insulating film; 상기 트랜치를 포함한 제 1 절연막 전면에 밀착용 메탈과, 상기 밀착용 메탈상에 배선층과, 상기 배선층상에 반사방지막을 트랜치와 제 1 절연막 표면을 따라서 형성하는 단계;Forming an adhesion metal on the entire first insulating film including the trench, a wiring layer on the adhesion metal, and an anti-reflection film on the wiring layer along the trench and the first insulating film surface; 상기 반사방지막, 배선층 그리고 밀착용 메탈을 연마하여 제 1 절연막의 상층면을 노출시키는 단계;Polishing the anti-reflection film, the wiring layer, and the adhesion metal to expose the upper layer surface of the first insulating film; 상기 제 1 절연막을 포함한 배선층 전면에 제 2 절연막을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체소자의 배선 형성방법.And forming a second insulating film over the entire wiring layer including the first insulating film. 제 1 항에 있어서, 상기 제 1, 제 2 절연막을 산화막과 질화막중 어느 하나로 형성함을 특징으로 하는 반도체소자의 배선 형성방법.The method of forming a wiring of a semiconductor device according to claim 1, wherein the first and second insulating films are formed of one of an oxide film and a nitride film. 제 1 항에 있어서, 상기 트랜치의 상층면은 라운드 형상으로 형성하거나, 기울어지게 형성하거나 또는 수직으로 형성함을 특징으로 하는 반도체소자의 배선 형성방법.The method of claim 1, wherein the upper layer surface of the trench is formed in a round shape, is formed to be inclined, or is formed vertically. 제 1 항에 있어서, 상기 배선층은 금속층으로 형성하는 것을 특징으로 하는 반도체소자의 배선 형성방법.The method of claim 1, wherein the wiring layer is formed of a metal layer. 제 1 항에 있어서, 상기 연마법은 화학기계적경면연마법인 것을 특징으로 하는 반도체소자의 배선 형성방법.The method of forming a wiring of a semiconductor device according to claim 1, wherein the polishing method is a chemical mechanical mirror polishing method. 제 1 항에 있어서, 상기 밀착용 메탈, 상기 배선층 그리고 상기 반사방지막은 물리기상증착법과 화학기상증착법중 어느 하나로 형성함을 특징으로 하는 반도체소자의 배선 형성방법.The method of claim 1, wherein the adhesion metal, the wiring layer, and the anti-reflection film are formed by any one of a physical vapor deposition method and a chemical vapor deposition method.
KR1019960071462A 1996-12-24 1996-12-24 Method for forming an interconnection of semiconductor device KR100209596B1 (en)

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