KR19980052338A - The delay error correction device of the clock phase shifter - Google Patents

Abstract

More particularly, the present invention relates to an apparatus for correcting a delay error due to voltage, temperature, and process error by determining a desired phase shift amount of a clock by measuring a shift amount due to delay reduction of a gate, So that the phase shift can be performed. The present invention includes a delay reduction measuring unit 210 for measuring a delay reduction of a gate in response to a system clock CLK, a phase shifting unit 220 for shifting a system clock CLK, And a shift phase selector 230 for selecting a corresponding one of the shift clocks of the phase shifter 220 and outputting phase-shifted clocks CLKs according to a control signal of the phase shifter 220.

Description

The delay error correction device of the clock phase shifter

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock phase shifter, and more particularly, to a delay error correction apparatus for a clock phase shifter that corrects an error using a gate delay.

In general, if you want to change the phase of a clock in a digital circuit, choose one of the following two methods.

1) There is a method of shifting the original system clock to a higher frequency secondary clock using a high frequency oscillator or a phase locked loop (PLL).

2) There is a method of shifting the phase of the clock using a simple gate delay.

However, the first of the two methods is advantageous in that the shifted phase is stable. However, since there is a problem that the analog circuit is built in the digital circuit and the size of the circuit is increased, Do not.

Thus, the second method is often used if a small amount of fluidity is allowed in the amount of phase to be shifted in general.

The conventional clock phase shifter is configured to shift the clock CLK by serially connecting a plurality of buffers as shown in the circuit diagram of Fig.

The operation of the conventional art will be described as follows.

First, when a phase is changed by shifting the clock CLK as shown in FIG. 2A, a plurality of buffers are connected in series. When a phase shift of 'T / 8' is desired as shown in FIG. 2B When 'N' gates are serially connected as shown in FIG. 1 (a) and a phase shift of 'T / 4' is desired as shown in FIG. 2 (c), '2N' .

Here, the gate delay of each buffer is T _g, and the period of the clock (CLK) is called 'T'.

Therefore, if a typical value of the gate delay for one buffer is T _G and a delay derating factor by voltage, temperature, and process is α, the gate delay (T _g ) for one buffer is α · T _G can be expressed.

If it is necessary to change the clock CLK to a clock CLK1 phase-shifted by 'T / 8' as shown in FIG. 1B, if it is necessary to use N buffers, the delay time T _{shift N-gate)} ) is as follows.

_{T shift (N-gate) =} N · T g = N · α · T G

At this time, if the delay reduction factor (α) is in the range of 0.5 to 1.5, the deviation (Δ _shift ) of the phase shift is as follows.

_{Δ shift = T shift.max - T shift.min} = N (1.5) · T G - N (0.5) · T G = N · T G

For example, if a clock (CLK) has a period of 100 ns and 1/4 of that, and a 25 ns shift is desired, 25 shifts of T _g = 1 ns will result in a deviation of Δ _shift = 37.5-12.5 = 25 ns.

When the clock CLK is to be phase-shifted by 'T / 4', the deviation ( _shift ) of the phase shift can be obtained by replacing 'N' in the above equation with '2N'.

However, such a conventional technique has a merit that the implementation circuit is simple, but there is a problem that the deviation of the phase shift becomes very large due to the connection of a plurality of gates because the gate delay changes due to the power supply voltage, the operating temperature,

Therefore, it is difficult to synchronize with the other circuits since it is difficult to predict the operation possibility in the actual chip in driving the circuit with the phase-shifted clock.

In order to solve the problems of the prior art, the present invention measures a shift amount due to delay reduction of a gate to determine a desired phase shift amount of a clock, thereby correcting a delay deviation due to voltage, temperature, and process error to perform a stable phase shift And a clock phase shifter for generating a delay error of the clock phase shifter.

1 is a configuration diagram of a clock phase shifter according to the prior art;

2 is a waveform diagram showing a clock phase shift;

3 is a block diagram of a delay error correction apparatus according to the present invention.

4 is a circuit diagram showing an embodiment of the present invention.

Description of the Related Art [0002]

210: Delayed tax reduction measuring unit

211, 212-1 to 212-2M, 221-1 to 221-M: D flip-

220: phase shift unit 230: shift phase selection unit

AN1, AN21 to AN2r: AND gate MUX: Multiplexer

In order to achieve the above-mentioned object, the present invention provides a system and method for controlling a delay time, comprising: delay decay measurement means for measuring a delay decay of a gate by inputting a system clock and outputting a control signal; phase shift means for shifting a system clock; And shift phase selecting means for selecting a corresponding one of the shift clocks of the phase shifting means according to a signal to output a phase-shifted clock.

Hereinafter, the present invention will be described in detail with reference to the drawings.

As shown in the block diagram of FIG. 3, when the desired phase shift amount is measured using the system clock (CLK) and the delay reduction of the gate is input and the desired phase shift amount is measured, the phase- A phase shift unit 220 for shifting the system clock CLK, and a phase shift unit 220 for outputting a phase shift signal according to a control signal of the delay reduction measurement unit 210. [ And a shift phase selector 230 for selecting a corresponding one of the shift clocks of the unit 220 and outputting the phase-shifted clocks CLKs.

Operation and effect of the embodiment of the present invention constructed as above will be described as follows.

Once initialized the system to normal operation delay tax measurement unit 210 to measure the amount of shift of the clock phase want the clock (CLK) as an input, each latch delay (T _g) connected in series to a plurality of D flip-flop having a And the desired phase shift amount is measured.

At this time, the phase shifting unit 220 sequentially shifts the clock CLK in the plurality of D flip-flops having the same latch delay (T _g ) as the respective D flip-flops constituting the delay reduction measurer 210.

Accordingly, when the delay reduction measurer 210 measures a desired phase shift amount and outputs a control signal, the shift phase selector 230 selects a corresponding output signal among a plurality of output signals of the phase shifting unit 220, And outputs the shifted clocks (CLKs).

In the meantime, the circuit for the 'T / 4' phase shift in the present invention is as shown in FIG.

First, the delay reduction measurement unit 210 sequentially connects the (2M + 1) D flip-flops 211 and 212-1 through 212-2M in series, and outputs the output power generation signal of the D flip- An AND gate AN1 for determining whether the (2M + 1) D flip-flops 211 and 212-1 through 212-2M are active by logically multiplying the output signal of the D flip flop 211, And AND gates AN21 to AN2r that logically multiply the non-inverted and inverted output signals of the two adjacent flip-flops of the flip-flops 212-2N-1 to 212-2M and outputs a control signal to the shift phase selector 230 .

The phase shifting unit 220 serially connects the M D flip-flops 221-1 to 221-M to output the output signals of the D flip-flops 221-N to 221-M to the shift phase selection unit 230 ).

The shift phase selector 230 comprises a multiplexer MUX1 for selecting one of the output signals of the phase shifter 220 according to a control signal of the delay reduction measurer 210. [ Unexplained reference numerals MUX2 are multiplexers.

The operation of the embodiment of the present invention will now be described.

First, it is assumed that the delay delay of the D flip-flop 211 in the delay reduction measurer 210 is 'T / 2' and that the delay is T _g of each of the D flip-flops 212-1 through 212-2M .

At this time, the delay reduction measuring unit 210 measures the delay time of the D flip-flops 212-1 to 212-2N by T / 2 2N · T _g if "if they meet the D flip-flops (211, 212-1~212-2M) to start the normal operation after Cree to" T / 2 "as long as the time elapsed (2N-1) th D The output signal of the flip-flop 212-2N-1 is '1', and the output signal of the 2N-th D flip-flop 212-2N is output as '0'.

Since the output signal of the D flip-flop 211 is '0' and the output signal of the D flip-flop 212-1 is '1', the delay decay measurement unit 210 outputs the output signal of the AND gate AN1 0 " to disable the operation of the D flip-flops 211 and 212-1 to 212-2M.

Accordingly, only the 2N-th D flip-flop 212-2N is fixed in a state where the input signal is '1' and the output signal is '0', and the remaining D flip-flop 212-2N + 1 The input signal and the output signal are fixed in the same state.

Therefore, only the AND gate AN21 outputs the signal '1' which inverts the output signal '0' of the D flip-flop 212-2N and the output of the D flip-flop 212-2N-1 And outputs a control signal of '1' to the shift phase selector 230 by multiplying the signal '1' by a logical sum.

The phase shifting unit 220 sequentially shifts the clock CLK through M series of D flip-flops 221-1 to 221-M. The M flip flops 221-1 to 221- -M) has the same latch and delay D flip-flop (212-1~212-2M) of the tax delay measurement unit (210) (T _g). That is, the latch delay in the N D flip-flops 221-1 to 221-N sequentially shifts the clock CLK by 'T / 4 = N · T _g ' and outputs to the shift phase selector 230 .

Accordingly, the shift phase selector 230 selects the output signal of the N-th D flip-flop 221-N of the phase shifting unit 220 by the multiplexer MUX1 according to the control signal of the delay reduction measuring unit 210 Thereby outputting the phase-shifted clock CLK2.

That is, even if the latch delay is reduced by voltage, temperature, or process, the shift phase selector 230 selects the M D flip-flops 221-1 of the phase shift unit 220 by the control signal of the delay reduction measurer 210 The output signal of the N-th D flip-flop 221-N is selected, so that the clock CLK2 shifted by N · T _g can be obtained.

The shift deviation (? _Shift ) in the delay reduction measurer 210 when the phase shift by 'T / 4' is performed is calculated as follows.

Where T _G is the typical delay of the latch, 0.5 alpha 1.5.

T / 2 _{2N · T G = 2N · α} · T G

T _shift = N · T _g = 1/2 (2N · T _g ) = N · α · T _G (N: not fixed)

1/2 (T / 2) = T / 4

Δ _shift = | T / 4-N · T _g |

_{= T g · | T / (} 4T g) -N |

Accordingly, the deviation (? _Shift )? T _g is _obtained because | T / (4T _g ) -N | 1.

That is, in the present invention will have a deviation (Δ _shift) as much as that is an integer multiple (N x) of the T / 4 is T _g.

For example, if T = 100 ns, T _G = 1 ns, 0.5? 1.5,? _Shift = | 1.5 * 16-0.5 * 50 | = 1 ns.

Therefore, it can be seen that the deviation (Δ _shift = T _g ) in the present invention is a very small value compared with the deviation (Δ _shift = N · T _g ) of the prior art, and thus a stable phase shift is performed.

As described in detail above, the present invention has an effect of performing stable phase shift operation by correcting a delay deviation due to voltage, temperature, and process error by determining a phase shift amount of a desired clock by using a simple gate delay.

Claims (6)

Delay decay measurement means for outputting a control signal for selecting a shifted clock (CLKs) by measuring a desired phase shift amount by inputting a system clock (CLK), phase shift means for sequentially shifting the system clock (CLK) And shift phase selection means for selectively outputting the corresponding clocks (CLKs) out of the phase-shifted clocks of the phase shifting means in accordance with the control signal of the delay reduction measure means. 2. The semiconductor memory device according to claim 1, wherein the delay reduction measuring means comprises: a latch having a delay time equal to a desired phase shift amount; a plurality of D flip-flops sequentially latching the output signal of the latch to measure a phase shift amount; And a logic gate block for outputting a control signal by logically calculating an output signal of the plurality of D flip-flops when a desired phase shift amount is measured in the D flip-flop. The apparatus of claim 2, further comprising a logic gate for disabling operation of a plurality of D flip-flops when a desired phase shift amount is measured. 3. The apparatus of claim 2, wherein the logic gate block comprises a plurality of AND gates for performing logical multiplication of non-inverted and inverted output signals of adjacent D flip-flops among the plurality of D flip flops. The apparatus as claimed in claim 1, wherein the phase shifting means comprises a plurality of D flip-flops for sequentially latching a clock (CLK) to output a phase-shifted clock. The apparatus as claimed in claim 2 or 5, wherein the plurality of D flip-flops have the same latch delay time.