KR100402928B1 - Apparatus for correcting delay error of clock phase shifter - Google Patents

Abstract

PURPOSE: An apparatus for correcting a delay error of a clock phase shifter is provided to correct a delay difference and stabilize a phase shift by using a gate delay to measure the amount of phase shift of a desired clock. CONSTITUTION: An apparatus for correcting a delay error of a clock phase shifter includes a delay reduction measurement part(210), a phase shift part(220), and a shift phase selection part(230). The delay reduction measurement part(210) measures the amount of phase shift of a desired clock according to a system clock and outputs a control signal to select a phase shift clock. The phase shift part(220) shifts the system clocks, sequentially. The shift phase selection part(230) outputs selectively the corresponding phase shift clock from the phase shift clocks of the phase shift part according to the control signal of the delay reduction measurement part.

Description

Delay error correction device of clock phase shifter

The present invention relates to a clock phase shifter, and more particularly, to an apparatus for correcting a delay error of a clock phase shifter for correcting an error using a gate delay.

In general, if you want to change the clock phase in a digital circuit, choose one of the following two methods.

1) There is a method of shifting the phase of the original system clock to a higher frequency secondary clock using a high frequency oscillator or phase locked loop (PLL).

2) There is a method of shifting the phase of the clock using a simple gate delay. By the way, the first of the two methods has the advantage that the shifted phase is stable, but there are problems such as the burden of designing the analog circuit embedded in the digital circuit and the problem of increasing the size of the circuit. .

Thus, the second method is often used if some fluidity is allowed for the amount of phase to shift.

The conventional clock phase shifter is configured to shift the clock CLK by connecting a plurality of buffers in series, as shown in the circuit diagram of FIG.

Referring to the operation process of the prior art as follows.

First, when the phase is changed by shifting the clock CLK as shown in FIG. 2 (a), a plurality of buffers are connected in series. When the phase shift as much as 'T / 8' is desired as shown in FIG. 1 (a) connects 'N' gates in series and 2 (c) shows '2/4' gates in series as shown in FIG. Will be configured.

Here, the gate delay of each buffer is Tg and the period of the clock CLK is referred to as 'T'. Therefore, if the formal value of the gate delay for one buffer is TG and the delay derating factor due to voltage, temperature, and process is α, the gate delay Tg for one buffer is α · TG. Can be expressed as

If the clock CLK is to be changed to the clock CLK1 shifted by 'T / 8' as shown in FIG. 1 (b), if 'N' buffers are required, the delay time required for shifting (Tshift (N -gate)) is given by

At this time, if the delay derating factor α has a range of "0.5 to 1.5", the deviation [Delta] shift of the phase shift is as follows.

For example, if the clock CLK has a period of 100 ns and wants a shift of 25 ns, that is 1/4, a 25 gate with TG = 1 ns is implemented, resulting in a deviation of Δshift = 37.5 -12.5 = 25 ns.

And. In the case where the clock CLK is to be phase shifted by 'T / 4', the deviation [Delta] shift of the phase shift can be obtained by replacing 'N' with '2N' in the above equation.

However, this conventional technology has the advantage that the implementation circuit is simple, but since the gate delay is changed due to the power supply voltage, the operating temperature, the process deviation, etc., there is a problem that the deviation of the phase shift becomes very large by connecting a plurality of gates.

Therefore, the prior art has difficulty in synchronizing with other circuits because it is difficult to predict the operability on the actual chip in driving the circuit with the phase shifted clock.

The present invention performs stable phase shifting by correcting delay variation caused by voltage, temperature, and process error by determining a desired phase shift amount of a clock by measuring a shift amount due to a delay reduction of a gate in order to solve the problems of the prior art. An object of the present invention is to provide a delay error correction device for a clock phase shifter.

1 is a block diagram of a conventional clock phase shifter.

2 is a waveform diagram showing a clock phase shift.

3 is a block diagram of a delay error correction apparatus according to the present invention.

4 is a circuit diagram showing an embodiment of the present invention.

*** Description of the symbols for the main parts of the drawings ***

210: delayed reduction measurement unit

211,212-1 to 212-2M.221-1 to 221-M: Difl-flop

220: phase shift unit 230: shift phase selector

AN1, AN21 ~ AN2r: And Gate MUX: Multiplexer

In order to achieve the above object, the present invention provides a delay derating measurement means for measuring a delay decay of a gate by inputting a system clock to output a control signal, a phase shift means for shifting a system clock, and control of the delay decay measurement means. And a shift phase selecting means for selecting a corresponding clock among the shift clocks of the phase shifting means and outputting a phase shifted clock according to the signal.

Hereinafter, the present invention will be described in detail with reference to the drawings.

According to an embodiment of the present invention, as shown in the block diagram of FIG. 3, the desired phase shift amount is measured by using the delay reduction of the gate by inputting the system clock CLK, and the phase shifted clock is measured by measuring the desired phase shift amount. A delay reduction measurement unit 210 for outputting a control signal for selecting a phase, a phase shift unit 220 for shifting a system clock CLK, and the phase shift according to a control signal of the delay reduction measurement unit 210. The shift phase selection unit 230 selects a corresponding clock among the shift clocks of the unit 220 and outputs a phase shifted clock CLKs.

Referring to the operation and effect of the embodiment of the present invention configured as described above are as follows.

When initialized and the system operates normally, the delay derating unit 210 measures a shift amount of a desired clock phase by inputting the clock CLK. The delay derating measurement unit 210 connects a plurality of flip-flops having a latch delay Tg in series. The desired amount of phase shift is measured.

In this case, the phase shifter 220 sequentially shifts the clock CLK in a plurality of flip-flops having the same latch delay Tg as the respective flip-flops constituting the delay deterioration measuring unit 210.

Accordingly, when the delayed derating measurement unit 210 measures a desired phase shift amount and outputs a control signal, the shift phase selector 230 selects a corresponding output signal among a plurality of output signals of the phase shift unit 220 to output a desired phase shift. Output clocks CLKs.

Meanwhile, the circuit for the embodiment for the 'T / 4' phase shift in the present invention is as shown in FIG.

First, the delay reduction measurement unit 210 sequentially connects (2M + 1) deflip-flops 211 and 212-1 to 212-2M in series, and outputs the inverted signal of the deflip-flop 212-1. An AND gate (AN1) for determining whether the (2M + 1) deflip-flops 211, 212-1 to 212-2M are active by ANDing the output signal of the deflip-flop 211, and the deflip To the AND gates AN21 to AN2r that non-invert and invert output signals of two adjacent flip-flops among the flops 212-2N-1 to 212-2M and output a control signal to the shift phase selector 230. Configure.

In addition, the phase shift unit 220 connects the M deflip-flops 221-1 to 221 -M in series, and shifts the output signal of the deflip-flops 221-N to 221 -M in the shift phase selector 230. ) To be entered.

The shift phase selector 230 includes a multiplexer MUX1 that selects one of the output signals of the phase shifter 220 according to the control signal of the delayed derating measurement unit 210.

Reference numeral MUX2 in the figure is a multiplexer.

Referring to the operation of the embodiment of the present invention configured as described above are as follows.

first. It is assumed that the latch delay of the deflip-flop 211 in the delay derating measurement unit 210 is 'T / 2' and the latch delay Tg of each of the deflip-flops 212-1 to 212-2M.

At this time, when the delay time in the de-flip flops 212-1 to 212-2N satisfies 'T / 2 = 2N · Tg', the delay derating measurer 210 determines the de-flip flops 211 to 212-1. 212-2M), the normal operation starts after 'T / 2' has elapsed, the output signal of the (2N-1) th flip-flop (212-2N-1) is '1', 2Nth The output signal of the flip-flop 212-2N is output as '0'.

In addition, since the output signal of the deflip-flop 211 is '0' and the output signal of the de-flip-flop 212-1 is '1', the delay derating measurement unit 210 outputs the output signal of the AND gate AN1. A value of '0' disables the operations of the flip-flops 211 and 212-1 to 212-2M.

Accordingly, in the delay derating unit 210, only the 2Nth flip-flop 212-2N is fixed with the input signal '1' and the output signal '0' and the remaining deflip-flops 212-2N + 1. 212-2M) are both fixed to the same state as the input signal and the output signal.

Therefore, the delay reduction measurement unit 210 outputs the signal '1' and only the AND gate AN21 inverts the output signal '0' of the deflip-flop 212-2N and the output of the flip-flop 212-2N-1. The control signal '1' is multiplied by the signal '1' and output to the shift phase selector 230.

In addition, the phase shift unit 220 sequentially shifts the clock CLK through the M deflected flops 221-1 to 221 -M connected in series, and the M deflected flops 221-1 to 221. -M) has the same latch delay Tg as the deflip-flops 212-1 to 212-2M of the delay derating measurement unit 210.

That is, the latch delays in the N deflip-flops 221-1 to 221 -N are 'T / 4 = N · Tg' to sequentially shift the clock CLK to output to the shift phase selector 230. do.

Accordingly, in the shift phase selector 230, the multiplexer MUX1 selects the output signal of the N-th flip-flop 221 -N of the phase shifter 220 by the control signal of the delay decay measurer 210. As a result, the clock shifted clock CLK2 is output.

That is, even if the latch delay is reduced by voltage, temperature, and process, the shift phase selector 230 causes the M deflect flops 221-1 of the phase shift unit 220 to be controlled by the control signal of the delay reduction measurement unit 210. By selecting the output signal of the N-th flip-flop 221-N out of 221-M, the clock CLK2 shifted by "N * Tg" can be obtained.

The shift deviation Δshift in the delay reduction measurement unit 210 when the phase shift by 'T / 4' is performed is as follows.

Here, TG: formal delay of the latch, 0.5 <α <1.5.

That is, in the present invention, the deviation (Δshift) is as much as T / 4 becomes an integer multiple (N times) of Tg.

For example, T = 100 ns, TG = 1 ns. When 0.5 <α <1.5, it becomes Δshift = | 1.5 * 16-0.5 * 50 | = 1ns.

Therefore, it can be seen that the deviation (Δshift = Tg) in the present invention is a very small value compared to the deviation (Δshift = N · Tg) of the prior art, so that a stable phase shift is performed.

As described in detail above, the present invention has an effect of performing a stable phase shift operation by correcting a delay variation caused by voltage, temperature, and process error by determining a phase shift amount of a desired clock using a simple gate delay.

Claims (6)

Delay derating measurement means for measuring a desired phase shift amount as an input of the system clock CLK and outputting a control signal for selecting the phase shifted clock CLKs; and phase shift means for sequentially shifting the system clock CLK. And a shift phase selecting means for selectively outputting the clocks (CLKs) among the clocks phase shifted by the phase shifting means in accordance with a control signal of the delayed derating measurement means. The delay derating measurement means according to claim 1, further comprising: a latch having a delay time equal to a desired phase shift amount, a plurality of deflip-flops for sequentially latching an output signal of the latch to measure the phase shift amount; A phase error correction device for a clock phase shifter, comprising: a logic gate block configured to output a control signal by logically calculating the output signals of the plurality of flip-flops when a desired amount of phase shift is measured in the flip-flop. 3. The apparatus of claim 2, further comprising a logic gate for disabling the operation of the plurality of flip-flops when the desired amount of phase shift is measured. 3. The apparatus of claim 2, wherein the logic gate block comprises a plurality of AND gates each of the non-inverted and inverted output signals of adjacent dip-flops among the plurality of dip-flops. 2. The apparatus of claim 1, wherein the phase shifting means comprises a plurality of deflip-flops for sequentially latching clocks (CLK) to output a phase shifted clock. 6. The apparatus of claim 2 or 5, wherein the plurality of deflip-flops have the same latch delay time.