KR19980048206A - Most transistor with double gate structure and manufacturing method - Google Patents

Abstract

1. Fields to which the invention described in the claims belong

Semiconductor device manufacturing.

2. The technical problem to be solved by the invention

When forming SOI type double gate MOSFET, it is necessary to go through CMP 2-3 times in order to form double gates of front gate and back gate, and solves the problem of low productivity and complexity of bonding two wafers. To do so.

3. Summary of Solution to Invention

A back gate electrode buried by ion implantation is formed in one SOI wafer, and a front gate electrode is formed on top of the wafer.

4. Important uses of the invention

Used in the manufacture of semiconductor devices.

Description

Most transistor with double gate structure and manufacturing method

The present invention relates to a MOS transistor having a double gate structure and a method for manufacturing the same, and more particularly, to a silicon on insulator (SOI) type MOSFET and a method for manufacturing the same.

Double gate MOSFETs have been developed using SOI wafers with lower power consumption and faster operating speed than MOSFETs using bulk-Si or simple SOI wafers.

A method of fabricating a double gate MOSFET using a conventional SOI wafer will now be described with reference to FIGS. 1A to 1E.

First, as shown in FIG. 1A, a field oxide film 2 is formed on a predetermined portion on the first SOI wafer 1, and a back gate oxide film 3 is formed on the active region defined by the field oxide film. The N + back gate electrode 4 is formed thereon.

Subsequently, as shown in FIG. 1B, a CVD oxide film 5 is formed on the entire surface of the wafer on which the rear gate electrode 4 is formed.

Next, as shown in FIG. 1C, the second SOI wafer 7 having the BPSG film 6 formed thereon is bonded to the upper surface of the first SOI wafer by allowing the CVD oxide film 5 and the BPSG film 6 to adhere thereto. Here, reference numeral A denotes an adhesive surface.

Subsequently, as illustrated in FIG. 1D, the back surface of the first SOI wafer 1, that is, the surface opposite to the surface on which the N + back gate electrode 4 is formed, is polished by chemical mechanical polishing (CMP) to form the silicon layer of the first SOI wafer. After exposure, the front gate oxide film 9 and the N + front gate electrode 10 are sequentially formed on the exposed silicon layer, source and drain ion implanted, followed by annealing to anneal the silicon across the front gate electrode 10. N + source and drain 11 are formed in the layer region. In this manner, a MOSFET having a double gate structure is formed.

In the above-described prior art, the CMP, which is difficult to process, has to be performed 2-3 times to form the double gates of the front gate and the rear gate, and the manufacturing process is very difficult because the method of bonding the first wafer and the first wafer is used. It is complicated and the productivity is low, thereby causing impurity particles or defects due to the process, which greatly reduces the production yield, and is also disadvantageous in terms of manufacturing cost. Therefore, there is a problem that it is difficult to put to practical use.

An object of the present invention is to provide an SOI type double gate MOSFET having excellent characteristics and a method of manufacturing the same through a simplified process.

A MOS transistor having a double gate of the present invention for achieving the above object is an SOI wafer comprising a silicon substrate of a first conductivity type, an investment oxide film formed on the silicon substrate and a silicon layer formed on the investment oxide film, and the SOI wafer A front gate electrode of the second conductive type formed on the silicon layer via the gate oxide film, a source and drain region of the second conductive type formed on the silicon layer portion across the front gate electrode, and

And a buried type second conductive rear gate electrode formed on the silicon substrate corresponding to the lower portion of the front gate electrode.

In the method of manufacturing a MOS transistor having a double gate of the present invention for achieving the above object, a pad oxide film is formed on an SOI wafer formed of a first conductive silicon substrate, a buried oxide film formed thereon, and a silicon layer formed on the buried oxide film. And implanting a second conductive impurity into the substrate to form a second conductive buried layer on the substrate under the buried oxide film, and forming a gate oxide film and a second conductive gate electrode on the silicon layer. And sequentially forming an ion implantation barrier layer, counter-doping a first conductive impurity into the substrate, and ion implanting a second conductive impurity into the silicon conductive layer on both sides of the gate electrode. And forming a drain region.

1A to 1E are process flowcharts showing a method for manufacturing a SOI type double gate MOSFET according to the prior art;

2 is a cross-sectional structure diagram of an SOI type double gate MOSFET according to the present invention;

3A to 3E are process flowcharts showing a method for manufacturing an SOI type double gate MOSFET according to the present invention.

* Explanation of symbols for main parts of the drawings

20: p-type silicon substrate 21: investment oxide film

22: silicon layer 26: n + back gate electrode

27: gate oxide film 28: n + front gate electrode

32: n + source and drain regions

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2 is a cross-sectional view of an SOI type double gate NMOS transistor according to an embodiment of the present invention. As shown, the SOI type double gate PMOS transistor of the present invention is composed of a p-type silicon substrate 20, an buried oxide film 21 formed on the substrate 20 and a silicon layer 22 formed on the buried oxide film 21. An SOI wafer and an n + front gate electrode 28 formed on the silicon layer 22 of the SOI wafer with a gate oxide film 27 interposed therebetween, and on the silicon layer 22 across the front gate electrode 28. The n + source and drain regions 32 are formed, and the buried n + back gate electrodes 26 are formed on the silicon substrate 20 corresponding to the lower portion of the front gate electrode 28.

As described above, the SOI type double gate MOS transistor according to the present invention has a buried back gate electrode 26 formed by ion implantation into one SOI silicon wafer, and has a front gate electrode on top of the wafer. Therefore, as in the above-described prior art, since two wafers are bonded and polished for this purpose, impurity particles and defects caused by these processes can be prevented, thereby forming a MOSFET having excellent characteristics. .

Referring to FIGS. 3A to 3D, a method of fabricating an SOI type double gate NMOS according to an embodiment of the present invention is as follows.

First, as shown in FIG. 3B, a field oxide film is formed on a predetermined region of an upper SOI wafer composed of a p-type silicon substrate 20, an investment oxide film 21, and a silicon layer 22 as shown in FIG. 3A. The pad oxide film 24 is formed in the film. In this case, the buried oxide film is preferably formed to a thickness of 1000-3000Å, the upper SOI layer 22 is preferably formed to about 200-1500Å. The SOI layer 22 is formed by bonding or formed on silicon on implanted oxide (SIMOX).

Subsequently, after implanting the n-type impurity into the substrate at a high concentration, annealing is performed to form an n + layer 26 embedded in the substrate portion under the buried oxide film 21 as shown in FIG. 3C. In the ion implantation, ion implantation is performed at a high energy level such that ions can penetrate the SOI layer 22 and the buried oxide film 21.

Next, as shown in FIG. 3D, the gate oxide film 27, the n + polysilicon layer 28 for forming the gate electrode, and the nitride film 29 are sequentially formed on the SOI layer 22, and then patterned with a predetermined gate pattern. Thus, the front gate electrode 28 is formed. Subsequently, a counter ion implantation 30 of p-type impurities is performed to convert the n + buried layer 26 except for the lower portion of the front gate electrode 28 to the same p-type as the substrate. (28) A rear gate electrode 26 made of the n + buried layer is formed on the lower substrate. At this time, the nitride film 29 on the front gate electrode 28 is implanted with p-type impurity ions into the n + front gate electrode 28 during the counter ion implantation so that the gate electrode is not switched to n- or p- type. It acts as a counter doping barrier. The nitride film 29 is preferably formed to a thickness of 500-2000 kPa.

Next, as shown in FIG. 3E, the n-type impurity is implanted at high concentration and annealed to form n + source and drain regions 32 on the SOI layer 22 across the front gate electrode 28 to form a double gate. Complete the SOI type MOSFET having.

Although the embodiment has been described using NMOS as an example, the present invention can be applied to PMOS as well. In this case, the polarities of the ions implanted when forming the gate electrode and the source and the drain can be reversed.

As described above, the present invention, unlike the prior art, which bonds two wafers each having a back gate and a front gate formed thereon, forms a self-aligned back gate electrode by implanting ions into a SOI wafer. Form a gate MOSFET. Therefore, it becomes possible to form a double gate MOSFET through a simplified process compared to the prior art.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

According to the present invention, it is possible to improve productivity and production yield in the production of SOI-type MOSFETs, and to realize high-integrated MOSFETs having excellent characteristics.

Claims (10)

An SOI wafer comprising a first conductive silicon substrate, an buried oxide film formed on the silicon substrate, and a silicon layer formed on the buried oxide film; A front gate electrode of a second conductivity type formed on the silicon layer of the SOI wafer via a gate oxide film; A source and drain region of a second conductivity type formed in the silicon layer portion across the front gate electrode, and A morph transistor having a double gate including a buried type second conductive back gate electrode formed on the silicon substrate portion corresponding to the bottom of the front gate electrode. The method of claim 1, And a double gate, wherein the buried oxide layer and the silicon layer form a SIMOX SOI structure. The method of claim 1, And a double gate formed by adhering the silicon layer to the buried oxide film. Forming a pad oxide film on the SOI wafer including the first conductive silicon substrate, the buried oxide film formed thereon and the silicon layer formed on the buried oxide film; Implanting a second conductive impurity into the substrate to form a second conductive buried layer on a substrate portion below the buried oxide film; Sequentially forming a gate oxide film, a gate electrode of a second conductivity type, and an ion implantation barrier layer on a predetermined portion of the silicon layer; Counter doping a first conductive impurity into the substrate, And implanting a second conductive impurity to form a source and a drain region of a second conductive type on the silicon layer on both sides of the gate electrode. The method of claim 4, wherein The method of manufacturing a MOS transistor having a double gate characterized in that the thickness of the buried oxide film is formed to about 1000-3000Å. The method of claim 4, wherein The silicon layer of the SOI wafer is a MOS transistor manufacturing method having a double gate characterized in that formed to a thickness of about 200-1500Å. The method of claim 4, wherein And the ion implantation barrier layer is formed of a nitride film. The method of claim 4, wherein The ion implantation prevention layer is a MOS transistor manufacturing method having a double gate, characterized in that for preventing the first conductive impurities are injected into the gate electrode in the counter doping step. The method of claim 4, wherein And the second conductive buried layer region except for the region under the gate electrode is converted to the first conductive type by counter-doping the first conductive type impurity. The method of claim 9, The second conductive buried layer region corresponding to the lower portion of the gate electrode serves as a gate electrode, and forms a double gate structure with a gate electrode formed on the substrate surface. .