KR19980036502A - Semiconductor Chip Package - Google Patents
Semiconductor Chip Package Download PDFInfo
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- KR19980036502A KR19980036502A KR1019960055072A KR19960055072A KR19980036502A KR 19980036502 A KR19980036502 A KR 19980036502A KR 1019960055072 A KR1019960055072 A KR 1019960055072A KR 19960055072 A KR19960055072 A KR 19960055072A KR 19980036502 A KR19980036502 A KR 19980036502A
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- semiconductor chip
- chip package
- semiconductor
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Abstract
본 발명은 양면에 동종 또는 이종의 패턴이 형성된 반도체칩을 수용하여 실장밀도를 향상시키도록 한 반도체칩패키지에 관한 것이다.The present invention relates to a semiconductor chip package which accommodates semiconductor chips having the same or different patterns formed on both surfaces thereof to improve the mounting density.
본 발명의 목적은 반도체칩패키지의 크기를 증가시키지 않고 반도체칩패키지의 실장밀도를 향상시키도록 한 반도체칩패키지를 제공하는데 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor chip package for improving the mounting density of the semiconductor chip package without increasing the size of the semiconductor chip package.
이와 같은 목적을 달성하기 위한 본 발명에 의한 반도체칩패키지는 양면에 패턴이 형성된 반도체칩들을 수용하여 반도체칩패키지의 수직, 수평크기를 증대시키지 않고도 실장밀도를 향상시키는 것을 특징으로 한다.The semiconductor chip package according to the present invention for achieving the above object is characterized by improving the mounting density without accommodating the semiconductor chip formed with a pattern on both sides, without increasing the vertical, horizontal size of the semiconductor chip package.
Description
본 발명은 반도체장치의 제조방법에 관한 것으로, 더욱 상세하게는 양면에 동종 또는 이종의 패턴이 형성된 반도체칩을 조립하여 실장밀도를 향상시키도록 한 반도체칩패키지에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a semiconductor chip package for assembling semiconductor chips having patterns of the same type or different types formed on both surfaces thereof to improve mounting density.
최근, 전자기기의 고기능화, 소형화 추세에 맞추어 인쇄회로기판의 실장밀도를 증대시키기 위해 반도체칩패키지가 경박단소화되고 있다. 또한, 반도체칩의 고속화, 고기능화에 대응하기 위해 반도체칩패키지의 형태가 경박단소화, 다핀화되고 있다.In recent years, in order to increase the mounting density of printed circuit boards in accordance with the trend of high functionality and miniaturization of electronic devices, semiconductor chip packages have been reduced in size and weight. In addition, in order to cope with high speed and high functionality of the semiconductor chip, the form of the semiconductor chip package has been reduced in size, weight, and pinning.
지금까지는 반도체칩패키지의 경박단소화를 위해 반도체칩패키지 구조 자체에 대한 연구 개발이 주로 이루어져 왔다.Until now, the research and development of the semiconductor chip package structure itself has been mainly carried out in order to make the semiconductor chip package thin and short.
도 1a 및 도 1b는 종래 기술에 의한 웨이퍼의 평면도 및 저면도이다.1A and 1B are a plan view and a bottom view of a wafer according to the prior art.
도 1a에 도시된 바와 같이, 웨이퍼(1)의 상부면에 반도체칩들(3)의 패턴이 형성되어 있고, 웨이퍼(1)의 하부면에 반도체칩들의 패턴이 전혀 형성되어 있다.As shown in FIG. 1A, patterns of the semiconductor chips 3 are formed on the top surface of the wafer 1, and patterns of the semiconductor chips are not formed on the bottom surface of the wafer 1.
이와 같이 구성되는 웨이퍼의 제조방법을 간단히 살펴보면 다음과 같다.Looking at the manufacturing method of the wafer is configured as follows briefly.
먼저, 통상적인 웨이퍼 레벨의 공정을 이용하여 웨이퍼(1)의 상부면에 반도체칩들(3)의 패턴을 형성한다. 이렇게 처리된 웨이퍼(1)는 통상적인 반도체칩패키지의 조립공정을 거치게 된다. 이를 좀 더 상세히 언급하면, 웨이퍼(1)의 아무런 패턴이 형성되지 않은 하부면을 필요한 두께만큼 연마하여 웨이퍼의 두께를 얇게 한다. 이후, 웨이퍼(1)를 반도체칩들(3)의 크기로 각각 절단, 분리하는 공정과, 분리된 반도체칩들(3)을 리드프레임의 다이패드에 접착하는 공정과, 반도체칩의 본딩패드들과 리드프레임의 내부리드들을 대응하여 도전성 와이어로 와이어본딩하는 공정과, 와이어본딩된 반도체칩을 성형수지의 봉지체롤 봉지하는 공정 등을 실시하여 반도체칩패키지를 완성한다.First, patterns of the semiconductor chips 3 are formed on the top surface of the wafer 1 using a conventional wafer level process. The wafer 1 thus processed is subjected to the assembly process of a conventional semiconductor chip package. In more detail, the thickness of the wafer is made thin by grinding the lower surface on which no pattern is formed on the wafer 1 to the required thickness. Thereafter, the process of cutting and separating the wafer 1 into the size of the semiconductor chips 3, the process of adhering the separated semiconductor chips 3 to the die pad of the lead frame, and the bonding pads of the semiconductor chips. And a process of wire bonding the inner leads of the lead frame with conductive wires, and encapsulating the wire-bonded semiconductor chip with an encapsulation roll of a molding resin, thereby completing the semiconductor chip package.
그러나, 종래에는 상부면에만 패턴이 형성된 반도체칩을 수용하는 반도체칩패키지(5)는 실장밀도를 향상시키기 위해서는 도 2에 도시된 바와 같이, 동일 외부리드들(7)이 전기적으로 연결되도록 적층되어야 한다. 즉, 복수개, 예를 들어, 2개의 반도체칩을 적층하기 위해서는 2개의 반도체칩패키지(5)가 적층되어야 하므로 전체 반도체칩패키지의 높이가 높아졌다.However, in the related art, a semiconductor chip package 5 accommodating a semiconductor chip having a pattern formed only on an upper surface thereof should be stacked such that the same external leads 7 are electrically connected, as shown in FIG. do. That is, since two semiconductor chip packages 5 must be stacked in order to stack a plurality of semiconductor chips, for example, two semiconductor chips, the height of the entire semiconductor chip package is increased.
그래서, 이의 대안으로서 하나의 반도체칩패키지에 여러개의 반도체칩, 즉 이종 또는 동종의 반도체칩들을 탑재하여 전기적 특성을 향상시키거나 반도체칩 밀도를 향상시키는 방안이 제시되었다. 그러나, 성형수지로 이루어진 봉지체에 의해 한정되는 공간에 여러개의 반도체칩을 탑재하는 것은 반도체칩의 두께에 따른 문제, 반도체칩들간의 신뢰도 문제 등이 야기되었다.Thus, as an alternative, a method of improving electrical characteristics or improving semiconductor chip density by mounting several semiconductor chips, that is, heterogeneous or homogeneous semiconductor chips in one semiconductor chip package, has been proposed. However, mounting a plurality of semiconductor chips in a space defined by an encapsulation member made of a molding resin has caused problems due to the thickness of the semiconductor chips and reliability problems between the semiconductor chips.
따라서, 본 발명의 목적은 반도체칩패키지의 크기를 증가시키지 않고 반도체칩패키지의 실장밀도를 향상시키도록 한 반도체칩패키지를 제공하는데 있다.Accordingly, it is an object of the present invention to provide a semiconductor chip package designed to improve the mounting density of a semiconductor chip package without increasing the size of the semiconductor chip package.
도 1a 및 도 1b는 종래 기술에 의한 웨이퍼의 평면도 및 저면도.1A and 1B are plan and bottom views of a wafer according to the prior art;
도 2는 종래 기술에 의한 적층형 반도체칩패키지의 구조를 나타낸 정면도.Figure 2 is a front view showing the structure of a stacked semiconductor chip package according to the prior art.
도 3a 및 도 3b는 본 발명에 의한 반도체칩패키지를 위한 웨이퍼의 평면도 및 저면도.3A and 3B are plan and bottom views of a wafer for a semiconductor chip package according to the present invention.
도면의주요부분에대한부호의설명Explanation of symbols on the main parts of the drawing
1: 웨이퍼 3: 반도체칩 5: 반도체칩패키지 7: 외부리드 11: 웨이퍼 13,14: 반도체칩 15: 반도체칩패키지DESCRIPTION OF SYMBOLS 1 Wafer 3: Semiconductor chip 5: Semiconductor chip package 7: External lead 11: Wafer 13, 14: Semiconductor chip 15: Semiconductor chip package
이와 같은 목적을 달성하기 위한 본 발명에 의한 반도체칩패키지는 양면에 패턴이 형성된 반도체칩들을 수용하여 반도체칩패키지의 수직, 수평크기를 증대시키지 않고도 실장밀도를 향상시키는 것을 특징으로 한다.The semiconductor chip package according to the present invention for achieving the above object is characterized by improving the mounting density without accommodating the semiconductor chip formed with a pattern on both sides, without increasing the vertical, horizontal size of the semiconductor chip package.
이하, 본 발명에 의한 반도체칩패키지를 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, a semiconductor chip package according to the present invention will be described in detail with reference to the accompanying drawings.
도 2A 및 도 2B는 본 발명에 의한 반도체칩패키지를 위한 웨이퍼의 평면도 및 저면도이다.2A and 2B are a plan view and a bottom view of a wafer for a semiconductor chip package according to the present invention.
도 2A 및 도 2B에 도시된 바와 같이, 웨이퍼(11)의 상부면과 하부면에 반도체칩들(13),(14)의 패턴이 각각 형성되어 있다.As shown in FIGS. 2A and 2B, patterns of the semiconductor chips 13 and 14 are formed on the top and bottom surfaces of the wafer 11, respectively.
이와 같이 양면에 패턴들이 형성된 반도체칩들(13),(14)이 하나의 반도체칩패키지(15)에 수용되면, 반도체칩패키지(15)는 도 2의 2개의 반도체칩패키지(5)가 적층된 전체 높이보다 상당히 낮아 경박단소화를 이룩할 수 있다. 여기서, 반도체칩(13)의 상, 하부면에 동종 또는 이종의 반도체칩 패턴이 형성되어 있어도 무방하다.When the semiconductor chips 13 and 14 having patterns formed on both surfaces are accommodated in one semiconductor chip package 15, the semiconductor chip package 15 is stacked with two semiconductor chip packages 5 of FIG. 2. It is considerably lower than the overall height, which makes it possible to achieve light and thin shortening. Here, the same or different types of semiconductor chip patterns may be formed on the upper and lower surfaces of the semiconductor chip 13.
이상에서 살펴본 바와 같이, 본 발명은 양면에 동종 또는 이종의 패턴이 형성된 반도체칩을 반도체칩패키지에 수용하여 반도체칩패키지의 경박단소화를 이룩할 수 있다. 양면에 반도체칩들의 패턴들이 형성되어 양면의 반도체칩들 사이의 신뢰성이 각각의 반도체칩패키지에 수용된 반도체칩들의 신뢰성보다 향상된다.As described above, according to the present invention, a semiconductor chip package having semiconductor patterns of the same type or a heterogeneous pattern formed on both surfaces thereof may be accommodated in the semiconductor chip package, thereby achieving light and thin reduction of the semiconductor chip package. Patterns of semiconductor chips are formed on both sides, so that the reliability between the semiconductor chips on both sides is improved than the reliability of the semiconductor chips housed in each semiconductor chip package.
Claims (3)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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KR1019960055072A KR19980036502A (en) | 1996-11-18 | 1996-11-18 | Semiconductor Chip Package |
Applications Claiming Priority (1)
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KR1019960055072A KR19980036502A (en) | 1996-11-18 | 1996-11-18 | Semiconductor Chip Package |
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KR19980036502A true KR19980036502A (en) | 1998-08-05 |
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KR1019960055072A KR19980036502A (en) | 1996-11-18 | 1996-11-18 | Semiconductor Chip Package |
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1996
- 1996-11-18 KR KR1019960055072A patent/KR19980036502A/en not_active Application Discontinuation
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