KR19980033827A - Method for manufacturing field effect transistor of semiconductor device - Google Patents
Method for manufacturing field effect transistor of semiconductor device Download PDFInfo
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- KR19980033827A KR19980033827A KR1019960051604A KR19960051604A KR19980033827A KR 19980033827 A KR19980033827 A KR 19980033827A KR 1019960051604 A KR1019960051604 A KR 1019960051604A KR 19960051604 A KR19960051604 A KR 19960051604A KR 19980033827 A KR19980033827 A KR 19980033827A
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- film
- forming
- polysilicon film
- semiconductor device
- effect transistor
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000000034 method Methods 0.000 title claims abstract description 30
- 230000005669 field effect Effects 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 51
- 229920005591 polysilicon Polymers 0.000 claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 16
- 238000005468 ion implantation Methods 0.000 claims abstract description 6
- 238000010438 heat treatment Methods 0.000 claims description 8
- 125000006850 spacer group Chemical group 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims 2
- 230000001590 oxidative effect Effects 0.000 claims 2
- 239000010408 film Substances 0.000 description 44
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910021341 titanium silicide Inorganic materials 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Thin Film Transistor (AREA)
Abstract
1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION
반도체 장치 제조방법.Semiconductor device manufacturing method.
2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention
소오스/드레인간의 직렬저항을 감소시켜 소자의 구동성 향상 및 고속 동작을 가능하게 하기 위한 반도체 장치의 전계효과트랜지스터 제공하고자 함.It is to provide a field effect transistor of a semiconductor device to reduce the series resistance between the source and drain to improve device driveability and enable high-speed operation.
3. 발명의 해결방법의 요지3. Summary of Solution to Invention
반도체 장치에 있어서, 반도체 기판상에 절연층을 형성하는 단계; 상기 절연층상에 제1 폴리실리콘막을 형성하는 단계; 마스크없이 상기 제1 폴리실리콘막내에 소오스/드레인 이온주입 공정을 실시하는 단계; 소오스/드레인 형성용 식각 마스크를 사용하여 소오스/드레인 영역을 형성하는 단계; 전체구조 상부에 제2 폴리실리콘막, 게이트 절연막 및 제3 폴리실리콘막을 차례대로 형성하는 단계; 및 게이트 전극용 식각 마스크를 사용하여 상기 제3 폴리실리콘막, 게이트 절연막 및 제2 폴리실리콘막을 차례로 식각하여 게이트 전극 및 채널 패턴을 형성하는 단계를 포함해서 이루어진 반도체 장치의 전계효과트랜지스터 제조방법을 제공하고자 함.A semiconductor device, comprising: forming an insulating layer on a semiconductor substrate; Forming a first polysilicon film on the insulating layer; Performing a source / drain ion implantation process into the first polysilicon film without a mask; Forming a source / drain region using the source / drain forming etching mask; Sequentially forming a second polysilicon film, a gate insulating film, and a third polysilicon film on the entire structure; And forming a gate electrode and a channel pattern by sequentially etching the third polysilicon film, the gate insulating film, and the second polysilicon film by using an etching mask for a gate electrode, to provide a field effect transistor manufacturing method of a semiconductor device. To do so.
4. 발명의 중요한 용도4. Important uses of the invention
반도체 장치 제조 공정 중 전계효과트랜지스터 제조 공정에 이용됨.Used in the field effect transistor manufacturing process of semiconductor device manufacturing process.
Description
본 발명은 반도체 소자 제조 공정중 반도체 장치의 전계효과트랜지스터(MOSFET) 제조방법에 관한 것으로, 특히 소오스/드레인간의 직렬저항의 감소에 따른 소자의 구동성 향상 및 고속 동작을 가능하게 하기 위한 반도체 장치의 전계효과트랜지스터 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a field effect transistor (MOSFET) of a semiconductor device during a semiconductor device manufacturing process. It relates to a field effect transistor manufacturing method.
일반적으로, 씬 필름(Thin Film)을 사용하여 완전히 공핍된(Fully Depeleted) 소오스/드레인 영역 및 채널 영역을 갖는 SOI(Silicon On Insulator) 기판을 사용한 전계효과트랜지스터나 CMOS는 소자의 운영 전압(Operation Voltage)으로 1.5V 이하의 저전압을 사용하는 소자에 있어서 매우 유용하게 응용되고 있다.In general, a field effect transistor or a CMOS using a silicon on insulator (SOI) substrate with a fully depleted source / drain region and a channel region using thin film is used as an operation voltage of the device. ) Is very useful for devices that use low voltages of 1.5V or less.
도1은 종래기술에 따른 반도체 장치의 전계효과트랜지스터가 형성된 단면도로, 기판의 최상면에서 약 500Å 정도 아래쪽에 약 4000Å 정도 두께의 절연층(2)이 형성된 SOI(Silicon On Insulator) 기판(1) 상부에 통상적인 전계효과트랜지스터를 제작한 것을 도시한 것으로, 도면부호 3은 소오스/드레인 영역, 3a는 채널 영역, 4는 게이트 산화막 및 5는 게이트 전극을 각각 나타낸다.1 is a cross-sectional view in which a field effect transistor of a semiconductor device according to the prior art is formed, and an upper surface of a silicon on insulator (SOI) substrate 1 having an insulating layer 2 having a thickness of about 4000 kV is formed below about 500 m from the top of the substrate. The conventional field effect transistor is shown in Fig. 3, where reference numeral 3 denotes a source / drain region, 3a a channel region, 4 a gate oxide film, and 5 a gate electrode.
상기와 같은 SOI 기판을 사용한 전계효과트랜지스터의 경우 일반적인 벌크 실리콘 기판(Bulk Silicon Wafer)에 비해 래치-업(LATCH-UP)에 강하고, 저전압 소자에 유용하게 적용할 수 있으며, 또한 소자의 고집적이 용이하다는 장점이 있다.Field effect transistors using the SOI substrate as described above are more resistant to latch-up than conventional bulk silicon wafers, can be usefully applied to low-voltage devices, and are easy to integrate. Has the advantage.
그러나, 상기 SOI 기판은 상기와 같은 장점이 있는데도 불구하고 일반 기판에 비해 너무 고가이기 때문에 상기 종래 기술에서 보는 바와 같이 매우 얇은 필름을 사용할 수밖에 없는데, 이 때문에 소오스/드레인간의 저항이 점점 높아지게 되고, 이러한 높은 소오스/드레인간의 저항에 의해 구동 전류가 크게 떨어져 소자의 구동성 및 고속 동작을 방해하게 되는 등의 문제점이 있었다.However, even though the SOI substrate has the above advantages, it is very expensive compared to the general substrate, so that a very thin film can be used as shown in the prior art, and thus, the resistance between the source and the drain increases gradually. Due to the high source / drain resistance, there is a problem that the driving current is greatly reduced, which hinders the driveability and high-speed operation of the device.
상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 소오스/드레인간의 직렬저항을 감소시켜 소자의 구동성 향상 및 고속 동작을 가능하게 하기 위한 반도체 장치의 전계효과트랜지스터 제공하는데 그 목적이 있다.Disclosure of Invention The present invention devised to solve the above problems is to provide a field effect transistor of a semiconductor device for improving the driveability of the device and enabling high-speed operation by reducing the series resistance between the source and the drain.
도1은 종래기술에 따라 형성된 반도체 장치의 전계효과트랜지스터 단면도,1 is a cross-sectional view of a field effect transistor of a semiconductor device formed according to the prior art;
도2A 내지 도2D는 본 발명의 일실시예에 따른 반도체 장치의 전계효과트랜지스터 제조 공정 단면도,2A to 2D are cross-sectional views of a field effect transistor manufacturing process of a semiconductor device according to an embodiment of the present invention;
도3A 및 도3C는 본 발명의 다른 실시예에 따른 반도체 장치의 전계효과트랜지스터 제조 공정 단면도.3A and 3C are cross-sectional views of a field effect transistor fabrication process of a semiconductor device according to another embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 반도체 기판 12 : 열산화막11 semiconductor substrate 12 thermal oxide film
13 : 소오스/드레인 형성용 폴리실리콘막13: polysilicon film for source / drain formation
14 : 채널용 폴리실리콘막 15 : 게이트 산화막14 polysilicon film for channel 15 gate oxide film
16 : 게이트 전극용 폴리실리콘막16: Polysilicon Film for Gate Electrode
17 : 포토레지스트17 photoresist
상기 목적을 달성하기 위하여 본 발명은 반도체 장치에 있어서, 반도체 기판상에 절연층을 형성하는 단계; 상기 절연층상에 제1 폴리실리콘막을 형성하는 단계; 마스크없이 상기 제1 폴리실리콘막내에 소오스/드레인 이온주입 공정을 실시하는 단계; 소오스/드레인 형성용 식각 마스크를 사용하여 소오스/드레인 영역을 형성하는 단계; 전체구조 상부에 제2 폴리실리콘막, 게이트 절연막 및 제3 폴리실리콘막을 차례대로 형성하는 단계; 및 게이트 전극용 식각 마스크를 사용하여 상기 제3 폴리실리콘막, 게이트 절연막 및 제2 폴리실리콘막을 차례로 식각하여 게이트 전극 및 채널 패턴을 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a semiconductor device comprising: forming an insulating layer on a semiconductor substrate; Forming a first polysilicon film on the insulating layer; Performing a source / drain ion implantation process into the first polysilicon film without a mask; Forming a source / drain region using the source / drain forming etching mask; Sequentially forming a second polysilicon film, a gate insulating film, and a third polysilicon film on the entire structure; And etching the third polysilicon layer, the gate insulating layer, and the second polysilicon layer in order using an etching mask for a gate electrode to form a gate electrode and a channel pattern.
또한, 본 발명은 반도체 장치에 있어서, 반도체 기판상에 절연층을 형성하는 단계; 상기 절연층상에 제1 폴리실리콘막을 형성하는 단계; 마스크없이 상기 제1 폴리실리콘막내에 소오스/드레인 이온주입 공정을 실시하는 단계; 소오스/드레인 형성용 식각 마스크를 사용하여 소오스/드레인 영역을 형성하는 단계; 전체구조 상부에 제2 폴리실리콘막, 게이트 절연막 및 제3 폴리실리콘막을 차례대로 형성하는 단계; 게이트 전극용 식각 마스크를 사용하여 상기 제3 폴리실리콘막, 게이트 절연막 및 제2 폴리실리콘막을 차례로 식각하여 게이트 전극 및 채널 패턴을 형성하는 단계; 상기 게이트 전극 및 채널 패턴 측벽에 절연막 스페이서를 형성하는 단계; 전체구조 상부에 금속막을 형성하고, 열처리하여 상기 금속막을 상 변환시키는 단계; 및 상기 열처리 공정에 의해 상 변환되지 않은 금속막을 제거하는 단계를 포함하는 것을 특징으로 한다.The present invention also provides a semiconductor device comprising: forming an insulating layer on a semiconductor substrate; Forming a first polysilicon film on the insulating layer; Performing a source / drain ion implantation process into the first polysilicon film without a mask; Forming a source / drain region using the source / drain forming etching mask; Sequentially forming a second polysilicon film, a gate insulating film, and a third polysilicon film on the entire structure; Forming a gate electrode and a channel pattern by sequentially etching the third polysilicon layer, the gate insulating layer, and the second polysilicon layer using an etching mask for a gate electrode; Forming an insulating film spacer on sidewalls of the gate electrode and the channel pattern; Forming a metal film on the entire structure and performing heat treatment to phase-change the metal film; And removing the metal film not phase-converted by the heat treatment process.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도2A 내지 도2D는 본 발명의 일실시예에 따른 반도체 장치의 전계효과트랜지스터 제조 공정 단면도이다.2A to 2D are cross-sectional views of a field effect transistor manufacturing process of a semiconductor device according to an embodiment of the present invention.
먼저, 도2A는 반도체 기판(11) 상부에 열산화 공정에 의해 약 3000Å 내지 5000Å 정도 두께의 열산화막(12)을 성장시킨 다음, 전체구조 상부에 약 2000Å 내지 5000Å 정도 두께의 소오스/드레인 형성용 폴리실리콘막(13)을 약 570℃ 이하의 저온에서 비정질 상태로 증착한 것을 도시한 것이다.First, FIG. 2A shows a thermal oxide film 12 having a thickness of about 3000 kPa to 5000 kPa grown on the semiconductor substrate 11 by a thermal oxidation process, and then forming a source / drain of about 2000 kPa to 5000 kPa on the entire structure. The polysilicon film 13 is shown deposited in an amorphous state at a low temperature of about 570 ° C or lower.
이어서, 도2B는 상기 소오스/드레인 형성용 폴리실리콘막(13)에 대해 열처리하여 결정화한 후, 마스크없이 상기 결정화된 소오스/드레인 형성용 폴리실리콘막(13) 전면에 이온주입 공정을 실시한 다음, 소오스/드레인 형성용 마스크를 사용한 식각 공정에 의해 하부의 열산화막(12)이 노출될때까지 상기 소오스/드레인 형성용 폴리실리콘막(13)을 식각하여 소오스/드레인 영역(13a)을 형성한 것을 도시한 것이다.Subsequently, in FIG. 2B, the source / drain polysilicon film 13 is heat-treated and crystallized, and then an ion implantation process is performed on the entire surface of the crystallized source / drain polysilicon film 13 without a mask. The source / drain forming polysilicon layer 13 is etched to form a source / drain region 13a until the lower thermal oxide layer 12 is exposed by an etching process using a source / drain forming mask. It is.
계속해서, 도2C는 전체구조 상부에 채널용 폴리실리콘막(14)을 상기 소오스/드레인 형성용 폴리실리콘막(13) 증착시와 동일한 방법으로 증착하여 비정질 상태로 형성하고, 열처리하여 결정화한 후, 전체구조 상부에 게이트 산화막(15)과 게이트 전극용 폴리실리콘막(16)을 차례로 형성하고, 상기 게이트 전극용 폴리실리콘막(16)에 불순물 도핑 공정을 실시한 다음, 상기 게이트 전극용 폴리실리콘막(16) 상부에 포토레지스트를 도포하고, 게이트 전극용 마스크를 사용한 노광·현상 공정에 의해 게이트 전극용 포토레지스트 패턴(17)을 형성한 것을 도시한 것이다.Subsequently, in FIG. 2C, the channel polysilicon film 14 is deposited on the entire structure in the same manner as the source / drain polysilicon film 13 is deposited in an amorphous state, and heat-treated to crystallize. A gate oxide film 15 and a polysilicon film 16 for the gate electrode are sequentially formed on the entire structure, and an impurity doping process is performed on the polysilicon film 16 for the gate electrode, and then the polysilicon film for the gate electrode is formed. (16) It shows that the photoresist was apply | coated on the upper part, and the photoresist pattern 17 for gate electrodes was formed by the exposure and image development process using the mask for gate electrodes.
마지막으로, 도2D는 상기 게이트 전극용 포토레지스트 패턴(17)을 식각장벽으로 하부의 소오스/드레인 영역(13a)이 드러날때까지 상기 게이트 전극용 폴리실리콘막(16), 게이트 산화막(15) 및 채널용 폴리실리콘막(14)을 차례대로 식각하여 게이트 전극(16a) 패턴 및 채널 패턴(14a)을 형성한 다음, 상기 게이트 전극용 포토레지스트 패턴(17)을 제거한 것을 도시한 것이다. 미설명 부호 15a는 게이트 절연막 패턴을 나타낸다.Lastly, FIG. 2D shows the gate electrode polysilicon layer 16, the gate oxide layer 15, and the photoresist pattern 17 for the gate electrode until an underlying source / drain region 13a is exposed as an etch barrier. The channel polysilicon film 14 is sequentially etched to form the gate electrode 16a pattern and the channel pattern 14a, and then the photoresist pattern 17 for the gate electrode is removed. Reference numeral 15a denotes a gate insulating film pattern.
도3A 및 3C는 본 발명의 다른 실시예에 따른 반도체 장치의 전계효과트랜지스터 제조 공정 단면도로, 도면부호 21은 반도체 기판, 22는 열산화막 및 25a는 게이트 절연막을 각각 나타낸다.3A and 3C are cross-sectional views of a field effect transistor fabrication process of a semiconductor device according to another embodiment of the present invention, where 21 is a semiconductor substrate, 22 is a thermal oxide film, and 25a is a gate insulating film, respectively.
먼저, 도3A는 상기 일실시예의 도2D까지 형성한 다음, 전체구조 상부에 스페이서 형성용 산화막을 증착한 후, 상기 스페이서 형성용 산화막을 마스크없이 전면식각하여 채널 패턴(24a) 및 게이트 전극 패턴(26a) 측벽에 산화막 스페이서(28)를 형성한 것을 도시한 것이다.First, FIG. 3A is formed up to FIG. 2D of the embodiment, and then deposits a spacer forming oxide film on the entire structure, and then etches the spacer forming oxide film without a mask on the entire surface without a mask to form a channel pattern 24a and a gate electrode pattern ( 26a) shows the formation of the oxide film spacers 28 on the sidewalls.
이어서, 도3B는 전체구조 상부에 티타늄막(29)을 증착한 다음, 열처리하여 상기 소오스/드레인 영역(23a) 및 게이트 전극 패턴(26a) 상부에 티타늄실리사이드막()(29a)을 형성한 것을 도시한 것으로, 이때 상기 티타늄실리사이드막(29a)은 상기 열처리 공정에 의해 상기 소오스/드레인 영역(23a) 및 게이트 전극 패턴(26a)인 폴리실리콘막과 상기 티타늄막(29)이 반응하여 형성된다.Subsequently, FIG. 3B shows a titanium film 29 deposited over the entire structure, and then heat treated to form a titanium silicide film over the source / drain regions 23a and the gate electrode pattern 26a. ), Wherein the titanium silicide film 29a is formed of the polysilicon film and the titanium film (ie, the source / drain regions 23a and the gate electrode pattern 26a) by the heat treatment process. 29) are reacted and formed.
마지막으로, 도3C는 상기 열처리 공정에 의해 상기 소오스/드레인 영역(23a) 및 게이트 전극 패턴(26a)인 폴리실리콘막과 반응하기 않은 상기 산화막 스페이서(28)상의 티타늄막(29)을 제거하여 Salicide(Self Aligned Silicide Gate) 구조의 전계효과트랜지스터를 형성한 것을 도시한 것으로, 본 발명의 일실시예에 비해 소오스/드레인간의 직렬 저항을 더 감소시킬 수 있다.Finally, FIG. 3C shows a salicide by removing the titanium film 29 on the oxide spacer 28 that has not reacted with the polysilicon film that is the source / drain region 23a and the gate electrode pattern 26a by the heat treatment process. It is shown that the field effect transistor having a structure of (Self Aligned Silicide Gate) is formed, and the series resistance between the source and the drain can be further reduced as compared with the embodiment of the present invention.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능함이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.
상기와 같이 이루어지는 본 발명은 일반적인 벌크 실리콘 기판(Bulk Silicon Wafer)을 사용하여 채널 영역의 두께는 얇게, 소오스/드레인 영역은 소오스/드레인간의 직결 저항을 최소화할 수 있을 정도의 두께로 형성함으로써, 소오스/드레인간의 직렬저항을 감소시켜 소자의 구동성 향상 및 고속 동작을 가능할 수 있으며, 또한 래치-업 특성이나 저전압 운용 소자 또는 고집적이 용이하다는 장점을 갖는 SOI 기판과 동일한 또는 그 이상의 소자 특성을 갖는 전계효과트랜지스터를 제조할 수 있어 소자의 수율 향상 및 비용 절감의 효과가 있다.In the present invention made as described above, the thickness of the channel region is made thin by using a bulk silicon wafer, and the source / drain regions are formed to have a thickness sufficient to minimize the direct resistance between the sources and the drains. Reduced series resistance between / drain enables improved device driveability and high-speed operation, and also has the same or better device characteristics as SOI substrates with the advantages of latch-up characteristics, low voltage operating devices, or high integration ease Since the effect transistor can be manufactured, there is an effect of improving the yield and cost of the device.
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