KR19980021715U - Semiconductor package - Google Patents
Semiconductor package Download PDFInfo
- Publication number
- KR19980021715U KR19980021715U KR2019960035021U KR19960035021U KR19980021715U KR 19980021715 U KR19980021715 U KR 19980021715U KR 2019960035021 U KR2019960035021 U KR 2019960035021U KR 19960035021 U KR19960035021 U KR 19960035021U KR 19980021715 U KR19980021715 U KR 19980021715U
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor package
- bonding
- semiconductor
- pad
- lead frame
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 238000003825 pressing Methods 0.000 claims abstract description 4
- 238000010438 heat treatment Methods 0.000 claims abstract description 3
- 239000000853 adhesive Substances 0.000 claims description 4
- 230000001070 adhesive effect Effects 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 238000000034 method Methods 0.000 description 18
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000002788 crimping Methods 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000006072 paste Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
Abstract
본 고안은 리드프레임을 와이어 없이 반도체의 패드와 직접적으로 본딩할 수 있는 반도체 패키지를 개시한다. 이 반도체 패키지는 가압과 가열에 의하여 본딩되는 본딩용 볼을 소정 위치에 구비한 리드프레임이 반도체 칩의 패드와 도전용 볼을 통하여 직접적으로 연결된 것을 특징으로 한다.The present invention discloses a semiconductor package capable of directly bonding a leadframe with a pad of a semiconductor without wires. The semiconductor package is characterized in that a lead frame having bonding balls bonded to each other by pressing and heating at a predetermined position is directly connected through pads and conductive balls of the semiconductor chip.
Description
본 고안은 반도체 패키지에 관한 것으로서, 특히 칩과 리드프레임의 연결구조를 달리한 반도체 패키지에 관한 것이다.The present invention relates to a semiconductor package, and more particularly, to a semiconductor package having a different connection structure between a chip and a lead frame.
일반적으로 반도체 소자의 칩 제조공정에서 설계된 단위셀을 배열하고 연결하기 위해 반도체 기판의 예정된 부분에 불순물의 선택적 도입공정, 절연층과 도전층을 적층하는 적층공정 및 패턴 마스크 공정등이 차례로 실행되어 각각의 칩에 집적회로가 형성된다.Generally, in order to arrange and connect unit cells designed in a chip manufacturing process of a semiconductor device, selective introduction of impurities into predetermined portions of a semiconductor substrate, a lamination process of laminating an insulating layer and a conductive layer, and a pattern mask process are sequentially performed. An integrated circuit is formed on the chip of.
이와 같이 형성된 집적회로 칩은 조립공정으로 보내져서 칩절단, 칩부착, 와이어 본딩, 몰드, 포밍, 트림공정 등의 순서로 진행하여 패키지화 된다.The integrated circuit chip thus formed is sent to an assembly process and packaged by proceeding in the order of chip cutting, chip attachment, wire bonding, mold, forming, trim process, and the like.
상기에서 언급한 반도체 패키지의 제조공정을 간단히 살펴보면 다음과 같다.Briefly looking at the manufacturing process of the above-mentioned semiconductor package is as follows.
먼저, 리드 프레임의 패드(Pad) 위에 낱개로 분리된 반도체 칩을 접착재(에폭시, 페이스트, 폴리이미드)로 부착시키는 다이 부착(Die Attach) 공정을 행한다.First, a die attach process is performed in which a semiconductor chip, which is separated separately, is attached onto a pad of a lead frame with an adhesive material (epoxy, paste, polyimide).
그런다음, 일정 온도에서 일정시간 동안 큐어링을 실시한 후, 반도체 칩의 본딩 패드와 리드 프레임의 인너 리드를 Au이나 Al과 같은 와이어로 상호 연결시켜 전기적으로 연결시키는 와이어 본딩 공정을 수행한다.Then, after curing for a predetermined time at a predetermined temperature, a wire bonding process for electrically connecting the bonding pad of the semiconductor chip and the inner lead of the lead frame by interconnecting with a wire such as Au or Al.
와이어 본딩이 끝나면, 에폭시 수지를 사용하여 반도체 칩을 인캡슐레이션 시키는 몰딩 공정을 수행한다. 상기 공정들을 통하여, 외부의 열적, 기계적 충격으로부터 반도체 칩을 보호할 수가 있는 것이다.After wire bonding is completed, a molding process of encapsulating a semiconductor chip using an epoxy resin is performed. Through the above processes, the semiconductor chip can be protected from external thermal and mechanical shocks.
몰딩 공정의 완료후에는, 실장에 용이하도록 아웃 리드를 도금하는 플래팅 공정, 디바이스의 종류, 기능 준위(Function Level) 작업 일자 등을 표시하는 마킹(Marking)공정, 기판에 실장이 용이하도록 아웃 리드를 소정 형태로 절곡하는 포밍 공정 및 리드를 지지하고 있는 댐바를 절단하는 트림공정을 진행하여 반도체 패키지를 제조하는 것이다.After the molding process is completed, a plating process for plating out lead for easy mounting, a marking process for displaying the type of device, a date of function level work, and an out lead for easy mounting on a substrate. The semiconductor package is manufactured by performing a forming process of bending a shape into a predetermined shape and a trimming process of cutting a dam bar supporting the lead.
일반적으로 반도체 소자의 칩 제조공정에서 설계된 단위셀을 배열하고 연결하기 위해 반도체 기판의 예정된 부분에 불순물의 선택적 도입공정, 절연층과 도전층을 적층하는 적층공정 및 패턴 마스크 공정등이 차례로 실행되어 각각의 칩에 집적회로가 형성된다.Generally, in order to arrange and connect unit cells designed in a chip manufacturing process of a semiconductor device, selective introduction of impurities into predetermined portions of a semiconductor substrate, a lamination process of laminating an insulating layer and a conductive layer, and a pattern mask process are sequentially performed. An integrated circuit is formed on the chip of.
도1은 종래의 실시예에 따른 반도체 패키지의 단면도로서, 리드프레임과 반도체 칩을 와이어 본딩한 것이다.1 is a cross-sectional view of a semiconductor package according to a conventional embodiment, in which a lead frame and a semiconductor chip are wire bonded.
도 1을 참조하면, 종래의 반도체 패키지는 패들(Paddle; 1)위에 탑재된 반도체 칩(2)의 각 패드(3)와 리드프레임(4)의 각 인너리드를 하나씩 금(Au) 와이어(5)로 본딩시킨다.Referring to FIG. 1, a conventional semiconductor package includes a gold wire 5 each of an inner lead of each pad 3 and a lead frame 4 of the semiconductor chip 2 mounted on a paddle 1. Bond with).
도 2는 도1의 본딩부분(A)의 부분상세도로서, 본딩시 와이어(5)와 본딩 패드(3)는 본딩 볼(6)에 의하여 서로 결합된다.FIG. 2 is a partial detail view of the bonding portion A of FIG. 1, in which the wire 5 and the bonding pad 3 are bonded to each other by the bonding ball 6.
그러나, 종래의 반도체 패키지는 각 리드와 각 패드를 개별적인 와이어로 본딩을 시켜주어야 하기 때문에, 제조수율이 낮은 문제점을 가진다.However, the conventional semiconductor package has a problem in that the manufacturing yield is low because each lead and each pad must be bonded by separate wires.
따라서, 본 고안의 목적은 제조수율을 향상시킬 수 있는 반도체 패키지를 제공하는데 있다.Accordingly, an object of the present invention is to provide a semiconductor package that can improve the manufacturing yield.
도 1은 종래의 기술에 따른 반도체 패키지의 단면도.1 is a cross-sectional view of a semiconductor package according to the prior art.
도 2는 도1의 A부의 상세도.FIG. 2 is a detailed view of portion A of FIG. 1; FIG.
도 3는 본 고안의 실시예에 따른 반도체 패키지의 단면도.3 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention.
도 4는 도3의 A부의 상세도.4 is a detailed view of portion A of FIG. 3;
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
12 : 반도체 칩 14 : 리드프레임12 semiconductor chip 14 lead frame
14a : 본딩볼 14b : 접착제14a: bonding ball 14b: adhesive
16 : 본딩패드 18 : 몰드16: bonding pad 18: mold
본 고안에 따르면, 반도체 패키지는 가압과 가열에 의하여 본딩되는 본딩용 볼을 소정 위치에 구비한 리드프레임이 반도체 칩의 패드와 도전용 볼을 통하여 직접적으로 연결된 것을 특징으로 한다.According to the present invention, the semiconductor package is characterized in that the lead frame having a bonding ball bonded by pressing and heating at a predetermined position is directly connected through the pad of the semiconductor chip and the conductive ball.
(실시예)(Example)
이하, 첨부한 도면을 참조하여 본 고안의 바람직한 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention.
도3은 본 고안의 실시예에 따른 반도체 패키지를 나타낸 것이고, 도4는 도3의 A부분의 상세도이다.3 illustrates a semiconductor package according to an embodiment of the present invention, and FIG. 4 is a detailed view of portion A of FIG. 3.
도3과 도4를 참고하면, 반도체 칩(12)의 각 패드(16)와 전기적으로 연결되어야 하는 각 리드프레임(14)의 본딩 위치에는 본딩볼(14a)이 결합된 상태로 위치하고, 그 내측 끝단은 반도체 칩(12)의 패드 위치를 지나서 중앙부의 소정 위치까지 연장된 상태로 패드(16)와의 정렬위치에 맞추어서 위치된다. 리드프레임(14)과 패드(16)와의 전기적 연결은 압착에 의하여 이루어지는데, 정렬이 이루어진 상태에서 적정량의 열 공급과, 소정의 압력으로 가압하여 주므로써, 본딩 볼(14a)이 패드(16)와 본딩된다.3 and 4, a bonding ball 14a is positioned at a bonding position of each lead frame 14 to be electrically connected to each pad 16 of the semiconductor chip 12, and an inner side of the bonding ball 14a is coupled thereto. The end is positioned in accordance with the alignment position with the pad 16 in a state extending beyond the pad position of the semiconductor chip 12 to a predetermined position in the center portion. The electrical connection between the lead frame 14 and the pad 16 is made by crimping. The bonding ball 14a is applied to the pad 16 by pressurizing to a predetermined pressure and supplying a proper amount of heat in an aligned state. Is bonded with.
한편, 압착시의 흔들림에 의한 정렬 불량을 방지하기 위하여 리드프레임(14)의 내측단부는 압착전에 절연성의 접착제(14b)로서 반도체 칩(13)에 접착시키는 것이 바람직하다.On the other hand, in order to prevent misalignment due to shaking during crimping, the inner end of the lead frame 14 is preferably adhered to the semiconductor chip 13 as an insulating adhesive 14b before crimping.
본딩 공정의 완료후에는 통상의 방법에 따라 몰딩과 후속공정을 실시하여 반도체 패키지를 완성하게 된다.After completion of the bonding process, molding and subsequent processes are performed according to a conventional method to complete a semiconductor package.
이상에서 설명한 바와 같이, 본 고안은 반도체 패키지는 압착에 의하여 본딩 패드와의 본딩을 가능하게 하는 본딩 볼을 리드프레임의 소정 위치에 부착하고, 정렬 및 가압에 의하여 본딩 패드와 리드프레임을 본딩할 수 있도록 하므로써, 본딩공정시의 제조수율을 향상시키는 효과를 제공한다.As described above, according to the present invention, the semiconductor package may attach a bonding ball, which enables bonding with the bonding pad by pressing, to a predetermined position of the lead frame, and bond the bonding pad and the lead frame by alignment and pressure. By doing so, it provides an effect of improving the manufacturing yield during the bonding process.
여기에서는 본 고안의 특정 실시예에 대해서 설명하고 도시 하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있다. 따라서, 이하, 실용신안등록청구의 범위는 본 고안의 진정한 사상과 범위에 속하는 한 모든 수정과 변형을 포함하는 것으로 이해할 수 있다.Although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Therefore, hereinafter, the scope of the utility model registration request can be understood to include all modifications and variations as long as they fall within the true spirit and scope of the present invention.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019960035021U KR19980021715U (en) | 1996-10-22 | 1996-10-22 | Semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019960035021U KR19980021715U (en) | 1996-10-22 | 1996-10-22 | Semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR19980021715U true KR19980021715U (en) | 1998-07-15 |
Family
ID=53979905
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019960035021U KR19980021715U (en) | 1996-10-22 | 1996-10-22 | Semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR19980021715U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990000204A (en) * | 1997-06-03 | 1999-01-15 | 윤종용 | Connection method of bonding pad and internal lead of semiconductor chip by adhesive means and LOC type semiconductor chip package using same |
-
1996
- 1996-10-22 KR KR2019960035021U patent/KR19980021715U/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990000204A (en) * | 1997-06-03 | 1999-01-15 | 윤종용 | Connection method of bonding pad and internal lead of semiconductor chip by adhesive means and LOC type semiconductor chip package using same |
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