KR19980017089U - PCB for interface of semiconductor inspection equipment - Google Patents

PCB for interface of semiconductor inspection equipment Download PDF

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Publication number
KR19980017089U
KR19980017089U KR2019960030447U KR19960030447U KR19980017089U KR 19980017089 U KR19980017089 U KR 19980017089U KR 2019960030447 U KR2019960030447 U KR 2019960030447U KR 19960030447 U KR19960030447 U KR 19960030447U KR 19980017089 U KR19980017089 U KR 19980017089U
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KR
South Korea
Prior art keywords
socket
pcb
mounting portion
interface
inspection equipment
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KR2019960030447U
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Korean (ko)
Inventor
박용민
Original Assignee
문정환
엘지반도체 주식회사
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Application filed by 문정환, 엘지반도체 주식회사 filed Critical 문정환
Priority to KR2019960030447U priority Critical patent/KR19980017089U/en
Publication of KR19980017089U publication Critical patent/KR19980017089U/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
    • G01R31/2863—Contacting devices, e.g. sockets, burn-in boards or mounting fixtures
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
    • G01R31/2879—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Environmental & Geological Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

본 고안은 반도체 검사장비의 인터페이스용 피시비기판에 관한 것으로, 종래에는 1개의 피시비기판에 1개의 소켓을 설치할 수 있어서, 다른 종류의 패키지를 검사하기 위해서는 다른 피시비기판으로 교체하여야 하기 때문에 검사시간의 절감에 따른 생산성향상에 한계가 있는 문제점이 있었다. 본 고안 반도체 검사장비의 인터페이스용 피시비기판은 몸체의 일측에 SOP 검사용 소켓을 설치할 수 있는 제1 소켓설치부를 형성하고, 타측에는 DIP 검사용 소켓을 설치할 수 있는 제2 소켓설치부를 형성하며, 상기 제1 소켓설치부와 제2 소켓설치부 사이에는 나노-핵스 핀 설치부를 형성하여, 1개의 피시비기판으로 2가지 종류의 패키지를 검사할 수 있도록 함으로서, 종래와 같이 1개의 패키지를 검사한 후 피시비기판을 교체하는 경우보다 검사시간에 절감되어 생산성이 향상되는 효과가 있다.The present invention relates to a PCB substrate for the interface of the semiconductor inspection equipment, and conventionally, one socket can be installed on one PCB substrate, and the inspection time can be reduced because the PCB must be replaced with another PCB to inspect different types of packages. There was a problem that there is a limit to the productivity improvement. The PCB for the interface of the inventive semiconductor inspection equipment forms a first socket mounting portion for installing the SOP inspection socket on one side of the body, and forms a second socket installation portion for installing the DIP inspection socket on the other side. A nano-nuclear pin mounting portion is formed between the first socket mounting portion and the second socket mounting portion, so that two kinds of packages can be inspected with one PCB, and then one package is inspected as before. Compared to the case of replacing the board, the inspection time is reduced, thereby improving productivity.

Description

반도체 검사장비의 인터페이스용 피시비기판PCB for interface of semiconductor inspection equipment

제 1 도는 종래 반도체 검사장비의 인터페이스용 피시비기판를 보인 평면도.1 is a plan view showing a PCB for the interface of the conventional semiconductor inspection equipment.

제 2 도는 제 1 도의 소켓설치부에 설치되는 소켓을 보인 사시도.2 is a perspective view showing a socket installed in the socket mounting portion of FIG.

제 3 도는 제 1 도의 나노-핵스 핀 설치부에 설치되는 나노-핵스 핀을 보인 사시도.3 is a perspective view showing the nano-nuclear fins installed in the nano-nuclear fin installation portion of FIG.

제 4 도는 본 고안 반도체 검사장비의 인터페이스용 피시비기판을 보인 평면도.Figure 4 is a plan view showing a PCB substrate for the interface of the inventive semiconductor inspection equipment.

*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

2 : 소켓11 : 몸체2: socket 11: body

12 : 제1 소켓설치부13 : 제2 소켓설치부12: first socket mounting portion 13: second socket mounting portion

14 : 나노-핵스 핀 설치부14 nano-core pin installation

본 고안은 반도체 검사장비의 인터페이스용 피시비기판에 관한 것으로, 특히 2개의 소켓(SOCKET)을 설치하여 검사할 수 있도록 하는데 적합한 반도체 검사장비의 인터페이스용 피시비기판에 관한 것이다.The present invention relates to a PCB for the interface of the semiconductor inspection equipment, and more particularly to a PCB for the interface of the semiconductor inspection equipment suitable for enabling inspection by installing two sockets (SOCKET).

일반적으로 패키지를 검사하기 위해서는 소켓에 패키지를 설치하고, 검사장비와 소켓 사이의 인터페이스 역할을 하는 피시비기판의 상면에 소켓을 설치한 다음, 패키지의 전기적인 특성검사를 실시하게 되는데, 이와 같은 종래의 일반적인 패키지 검사용 소켓이 설치되는 피시비기판이 제 1 도에 도시되어 있는 바, 이를 간단히 설명하면 다음과 같다.In general, in order to inspect a package, a package is installed in a socket, and a socket is installed on an upper surface of a PCB to serve as an interface between the test equipment and the socket, and then electrical characteristics of the package are inspected. The PCB of the general package inspection socket is installed is shown in Figure 1, which is briefly described as follows.

제 1 도는 종래 반도체 검사장비의 인터페이스용 피시비기판을 보인 평면도이고, 제 2 도는 제 1 도의 소켓설치부에 설치되는 소켓을 보인 사시도이며, 제 3 도는 제 1 도의 나노-핵스 핀 설치부에 설치되는 나노-핵스 핀을 보인 사시도이다.1 is a plan view showing a PCB substrate for the interface of the conventional semiconductor inspection equipment, FIG. 2 is a perspective view showing a socket installed in the socket mounting portion of FIG. 1, and FIG. A perspective view showing a nano-nux fin.

도시된 바와 같이, 몸체(1)의 일측에 패키지를 수납한 소켓(2)이 설치되는 소켓설치부(3)가 형성되어 있고, 타측에는 다수개의 나노-핵스 핀(4)이 설치되며 소켓 어댑터와의 접촉부인 나노-핵스 핀 설치부(5)가 형성되어 있다.As shown, a socket mounting portion 3 is formed on one side of the body 1 is installed a socket (2) for storing the package, the other side is a plurality of nano-nuclear pin (4) is installed and the socket adapter The nano-nuclear pin installation part 5 which is a contact part with is formed.

그리고, 상기 소켓설치부(3)와 나노-핵스 핀 설치부(5) 사이에는 다수개의 회로배선(6)이 형성되어 있다.Further, a plurality of circuit wirings 6 are formed between the socket mounting portion 3 and the nano-nuclear pin mounting portion 5.

상기와 같이 구성되어 있는 피시비기판의 소켓설치부(3)에 소켓(2)을 설치하고, 납땜으로 소켓(2)을 고정한다. 그런 다음, 상기 나노-핵스 핀 설치부(5)에 수개의 나노-핵스 핀(4)을 설치한 후, 납땜으로 나노-핵스 핀(4)을 고정한다.The socket 2 is installed in the socket mounting portion 3 of the PCB, which is configured as described above, and the socket 2 is fixed by soldering. Then, after installing several nano-nucleated pins 4 in the nano-nuclear pin installation portion 5, the nano-nucleated pins 4 are fixed by soldering.

상기와 같은 상태에서 소켓(2)에 검사하고자 하는 패키지를 결합한 다음, 전기적인 특성검사를 실시한다.In the above state, the package to be inspected is coupled to the socket 2, and then the electrical characteristic test is performed.

그러나, 상기와 같은 종래 반도체 검사장비의 인터페이스용 피시비기판은 1개의 피시비기판에 1개의 소켓(2)을 설치할 수 있고, 다른 소켓(2)을 사용하기 위해서는 별도의 피시비기판이 필요하여 동일한 소켓 어댑터를 사용함에도 불구하고, 다른 피시비기판으로 교체해야 하므로 대량 생산공장에서 검사시간의 절감에 따른 생산성향상에 한계가 있는 문제점이 있었다.However, the PCB for the interface of the conventional semiconductor inspection equipment as described above may be provided with one socket 2 on one PCB, and in order to use another socket 2, a separate PCB is required to use the same socket adapter. In spite of using, there is a problem that there is a limit in productivity improvement due to the reduction of inspection time in the mass production plant because it has to be replaced with another PCB.

상기와 같은 문제점을 감안하여 안출한 본 고안의 목적은 1개의 피시비기판에 2개의 소켓을 설치하여 검사시간을 절감할 수 있도록 하는데 적합한 반도체 검사장비의 인터페이스용 피시비기판을 제공함에 있다.The object of the present invention devised in view of the above problems is to provide a PCB substrate for the interface of the semiconductor inspection equipment suitable for installing two sockets in one PCB substrate to reduce the inspection time.

상기와 같은 본 고안의 목적을 달성하기 위하여 몸체의 일측에 소켓을 설치하기 위한 제1 소켓설치부를 형성하고, 타측에 다른 종류의 소켓을 설치하기 위한 제2 소켓설치부를 형성하며, 상기 제1 소켓설치부와 제2 소켓설치부 사이에 소켓 어댑터와 연결되는 나노-핵스 핀 설치부를 형성하여서 구성된 것을 특징으로 하는 반도체 검사장비의 인터페이스용 피시비기판이 제공된다.In order to achieve the object of the present invention as described above to form a first socket mounting portion for installing a socket on one side of the body, to form a second socket installation portion for installing a different type of socket on the other side, the first socket There is provided a PCB for the interface of a semiconductor inspection equipment, characterized in that formed by forming a nano-nuclear pin installation portion connected to the socket adapter between the installation portion and the second socket installation portion.

이하, 상기와 같이 구성되는 본 고안 반도체 검사장비의 인터페이스용 피시비기판을 첨부된 도면의 실시예를 참고하여 보다 상세히 설명하면 다음과 같다.Hereinafter, with reference to the embodiment of the accompanying drawings of the PCB substrate for the interface of the subject innovation semiconductor inspection equipment configured as described above will be described in more detail.

제 4 도는 본 고안 반도체 검사장비의 인터페이스용 피시비기판을 보인 평면도로서, 도시된 바와 같이, 몸체(11)의 일측에는 패키지(예: SOP)를 장착한 소켓(2)을 설치하기 위한 제1 소켓설치부(12)를 형성하고, 타측에 다른 패키지(예: DIP)를 장착한 소켓(2)을 설치하기 위한 제2 소켓설치부(13)를 형성하며, 상기 제1 소켓설치부(12)와 제2 소켓설치부(13) 사이에 소켓 어댑터(미도시)와 연결되는 나노-핵스 핀 설치부(14)를 형성하여서 구성된다.4 is a plan view showing a PCB substrate for an interface of the inventive semiconductor inspection equipment. As shown in the drawing, a first socket for installing a socket (2) on which a package (for example, an SOP) is mounted on one side of the body 11 is shown. The second socket installation part 13 is formed to form an installation part 12, and to install the socket 2 on which the other package (eg, DIP) is mounted on the other side, and the first socket installation part 12 is formed. And a nano-nuclear pin installation unit 14 connected to a socket adapter (not shown) between the second socket installation unit 13 and the second socket installation unit 13.

즉, 1개의 피시비기판에 2개의 소켓(2)을 설치할 수 있도록 하였으며, 중앙부분에 소켓 어댑터(미도시)와 연결되는 나노-핵스 핀 설치부(14)를 형성한 것이다.That is, two sockets 2 can be installed on one PCB, and a nano-nuclear pin installation portion 14 connected to a socket adapter (not shown) is formed in the center portion.

상기와 같이 구성되는 본 고안 반도체 검사장비의 인터페이스용 피시비기판은 제1 소켓설치부(12)에 패키지(SOP)를 검사할 수 있는 소켓(2)을 장착하여 납땜하고, 제2 소켓설치부(13)에 다른 패키지(DIP)를 검사할 수 있는 소켓(2)을 장착하여 납땜한다.The PCB for the interface of the inventive semiconductor inspection equipment constructed as described above is soldered by mounting a socket 2 capable of inspecting a package SOP on the first socket installation part 12, and soldering the second socket installation part ( 13) Install and solder the socket (2) which can inspect another package (DIP).

상기와 같은 상태에서 SOP를 검사하고자 할 경우에는 제1 소켓설치부(12)에 고정된 소켓(2)에 SOP를 장착하고, 전기적인 특성검사를 실시하며, 이때 상기 제2 소켓설치부(13)에 설치된 소켓(2)에는 다른 패키지가 장착되지 않은 상태이어야 한다. 그리고, DIP를 검사하고자 할 경우에는 제2 소켓설치부(13)에 고정된 소켓(2)에 DIP를 장착하고, 전기적인 특성검사를 실시하는데, 이때 제1 소켓설치부(12)에 설치된 소켓(2)에는 패키지가 장착되지 않은 상태이어야 한다.When the SOP is to be inspected in the above state, the SOP is mounted on the socket 2 fixed to the first socket installation part 12, and the electrical property test is performed. In this case, the second socket installation part 13 Sockets (2) installed in the package shall be free of other packages. In addition, when the DIP is to be inspected, the DIP is mounted on the socket 2 fixed to the second socket installation part 13 and an electrical characteristic test is performed. In this case, the socket installed in the first socket installation part 12 is performed. (2) The package should not be mounted.

이상에서 상세히 설명한 바와 같이 본 고안 반도체 검사장비의 인터페이스용 피시비기판은 몸체의 일측에 SOP 검사용 소켓을 설치할 수 있는 제1 소켓설치부를 형성하고, 타측에는 DIP 검사용 소켓을 설치할 수 있는 제2 소켓설치부를 형성하며, 상기 제1 소켓설치부와 제2 소켓설치부 사이에는 나노-핵스 핀 설치부를 형성하며, 1개의 피시비기판으로 2가지 종류의 패키지를 검사할 수 있도록 함으로서, 종래와 같이 1개의 패키지를 검사한 후 피시비기판을 교체하는 경우보다 검사시간을 절감할 수 있어 생산성이 향상되는 용이한 효과가 있다.As described above in detail, the PCB for the interface of the inventive semiconductor inspection equipment forms a first socket mounting portion for installing a SOP inspection socket on one side of the body, and a second socket for installing a DIP inspection socket on the other side. Forming an installation portion, between the first socket installation portion and the second socket installation portion to form a nano-nuclear pin installation portion, by allowing one PCB to inspect two types of packages, one by one After inspecting the package, it is possible to reduce the inspection time than replacing the PCB, thereby improving productivity.

Claims (1)

몸체의 일측에 소켓을 설치하기 위한 제1 소켓설치부를 형성하고, 타측에 다른 종류의 소켓을 설치하기 위한 제2 소켓설치부를 형성하며, 상기 제1 소켓설치부와 제2 소켓설치부 사이에 소켓 어댑터와 연결되는 나노-핵스 핀 설치부를 형성하여서 구성된 것을 특징으로 하는 반도체 검사장비의 인터페이스용 피시비기판.A first socket mounting portion for installing a socket is formed on one side of the body, and a second socket mounting portion for installing another type of socket is formed on the other side, and a socket is formed between the first socket mounting portion and the second socket mounting portion. The PCB of the interface of the semiconductor inspection equipment, characterized in that formed by forming a nano-nuclear pin installation portion connected to the adapter.
KR2019960030447U 1996-09-21 1996-09-21 PCB for interface of semiconductor inspection equipment KR19980017089U (en)

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