KR19980015795A - In the MPEG-2 encoder, a differential pulse code modulator - Google Patents

Abstract

The present invention includes a latch unit 30 for inputting 8 bits of original image data (Org_data1, Org_data2) on a frame basis or field basis from a frame memory or a motion estimator (ME); Subtraction means 32 for subtracting the original image data (Org_data1, Org_data2) from the latch unit 30 and the motion compensation data (MCed_data1, MCed_data2) from the motion compensation means (MC); The data from the latch unit 30 and the subtracting unit 32 are stored by the write address signal Wadrs from the RAM controller 40 and the first and second RAMs 34 and 36; A third multiplexer (38) for selectively outputting image data of the first and second RAMs (34, 36) by a coding identification signal (inter_intra) input from the system control unit; Alignment means (42) for aligning the video data from the third multiplexer (38) by a latch enable signal (latch_en) from the RAM controller (40); A fourth multiplexer 44 for selectively outputting image data from the alignment means 42 by a selection signal SEL from the RAM controller 42; A RAM controller 40 for aligning the image data stored in the first and second RAMs 34 and 36 to the alignment means 42 through the third multiplexer 38 and outputting the image data to the fourth multiplexer 44 ).

Description

In the MPEG-2 encoder, a differential pulse code modulator

More particularly, the present invention relates to a differential pulse code modulator (DPCM) in an MPEG-2 encoder. More particularly, the present invention relates to a differential pulse code modulator (DPCM) RAM), and arranged in alignment means by a read address signal, and outputted, so that the DCT can be easily performed. [0002] This invention relates to a differential pulse code modulator in an MPEG-2 encoder.

1 is a block diagram illustrating a general image encoder. The image encoder includes a frame memory unit 100, a differential pulse code modulator 120, a DCT (DCT) 130, a quantizer 140, An inverse quantizer 160, an IDCT 170, an adder 180, and a motion compensator 190 (MC).

As is well known, the image encoder receives a current image signal input through the frame memory unit 100 and a previous image signal input from a motion compensator 190 (MC) to a differential pulse code modulator 120 The image data from the differential pulse code modulator 120 is input to the DC-DC converter 130 and is subjected to DC-DC conversion. Next, the image data subjected to DCT by the DCT transformer 130 is input to a quantizer 140 and quantized. The quantized data is subjected to run-length encoding and variable length encoding after zigzag scanning, .

In the image encoder of the MPEG-2 standard as described above, a differential pulse code modulator is required which is output as it is in the case of I-picture and in which the difference image signal is outputted between P-picture and B-picture .

In addition, the video signal input to the differential pulse code modulator is divided into an I-picture, a P-picture and a B-picture, and the video signal, for example, the previous screen, the differential screen and the current screen are output as they are. However, it is necessary to adjust the output value output from the differential pulse code modulator in order to reduce the conversion time while the DCT is efficiently performed in the DCT converter design.

When the original picture data input from the frame memory is frame data or field data and the motion compensation data input from the motion compensator is data predicted in a field form, for example, the picture structure (Pic_str) is a frame picture and the frame motion type frm_motion_type) is a field-based type, the input format is different, and proper address conversion is required.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above problems, and it is an object of the present invention to provide a method and apparatus for decoding motion compensation data, In the MPEG-2 encoder in which the discrete cosine transform can be easily performed by being stored in the storage means (RAM) by the write address signal from the controller (RAMCON) and then outputted to the alignment means by the read address signal, Code modulator.

According to an aspect of the present invention, there is provided an image processing apparatus including a latch unit for inputting eight bits of original image data in units of frames or fields from a frame memory or a motion estimator; Subtraction means for subtracting the original image data from the latch portion and the motion compensation data from the motion compensation means; First and second RAMs for storing data from the latch unit and the subtracting unit by a write address signal from the RAM controller and outputting the data by a read address signal; A third multiplexer for selectively outputting video data of the first and second RAMs according to a coding identification signal input from a system control unit; Alignment means for aligning image data from the third multiplexer by a latch enable signal from the RAM controller; A fourth multiplexer for selectively outputting image data from the alignment means in response to a selection signal from the RAM controller; And a ram controller which aligns the image data stored in the first and second RAMs to the alignment means through the third multiplexer and outputs the image data by the fourth multiplexer.

According to the present invention configured as described above, even when the original image data input from the frame memory in the MPEG-2 encoder is frame data or field data and the motion compensation data input from the motion compensator is predicted in the form of a field, The address signal is stored in the RAM, and the address signals are aligned and output to the aligning means by the read address signal, so that the DCT can be easily performed.

1 is a block diagram illustrating a general image encoder,

FIG. 2 is a block diagram showing an embodiment of a differential pulse code modulator in the MPEG-2 encoder according to the present invention;

3 is a block diagram showing a RAM controller (RAMCON) shown in FIG. 2;

4 is a timing chart showing the operation timing of the ram controller shown in Fig. 3,

FIG. 5 is a diagram showing the data sorting order of the sorting unit shown in FIG. 2. FIG.

Description of the Related Art [0002]

10 to 13: first to fourth FIFOs, 20: write address generator,

22: a read address generating unit,

23: write address conversion unit, 24: read address conversion unit,

25, 26, 38, 44: first, second, third and fourth multiplexers,

27: input data judging unit, 30: latch unit,

32: subtraction unit, 34,36: first and second RAM,

40: RAM controller (RAMCON), 42: Arrangement part.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, when the DCT is performed by the DCT, the conversion is performed in units of 8 × 8 blocks. The processing in units of 8 × 8 blocks is performed in the same manner in the differential pulse code modulator (DPCM) .

Table 1 below shows the addresses of the 8x8 image block data input to the differential pulse code modulator.

[Table 1]

0 1 2 3 4 5 6 78 9 abcde f10 11 12 13 14 15 16 1718 19 1a 1b 1c 1f20 21 22 23 24 25 26 2728 29 2a 2b 2c 2d 2e 2f30 31 32 33 34 35 36 3738 39 3a 3b 3c 3d 3e 3f

Here, when the 8.times.8 image block data is input from the frame memory or the motion estimator (ME) to the differential pulse code modulator, the data is converted into a latch to easily convert the data by the DC / And then outputs the result.

On the other hand, data of the currently designed encoder is processed two pixels at a time. When two-pixel data is input to the differential pulse code modulator, the following address data are input in the following order.

(0, 1), (2, 3), (4, 5), (6, 7), (8, 9), (a, b),

Here, the number indicates the address of each pixel made up of 8 bits.

After the data of the address is inputted to the differential pulse code modulator, the differential pulse code modulator outputs data of the address in the following order so that the calculation can be easily performed by the DC-DC converter.

(0, 4), (1,5), (2,6), (3,7), (8, c), (9, d), (a,

Here, the number indicates the address of each pixel made up of 8 bits.

2 is a block diagram of an embodiment of a differential pulse code modulator in the MPEG-2 encoder according to the present invention, in which the code modulator comprises a latch unit 30, a subtractor 32, Third and fourth multiplexers 38 and 44, a RAM controller 40 and an aligner 42. The first and second multiplexers 38 and 44 are connected to the first and second multiplexers 38 and 44, respectively.

First, 8 bits of original image data (Org_data1, Org_data2) in units of frames are input to the latch unit 30 from the frame memory or the motion estimator ME, and the motion compensation data inputted from the motion compensator (MC) (MCed_data1, MCed_data2) are input to the subtracter 32 by 8 bits.

The latch unit 30 inputs the original image data Org_data1 and Org_data2 to the first RAM 34 and the subtractor 32. The subtractor 32 subtracts the original image data Org_data1 and Org_data2 from the latch unit 30 The difference data between the original image data Org_data1 and Org_data2 from the motion compensator MC and the motion compensation data MCed_data1 and MCed_data2 from the motion compensator MC is input to the second RAM 36. [

Here, the first RAM 34 stores original image data (Org_data1, Org_data2), i.e., I-picture, from the latch unit 30, and the second RAM 36 stores the original image data Difference data, that is, a P-picture and a B-picture.

The I-picture and the P-picture and the B-picture stored in the first and second RAMs 34 and 36 are selectively output by the third multiplexer 38, The data of the first RAM 34 in which the original image data (Org_data1, Org_data2) as the I-picture is stored is output by the coding identification signal inter_intra inputted from the control unit (not shown) Coding method, the data of the second RAM 36, which is the P-picture or the B-picture, is stored.

Here, in the case of the intra coding scheme, for example, when the coding identification signal inter_intra outputted from the system control unit is 1, the third multiplexer 38 outputs the data of the first RAM 34, The first multiplexer 38 outputs the data of the second RAM 36 when the coding identification signal inter_intra outputted from the system controller is 0, for example.

On the other hand, when the RAM controller 40 (RAMCON) outputs a write address signal Wadrs, the video data of the latch unit 30 and the subtractor 32 are stored in the addresses of the first and second RAMs 34 and 36 . When the image data stored in the first and second RAMs 34 and 36 are output, the first and second RAMs 34 and 36 are turned on by the latch enable signal latch_en of the RAM controller 40, 36 are input to the sorting unit 42 through the first multiplexer 38 in units of four clocks, and are aligned.

Thereafter, the image data input to the alignment unit 42 is processed by 2 pixels, and the input data is processed in the order of (0, 1), (2, 3), (4, 5) (0, 4), (1, 5), (2, 6), (3, 7).

Here, the number indicates the address of each pixel made up of 8 bits.

3 is a block diagram showing the RAM controller shown in FIG. 2, wherein the RAM controller includes a write address generating unit 20, a read address generating unit 22, a write address converting unit 23, a read address converting unit 24 ), First and second multiplexers 25 and 26, and an input data determination unit 27. First, in order to facilitate understanding, each constituent block and signal input / output to / from this constituent block will be outlined.

The CLS signal is a system clock, and the RST signal is a reset signal operated in an active low. The macroblock start signal MBS indicates the start of the input of the video data by the output when the video data is input from the frame memory to the latch unit 30 and the subtractor 32, The storage from the 9th clock after the generation of the MBS to the first and second RAMs 34 and 36 is started.

The write address signal Wadrs is an address signal in which the data of the latch 30 and the subtractor 32 are stored in the first and second RAMs 34 and 36. The write enable signal WREN is Is a signal enabling data storage of the latch unit 30 and the subtraction unit 32 at the 9th clock after the macroblock start signal MBS.

The read address signal Radrs is an address signal for reading data stored in the first and second RAMs 34 and 36. The panel block start signal PBS is a macroblock start signal MBS ), And then starts outputting the data stored in the first and second RAMs 34 and 36 from the 140th clock.

The latch enable signal latch_en is a signal for selectively outputting the data stored in the aligner 42. The SEL signal is a signal for selectively outputting the data input from the aligner 42 to the second multiplexer 44, And outputs the selected signal.

On the other hand, the feature of motion estimation in MPEG-2 is classified based on a picture structure (picture structure) and a picture coding type, so that field prediction and frame prediction can be supported. In MPEG-2, a picture is a unit for coding different from an existing frame. A frame picture is coded on a frame-by-frame basis, and a field picture is coded on a field-by-field basis.

In addition, according to the picture structure of the picture coding extension in the MPEG-2 bit stream structure, pictures are classified as shown in Table 2 (MPEG IS: Table 6-13).

[Table 2]

Picture_structure meaning 00 Reserved 01 Top field 10 Bottom field 11 Frame picture

As shown in Table 2, the picture is divided into a frame structure picture and a field structure picture (Top Fied and Bottom field) according to the picture structure. The field picture can be a field structure only, It is possible. Therefore, only field prediction is possible in the field picture, but frame prediction and field prediction are possible in the frame picture.

On the other hand, when the picture structure signal Pic_str is a frame picture signal, for example, 11 and the frame motion type signal frm_motion_type is a field base signal, for example, 1, the input form is different, And outputs the selection signal Wadrs_sel.

Therefore, when the write address selection signal Wadrs_sel is output, the first multiplexer 25 outputs the write address signal Wadrs from the write address conversion unit 23, for example, the frame picture field address conversion unit, When the write address selection signal is not output, the write address signal Wadrs from the write address generation unit 20 is output.

The write address conversion unit 23 converts the frame data address into a field data address by a programmed logic array (PLA) shown in Table 3 below.

[Table 3]

First block 00000000 00000000 Second block 00100000 00100000

00000001 00000001 00100001 00100001

00000010 00000010 00100010 00100010

00000011 00000011 00100011 00100011

00000100 00001000 00100100 00101000

00000101 00001001 00100101 00101001

00000110 00001010 00100110 00101010

00000111 00001011 00100111 00101011

00001000 00010000 00101000 00110000

00001001 00010001 00101001 00110001

00001010 00010010 00101010 00110010

00001011 00010011 00101011 00110011

00001100 00011000 00101100 00111000

00001101 00011001 00101101 00111001

00001110 00011010 00101110 00111010

00001111 00011011 00101111 00111011

00010000 01000000 01100000 01100000

00010001 01000001 01100001 01100001

00010010 01000010 01100010 01100010

00010011 01000011 01100011 01100011

00010100 01001000 00110100 01101000

00010101 01001001 00110101 01101001

00010110 01001010 00110110 01101010

00010111 01001011 00110111 01101011

00011000 01010000 00111000 01110000

00011001 01010001 00111001 01110001

00011010 01010010 00111010 01110010

00011011 01010011 00111011 01110011

00011100 01011000 00111100 01111000

00011101 01011001 00111101 01111001

00011110 01011010 00111110 01111010

00011111 01011011 00111111 01111011

Third block 01000000 00000100 Fourth block 01100000 00100100

01000001 00000101 01100001 00100101

01000010 00000110 01100010 00100110

01000011 00000111 01100011 00100111

01000100 00001100 01100100 00101100

01000101 00001101 01100101 00101101

01000110 00001110 01100110 00101110

01000111 00001111 01100111 00101111

01001000 00010100 01101000 00110100

01001001 00010101 01101001 00110101

01001010 00010110 01101010 00110110

01001011 00010111 01101011 00110111

00011100 01101100 00111100

01001101 00011101 01101101 00111101

01001110 00011110 01101110 00111110

01111111 00011111 01101111 00111111

01010000 01000100 01110000 01100100

01010001 01000101 01110001 01100101

01010010 01000110 01110010 01100110

01010011 01000111 01110011 01100111

01010100 01001100 01110100 01110100

01010101 01001101 01110101 01110101

01010110 01001110 01110110 01110110

01010111 01001111 01110111 01110111

01011000 01010100 01111000 01110100

01011001 01010101 01111001 01110101

01011010 01010110 01111010 01110110

01011011 01010111 01111011 01110111

01011100 01011100 01111100 01111100

01011101 01011101 01111101 01111101

01011110 01011110 01111110 01111110

01011111 01011111 01111111 01111111

The fifth block 10000000 10000100 The sixth block 10100000 10100000

10000001 10000101 10100001 10100001

10000010 10000110 10100010 10100010

10000011 10000111 10100011 10100011

10000100 10001100 10100100 10101000

10000101 10001101 10100101 10101001

10000110 10001110 10100110 10101010

10000111 10001111 10100111 10101011

10001000 10010100 10101000 10110000

10001001 10010101 10101001 10110001

10001010 10010110 10101010 10110010

10001011 10010111 10101011 10110011

10001100 10011100 10101100 10111000

10001101 10011101 10101101 10111001

10001110 10011110 10101110 10111010

10001111 10011111 10101111 10111011

10010000 10000100 10110000 10100100

10010001 10000101 10110001 10100101

10010010 10000110 10110010 10100110

10010011 10000111 10110011 10100111

10010100 10001100 10110100 10101100

10010101 10001101 10110101 10101101

10010110 10001110 10110110 10101110

10010111 10001111 10110111 10101111

10011000 10010100 10111000 10110100

10011001 10010101 10111001 10110101

10011010 10010110 10111010 10110110

10011011 10010111 10111011 10110111

10011100 10011100 10111100 10111100

10011101 10011101 10111101 10111101

10011110 10011110 10111110 10111110

10011111 10011111 10111111 10111111

In addition, the field frame selection signal field_frame is a signal indicating whether the type of the DCT is Dct_type, for example, field DCT or frame DCT. When the input data is a frame picture For example, a read address (Radrs) signal from the read address converting section 24, and in the case of a field picture, a lead address (Radrs) signal from the read address generating section 22 do.

Then, the read address converting section 24 reads the field data address by the programmable logic array (PLA) shown in the following Table 4 and outputs it.

[Table 4]

First block 00000000 00000000 Second block 00100000 00100000

00000001 00000001 00100001 00100001

00000010 00000010 00100010 00100010

00000011 00000011 00100011 00100011

00000100 00001000 00100100 00101000

00000101 00001001 00100101 00101001

00000110 00001010 00100110 00101010

00000111 00001011 00100111 00101011

00001000 00010000 00101000 00110000

00001001 00010001 00101001 00110001

00001010 00010010 00101010 00110010

00001011 00010011 00101011 00110011

00001100 00011000 00101100 00111000

00001101 00011001 00101101 00111001

00001110 00011010 00101110 00111010

00001111 00011011 00101111 00111011

00010000 01000000 01100000 01100000

00010001 01000001 01100001 01100001

00010010 01000010 01100010 01100010

00010011 01000011 01100011 01100011

00010100 01001000 00110100 01101000

00010101 01001001 00110101 01101001

00010110 01001010 00110110 01101010

00010111 01001011 00110111 01101011

00011000 01010000 00111000 01110000

00011001 01010001 00111001 01110001

00011010 01010010 00111010 01110010

00011011 01010011 00111011 01110011

00011100 01011000 00111100 01111000

00011101 01011001 00111101 01111001

00011110 01011010 00111110 01111010

00011111 01011011 00111111 01111011

Third block 01000000 00000100 Fourth block 01100000 00100100

01000001 00000101 01100001 00100101

01000010 00000110 01100010 00100110

01000011 00000111 01100011 00100111

01000100 00001100 01100100 00101100

01000101 00001101 01100101 00101101

01000110 00001110 01100110 00101110

01000111 00001111 01100111 00101111

01001000 00010100 01101000 00110100

01001001 00010101 01101001 00110101

01001010 00010110 01101010 00110110

01001011 00010111 01101011 00110111

00011100 01101100 00111100

01001101 00011101 01101101 00111101

01001110 00011110 01101110 00111110

01111111 00011111 01101111 00111111

01010000 01000100 01110000 01100100

01010001 01000101 01110001 01100101

01010010 01000110 01110010 01100110

01010011 01000111 01110011 01100111

01010100 01001100 01110100 01110100

01010101 01001101 01110101 01110101

01010110 01001110 01110110 01110110

01010111 01001111 01110111 01110111

01011000 01010100 01111000 01110100

01011001 01010101 01111001 01110101

01011010 01010110 01111010 01110110

01011011 01010111 01111011 01110111

01011100 01011100 01111100 01111100

01011101 01011101 01111101 01111101

01011110 01011110 01111110 01111110

01011111 01011111 01111111 01111111

The fifth block 10000000 10000100 The sixth block 10100000 10100000

10000001 10000101 10100001 10100001

10000010 10000110 10100010 10100010

10000011 10000111 10100011 10100011

10000100 10001100 10100100 10101000

10000101 10001101 10100101 10101001

10000110 10001110 10100110 10101010

10000111 10001111 10100111 10101011

10001000 10010100 10101000 10110000

10001001 10010101 10101001 10110001

10001010 10010110 10101010 10110010

10001011 10010111 10101011 10110011

10001100 10011100 10101100 10111000

10001101 10011101 10101101 10111001

10001110 10011110 10101110 10111010

10001111 10011111 10101111 10111011

10010000 10000100 10110000 10100100

10010001 10000101 10110001 10100101

10010010 10000110 10110010 10100110

10010011 10000111 10110011 10100111

10010100 10001100 10110100 10101100

10010101 10001101 10110101 10101101

10010110 10001110 10110110 10101110

10010111 10001111 10110111 10101111

10011000 10010100 10111000 10110100

10011001 10010101 10111001 10110101

10011010 10010110 10111010 10110110

10011011 10010111 10111011 10110111

10011100 10011100 10111100 10111100

10011101 10011101 10111101 10111101

10011110 10011110 10111110 10111110

10011111 10011111 10111111 10111111

On the other hand, when the macro block start signal MBS is inputted, the data is delayed by 9 clocks and then stored in the first and RAMs 34 and 36. This is because the input data is delayed while passing through the latch unit 30 .

When the data of the first and the RAMs 34 and 36 are read out, data is read out after the 140th panel block start signal PBS is outputted after the macroblock start signal MBS, Two pixels are output for one clock, and two addresses are output for one clock.

FIG. 4 is a timing diagram showing the operation timing of the ram controller shown in FIG. 3. Here, the write address signal Wadrs is outputted at the 9th clock after the start of the macro block start signal MBS, Then, a panel block start signal (PBS) is outputted at the 140th clock and the read address signal (Radrs) is outputted.

FIG. 5 is a diagram showing a data sorting order of the sorting unit shown in FIG. 2. Here, the drawing shows the third and fourth multiplexers 38 and 44 and the sorting unit 42. FIG. The alignment unit 42 includes first to fourth FIFOs 10 to 13. First, the data stored in the first and second RAMs via the third multiplexer 38 are read out by the read address signal Radrs of the RAM controller 40 in units of two pixels in the order of the first FIFO 10, the third FIFO 12 ), The second FIFO 11, and the fourth FIFO 13 in that order.

The first data and the second data of the first and second FIFOs 10 and 11 and the data of the third and fourth FIFOs 12 and 13 are latched by the latch enable signal latch_en of the RAM controller 40 The first data, and the second data.

It should be noted that the drawings are not intended to limit the technical scope of the present invention to the embodiments shown in the drawings in order to facilitate understanding of the present invention.

As described above, according to the present invention, even when the original image data input from the frame memory in the MPEG-2 encoder is frame data or field data and the motion compensation data input from the motion compensator is predicted in the form of a field, The read address signal is stored in the RAM by the write address signal, and is output to the aligning means by the read address signal. Thus, the DCT can be easily performed.

Claims (9)

A latch unit 30 for inputting 8 bits of original image data (Org_data1, Org_data2) in units of frames or fields from a frame memory or a motion estimator (ME); Subtraction means 32 for subtracting the original image data (Org_data1, Org_data2) from the latch unit 30 and the motion compensation data (MCed_data1, MCed_data2) from the motion compensation means (MC); The data from the latch unit 30 and the subtracting unit 32 are stored by the write address signal Wadrs from the RAM controller 40 and the first and second RAMs 34 and 36; A third multiplexer (38) for selectively outputting image data of the first and second RAMs (34, 36) by a coding identification signal (inter_intra) input from the system control unit; Alignment means (42) for aligning the video data from the third multiplexer (38) by a latch enable signal (latch_en) from the RAM controller (40); A fourth multiplexer 44 for selectively outputting image data from the alignment means 42 by a selection signal SEL from the RAM controller 42; A RAM controller 40 for aligning the image data stored in the first and second RAMs 34 and 36 to the alignment means 42 through the third multiplexer 38 and outputting the image data to the fourth multiplexer 44 Wherein the difference pulse code modulator comprises: 2. The image processing apparatus according to claim 1, wherein the first RAM (34) stores original image data (Org_data1, Org_data2), i.e., I-picture, from the latch unit (30) (32), that is, a P-picture and a B-picture are stored in the differential pulse code modulator. The system according to claim 1, wherein the third multiplexer (38) comprises a first RAM (34) in which original video data (Org_data1, Org_data2), which is I-picture, is stored by a coding identification signal (inter_intra) And outputs the data of the second RAM 36 in which the difference image data which is a P-picture or a B-picture is stored in the inter-coding system. 2. The semiconductor memory device according to claim 1, wherein the RAM controller (40) comprises write address generating means for outputting a write address signal (Wadrs) and a write enable signal (WREN) at the ninth clock after the macroblock start signal (MBS) 20); A write address converting means (23) for converting the frame picture write address signal from the write address generating means (20) into a field picture write address signal; A read address generating means (22) for outputting a panel block start signal (PBS) at 140th clock after the macroblock start signal (MBS) is outputted and for outputting a read address signal (Radrs); A read address converting means (24) for converting the frame picture read address signal from the read address generating means (22) into a field read address signal; Input data determination means (27) for outputting a write address selection signal (Wadrs_sel) when the picture structure signal (Pic_str) is a frame picture signal and the frame motion type signal (frm_motion_type) is a field base signal; And selectively outputs a write address signal from the write address conversion means 23 and a write address signal from the write address generation unit 20 by a write address selection signal Wadrs_sel from the input data determination means 27 A first multiplexer (25) for receiving the first multiplex signal; A second multiplexer 26 for selectively outputting a read address signal from the read address converting means 24 and a read address signal from the read address generating section 22 by a field frame select signal (field_frame) from the system control section Wherein the difference pulse code modulator comprises: The method as claimed in claim 4, wherein the input of the video data by the macroblock start signal (MBS) starts from the frame memory to the latch unit (30) and the subtraction unit (32) Wherein the first and second RAMs (34, 36) start storing image data. The differential pulse code modulator as claimed in claim 1, wherein the first and second RAMs (34, 36) The semiconductor memory device according to claim 4, wherein the data of the latch unit (30) and the subtraction unit (32) are stored in the first and second RAMs (34, 36) by the write address signal (Wadrs) The data of the latch unit 30 and the subtracting unit 32 are stored in the first and second RAMs 34 and 36 at the 9th clock of the macroblock start signal MBS by the WREN Wherein the difference pulse code modulator is a differential pulse code modulator in an MPEG-2 encoder. The method as claimed in claim 4, wherein the data stored in the first and second RAMs (34, 36) are read out by the read address signal (Radrs) and the macroblock start signal (MBS) And the data stored in the first and second RAMs (34, 36) is output from the 140th clock of the first pulse width modulator. The differential pulse code modulator according to claim 4, wherein the write address conversion means (23) converts the frame data address into a field data address by a programmable logic array (PLA). 5. The differential pulse code modulator according to claim 4, wherein the read address conversion means (24) reads the field data address by a programmable logic array (PLA) and outputs it.