JP2000299867A - Moving picture decoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow a television receiver adopting an interlace scanning system to display a noninterlace scanning image signal of 60 frames per second by decoding a stream resulting from applying MPEG coding to the image signal with an inexpensive decoder. SOLUTION: A stream analysis section 2 of this moving picture decoder sequentially detects I, B, P picture codes from a coding stream and gives them to a frame abort section 4. The frame abort section 4 alternately aborts any of two B pictures between I, P pictures and between P, P pictures and gives a remaining code to a video decoding section 6. Thus, the video decoding section 6 decodes a frame code with number of frames less than 60 frames per second and gives the result to a display control section 8. The display control section 8 interlaces prescribed P pictures to read the remaining decoded frames by respective fields and a display device displays them interlaced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a moving picture decoding apparatus, and more particularly to, for example, MPEG (motion picture coding).
The present invention relates to a moving image decoding apparatus suitable for use in simply reproducing a high-definition image encoded by an experts group) method.

[0002]

2. Description of the Related Art For example, as a system for coding a moving image such as a television image or a computer image, an MPEG coding system using motion compensation interframe coding is being standardized. In the MPEG system, each frame is compression-encoded and transmitted by a P picture which is inter-coded by forward prediction and a B picture which is encoded by bi-directional prediction, with reference to an intra-coded I picture, or It was stored in a storage medium.

On the other hand, in recent years, high definition images such as high definition television (HDTV) have been known in the broadcasting field, and high resolution images such as SVGA (super video graphics array) have been known in the computer field. A sequential scan for displaying and an interlaced scan for displaying for each field are known.

[0004] When these are encoded by the above-mentioned MPEG system, for example, ATSC (advanced television syst)
ems committee), as shown in FIG. 8, for each moving image of each resolution, an aspect ratio representing an aspect ratio,
The frame frequency and the scanning method are standardized. Among them, the (720 × 1280) image called 720P only supports sequential scanning, and when a moving image of 60 frames per second is obtained, the display method such as the current television receiver uses the scanning method and Due to the difference in frame frequency,
The decoded moving image cannot be displayed as it is.

Therefore, conventionally, as a moving picture decoding apparatus for decoding a 720P moving picture signal as described above and displaying it on a display device such as a current television receiver, for example, an MPEG-compatible decoder corresponding to 720P, A converter using a progressive (sequential scanning) -interlace (interlaced scanning) conversion of the output is conceivable.

FIG. 9 shows an example of such an apparatus. In FIG. 9, a stream 500 encoded by the MPEG method is shown.
Is received by the stream analysis unit 50, and whether or not the stream is a 720P encoded stream is analyzed by detecting the header to detect whether the stream is a 720P encoded stream. If the stream is a 720P coded stream, each coded frame is detected, and the code is sequentially supplied to the video decoding unit 52. The video decoding unit 52 sequentially decodes the P picture and the B picture on the basis of the I picture in a process opposite to the encoding side, and sequentially supplies the results to the progressive-interlace conversion unit 54. The progressive-interlace conversion unit 52 receives the moving image signal of 60 frames per second decoded by the video decoding unit 52, sequentially and alternately reads the image signal of the odd field or the even field from each frame, and The image was converted into a moving image 502 of 60 fields, supplied to a display device such as a current television receiver, and sequentially displayed.

[0007]

However, in the above-mentioned conventional technique, the display speed of 60 fields per second (30 frames per second) is sufficient on the television receiver side, but the video decoding section requires (720 × 1280). ) Images every second
The ability to decode at a high processing speed of 60 frames is required, and there is a problem that the apparatus becomes expensive.

[0008] The present invention solves the above-mentioned problems, and effectively decodes and displays a signal obtained by encoding a moving image having a frame rate higher than the display speed of a display device using a video decoding unit having a low processing capability. It is an object of the present invention to provide a video decoding device capable of performing the above.

[0009]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, a moving picture decoding apparatus according to the present invention provides a moving picture decoding apparatus in which a moving picture signal having a predetermined frame frequency or higher is coded by a predetermined coding method. A video decoding device that receives a stream, decodes the stream into a video signal of a lower frame frequency, and displays the video signal on an interlaced display device. A stream analyzing unit that detects a code of each encoded frame from the encoded stream; a discarding unit that discards a code of an encoded frame for each predetermined frame among the encoded frames from the stream analyzing unit; A decoding method for receiving a code of a coded frame from the stream analyzing unit excluding a code of a discarded coded frame and decoding a moving image signal of a forward dimension frame When, characterized in that it comprises a display control means for displaying on the display device of the interlaced display mode is converted into each sequential field of each frame based on the moving image signal decoded by the decoding means.

In particular, a moving picture decoding apparatus according to the present invention receives a coded stream obtained by coding a moving picture signal of progressive scanning at 60 frames per second by an encoding method including inter-frame coding, and receives the stream from the stream. It is preferable to apply the present invention to a method in which a moving image signal of interlaced scanning at 60 fields per second is decoded and displayed on a display device.

In this case, the discarding means is a discarding means for discarding some of a plurality of B pictures inter-coded by bidirectional prediction among the respective encoded frames from the stream analyzing means. Then, the codes of the B pictures corresponding to the frame next to the frame to be displayed on the display means may be sequentially discarded.

[0012] In this case, the display control means converts the inter-frame coded P picture by forward prediction corresponding to the frame next to the discarded B picture in the moving picture signal decoded by the decoding means. The moving image signals of the remaining frames excluding the decoded moving image may be read out for each field and displayed on the display means.

On the other hand, in the moving picture decoding apparatus according to the present invention, the discarding means includes a part of the coded frames from the stream analyzing means, which has been inter-coded by bidirectional prediction.
B-picture discarding means for discarding all the codes of the pictures, wherein the decoding means sequentially decodes only I- and P-picture codes of only intra-coded I-pictures and P-pictures inter-coded by forward prediction. Decoding means may be used.

In this case, the display control means preferably reads out the decoded frames of the I picture and the P picture decoded by the decoding means as three or more fields, respectively, and displays them on the display device.

[0015]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a moving picture decoding apparatus according to the present invention. FIG. 1 shows an embodiment of a moving picture decoding apparatus according to the present invention. The moving picture decoding apparatus according to the present embodiment, for example, has (720 × 1280) pixels for each screen and has a frame frequency of 60
A decoding device that receives a coded stream in which a moving image signal of Hz, that is, a so-called 720P moving image signal is coded by the MPEG coding method, and decodes the coded stream, which is a current interlaced television receiver This is a simple display device that converts and displays a moving image with a field frequency of 60 Hz on a display device such as the above.

In particular, in the moving picture decoding apparatus of this embodiment, the MP
A frame discarding unit 4 for discarding some of the B-pictures inter-coded by bidirectional prediction among the EG-coded frames is provided in front of a video decoding unit 6 for decoding the coded frame. A display control unit 8 for thinning out some of the image signals obtained by decoding P-pictures obtained by inter-frame coding by forward prediction among the frames decoded by the decoding unit 6 and then displaying the images of the remaining frames in a field. Is a main feature point.

In order to facilitate understanding of this embodiment, the coded stream supplied to the moving picture decoding apparatus of this embodiment will be described together with the coding apparatus shown in FIG. Are supplied to the input unit 10 of the encoding device. The video signals F0, F1, F2, F3,. Video signal F0, F1, F
2, F3,... Are image signals of (720 × 1280) pixels for each frame, and are signals representing a moving image captured by a high-resolution camera or the like by sequential scanning at 60 frames per second. is there.

As shown in FIG. 2, for example, the encoding apparatus includes a subtractor 12 for generating an inter-frame difference value and an orthogonal transformation circuit for performing an orthogonal transformation on the difference value or a direct image signal.
14, a quantizing circuit 16 for quantizing the transform coefficient, a variable-length coding circuit 18 for further performing variable-length coding on the quantized transform coefficient using a Huffman code or the like, and an inverse quantization of the quantized code. An inverse quantization circuit 20, an inverse orthogonal transform circuit 22 for inversely transforming the inversely quantized code to the original transform coefficient, a frame memory 24 for temporarily storing the image signal of the inversely transformed previous frame, A motion compensation circuit 26 that obtains a motion vector from the image signal of the current frame and the current frame image signal to perform motion compensation, and adds the motion compensated image signal and the image signal from the inverse orthogonal transform circuit 22 to supply them to a frame memory 24. An addition circuit 28, a vector coding circuit 30 for coding the motion vector obtained by the motion compensation circuit 26, and control of each circuit to control the types of I, P, and B pictures of the generated coded frame. Control code representing Coding control unit 32 for outputting
And a stream generation circuit 34 for generating and outputting respective encoded frames including a control code, a variable length code, and a motion vector code into a predetermined encoded stream.

In such an encoding apparatus, for example, an I1 picture in an encoded stream shown in FIG. 3 is obtained by intra-frame encoding of an input F3 frame by an orthogonal transformation circuit 14, and the transform coefficient is quantized. Each is quantized by the circuit 16, further subjected to variable-length encoding by the variable-length encoding circuit 18, and formed into an encoded frame by the stream generating circuit 34.

Next, with respect to the P4 picture, the input F6 frame and the previous frame corresponding to the F3 frame stored in the frame memory 24 are motion-compensated by forward prediction in the motion compensation circuit 26, and the difference value is calculated as described above. Similarly to the above, an inter-frame coded frame including a code that is orthogonally transformed, quantized, and further subjected to variable length coding, and a motion vector code from the vector coding circuit 30 are generated.

Next, the B5 picture is motion-compensated by bidirectional prediction from the F3 frame in which the F4 frame has been intra-coded and the F6 frame in which the F4 frame has been inter-coded by forward prediction. The value is orthogonally transformed, quantized, and formed into a coded frame represented by a code obtained by variable length coding and a motion vector code. Similarly, the B6 picture is formed as an encoded frame in which the F5 frame is inter-coded by bidirectional prediction from the F3 frame and the F6 frame.

Next, the P7 picture is formed as an encoded frame obtained by performing motion compensation on the F9 frame using a frame corresponding to the F6 frame of the P4 picture as the previous frame and then performing forward prediction on the F9 frame. Next, the B8 and B9 pictures are formed as coded frames in which the F7 or F8 frame is inter-coded from the F6 and F9 frames by bidirectional prediction, respectively.

Similarly, a forward predicted P picture is formed every three frames, and two frames between them are formed as bidirectional predicted B pictures. The B2 and B3 pictures after the I1 picture are
Between the F3 frame and the F0 frame of the P0 picture previously coded by forward prediction, the F1 and F2 frames are coded frames respectively coded by bidirectional prediction. As a result, an encoded stream is formed in the order of the encoded frames shown in FIG. 3 and supplied to the moving picture decoding apparatus of the present embodiment.

Next, the details of the moving picture decoding apparatus according to the present embodiment will be described. As shown in FIG. 1, the moving picture decoding apparatus according to the present embodiment comprises a stream analyzing unit 2, a frame discarding unit 4, It includes a decoding unit 6 and a display control unit 8, and its output is connected to an interlaced display device such as a current television receiver.

The stream analysis unit 2 receives the encoded stream 200 supplied from the encoding side, analyzes the header, and sequentially detects the code of each encoded frame based on the syntax. In this embodiment, the stream separation circuit extracts the respective codes and sequentially supplies the codes to the frame decoding unit 6 via the frame discarding unit 4 when detecting that the stream is a 720P coded stream. In particular, in the present embodiment, the types of I, P, and B pictures of each encoded frame are detected, and the result is sent to the frame discarding unit 4, the video decoding unit 6, and the display control unit 8 to process the code or It includes a control circuit for instructing image processing, and supplies a code of an encoded frame via the frame discarding unit 4 together with each instruction.

The frame discarding unit 4 includes a stream analyzing unit 2
Is a circuit for sequentially receiving the codes of the respective coded frames from among them, and discarding some of the coded frames indicating the B picture among them. In this embodiment, for example, one input can be freely changed to two outputs. And a switching circuit that discards one output to the video decoding unit 6 and discards the other output is effectively applied. In particular, the B picture to be discarded in this embodiment is the B picture immediately after the frame to be displayed.

For example, the original moving picture frame shown in FIG.
By alternately displaying or not displaying the images at F0, F1, F2,..., A moving image of 30 frames per second can be obtained. Considering this from the F3 frame corresponding to the I1 picture, the odd-numbered frames of F3, F5, F7, F9,... Are frames to be displayed. Thereby, in the encoded frames I1, B2, B3, ..., among the frames corresponding to the even-numbered frames F2, F4, F6, ... of the original moving image frames, B3, B5, B9, B11, ... are B pictures to be discarded. This is because the following B3 picture among B2 and B3 pictures between I1 and P4 pictures, the previous B5 picture among B5 and B6 pictures between P4 and P7 pictures, and the subsequent B9 picture between P7 and P10 pictures.
The picture becomes the previous B11 picture between the P10 and P13 pictures. Hereinafter, of the two B pictures between the P pictures, the preceding one is followed by the latter one.

That is, the frame discarding unit 4 of the present embodiment
When two consecutive B pictures are detected on the basis of an I picture based on an I, P, B picture instruction from the stream analysis unit 2, the preceding, rear, front,. . . And supplies the other encoded frames to the video decoding unit 6 sequentially. Thereby, the number of encoded frames supplied to the video decoding unit 6 is reduced.

The video decoding unit 6 is a decoder compatible with MPEG, and decodes the code of each coded stream supplied via the frame discarding unit 4 in response to an instruction from the stream analysis unit 2. It is. More specifically,
For example, as shown in FIG. 4, a variable length decoding circuit 62, an inverse quantization circuit 64, an inverse orthogonal transform circuit 66, an adder 68, a vector decoding circuit 72, a motion compensation circuit 74, a frame memory
And a decoding circuit for decoding each code into the original moving image signal in a step substantially opposite to that on the encoding side.

The details of each section will be described.
Reference numeral 62 denotes a decoding circuit which detects a variable length code such as a Huffman code from each of the encoded frames and decodes the code into the code of the original transform coefficient. The code of the separated motion vector is supplied to the vector decoding circuit 72. The sign of the decoded transform coefficient is supplied to the inverse quantization circuit 64.

The inverse quantization circuit 64 is a conversion circuit for inversely transforming the code of the transform coefficient quantized on the encoding side into the original transform coefficient, and performs quantization based on an instruction from the control unit of the stream analysis unit 2. Inverse quantization is performed in steps. The inversely quantized transform coefficient is supplied to an inverse orthogonal transform circuit 66.

The inverse orthogonal transform circuit 66 is a transform circuit for inversely transforming the transform coefficient from the inverse quantization circuit 64 into the original pixel value.
For example, DCT (discrete cosine transf
orm) is a reproducing circuit for reproducing the converted image signal for each macro block. The reproduced image signal is
The data is supplied to the display control device 8 of FIG. 1 via the adder 68 or is temporarily stored in the frame memory 76.

On the other hand, the vector decoding circuit 72 is a decoding circuit for decoding the encoded motion vector, and the decoded motion vectors are sequentially supplied to the motion compensation circuit 74. The motion compensating circuit 74 is a motion compensating circuit that generates a current frame image signal in which the image signal of the previous frame from the frame memory 76 is motion-compensated with the motion vector from the vector decoding circuit 72. The motion-compensated image signal is added to the image signal from the inverse orthogonal transform circuit 66 by an adder 68, and the display control device 8
Supplied to

Returning to FIG. 1, the display control unit 8 is a circuit for converting the decoded image signal for each frame into field units and supplying the converted image signals to the display device. For example, the image signals are sequentially written from one port. Dual port RAM (random access memo) that can be read randomly from the other port
ry) and an AD converter that performs digital-to-analog conversion of the output. In particular,
In the present embodiment, the signal control circuit is a signal control circuit that thins out P pictures that are not displayed in accordance with an instruction from the stream analysis unit 2 and sequentially reads out the remaining frames for each field and supplies the frames to the display device. Non-display, display, non-display,. . . May be repeatedly controlled.

The operation of the moving picture decoding apparatus according to this embodiment in the above configuration will be described. First, when an encoded stream is supplied to the stream analyzing unit 2, the stream analyzing unit 2 analyzes the header and the like. Then, it detects whether or not the encoded stream is a 720P stream. If the stream is a 720P stream, each coded frame is sequentially supplied to the frame discarding unit 4 while detecting the type of each coded frame and the type of I, P, B picture. For example, the coded stream 200 supplied to the stream analyzer 2 is a coded stream I shown in the upper part of FIG.
.., B2, B3,..., The instruction of the code processing and display processing of each coded frame is based on the I1 picture, the frame discarding unit 4, the video decoding unit 6, and the display control unit 8 Supplied to

Next, when the frame discarding unit 4 first receives the code of the I1 picture based on the instruction from the stream analyzing unit 2, it resets and connects the I1 picture to the video decoding unit 6 for output. Next, when you receive the B2 picture,
The B2 picture is output while being connected to the video decoding unit 6. Next, when a B3 picture is received, switching to the discarding side is performed and the B3 picture is discarded. When the B3 picture has been discarded, it is connected to the video decoding unit 6 again to output a P4 picture. When a B5 picture is subsequently received, the picture is switched to the discard side and discarded.

Similarly, based on the instruction from the stream analysis unit 2, of the two consecutive B pictures, the preceding or succeeding B picture is alternately discarded, and the remaining B pictures and P pictures are sequentially video decoded. Output to the unit 6.
As a result, the encoded frames are supplied to the video decoding unit 6 as the middle streams I1, B2, P4,... Shown in FIG.

Next, upon receiving the I1 picture, the video decoding unit 6 performs intra-frame decoding by variable length decoding, inverse quantization, and inverse orthogonal transform in response to an instruction from the stream analyzing unit 2. Image signal of frame memory 76
Temporarily. Next, upon receiving the code of the B2 picture, the difference value is decoded from the transform coefficient in the same manner as described above,
The motion vector is decoded, and the original F1 frame is reproduced by bidirectional prediction from the previous frame (corresponding to the F0 frame in FIG. 3) and the frame after decoding the I1 picture stored in the frame memory 76. The reproduced B2 picture frames are sequentially output, and subsequently, the I1 picture is read from the frame memory 76 and supplied to the display control unit 8, respectively.

Next, when the P4 picture is supplied to the video decoding unit 6, the transform coefficient is decoded in the same manner as described above, and its motion vector is decoded. The original image signal is reproduced by the direction prediction. The reproduced image signal is temporarily stored in the frame memory 76 similarly to the P1 picture. Next, when the B6 picture is supplied, the difference value and the motion vector are decoded in the same manner as described above, and the original value is obtained by bidirectional prediction from the previous frame after decoding the I1 picture and the frame after decoding the P4 picture. Is reproduced. B6 played
The picture frame is output first, and then the P4 picture frame is read and supplied to the display control device 8.

Similarly, a P picture is decoded from the previous frame by forward prediction and temporarily stored in the frame memory 76, and a subsequent B picture is decoded from the previously decoded previous frame and subsequent frame by bidirectional prediction. It is decoded and reproduced to the original image signal. The reproduced image signal is output first from the B picture frame, then the P picture frame read from the frame memory 76 is output, and the image signal of each frame is sequentially output to the display control device 8. Supplied.

Next, when receiving the decoded frame of the B2 picture, the display control section 8 first stores the decoded frame, reads out the odd field, displays it on the display device, and further reads and displays the even field. . During this time, the decoded frames of the I1 picture are sequentially received and accumulated, and when the display of the B2 field is completed, the odd fields of the decoded frame of the I1 picture are similarly read and displayed, and then the even fields are read and displayed.

During this time, the B6 picture and the P4 picture are decoded and supplied, but only the decoded frame of the B6 picture is accumulated and becomes the next P picture following the I1 picture based on the instruction from the stream analyzer 2. When the frame display of the I1 picture is completed without storing the decoded frame of the P4 picture, the decoded frame of the B6 picture is field-displayed.

During this time, when the decoded frames of the B8 picture and the P7 picture are supplied, the decoded frames of the B8 picture are accumulated in the same manner as described above, and subsequently, the decoded frames of the P7 picture are accumulated. This time, since it is a decoded frame of the P picture next to the P4 picture which was not displayed, it is stored and displayed. Thus, when the display of the frame of the B6 picture is completed, the decoded frame of the B8 picture is field-displayed, and then the decoded frame of the P7 picture is similarly field-displayed.

Hereinafter, all the decoded frames of the B picture which are sequentially decoded are displayed in the field, and the decoded frames of the P picture during that period are alternately thinned out in accordance with the instruction from the stream analysis unit 2, and the non-display and display are repeated. To go. As a result, as shown in the lower part of FIG. 5, each of the fields is read out in a frame sequence B2, I1, B6,... Having half the frame frequency of the original coded stream I1, B2, B3,. By doing so, a moving image can be effectively displayed on a display device such as a television receiver of the current interlaced display.

As described above, according to the moving picture decoding apparatus of this embodiment, based on the I, P, and B instructions detected by the stream analyzing unit 2, the frame discarding unit 4 selects between the I and P pictures and After discarding one of the two B pictures between the P and P pictures, the decoding unit 6 decodes the remaining encoded frames, so that the processing speed is reduced when all encoded frames are decoded. In comparison, a processing performance of about two-thirds lower is sufficient, and an inexpensive video decoder can be applied.

Further, the frame discarding unit 4 discards the B picture after the frame to be displayed, and the display control unit 8 thins out the remaining non-displayed P pictures and supplies them to the display device. Every other frame of the original moving image frame sequence before the operation can be accurately displayed every other frame. Therefore, accurate display can be achieved without disturbing the interval between the original images.

For example, in the conventional moving picture decoding apparatus shown in FIG. 9, the encoded frame from the stream analyzing unit 50 is
All are supplied to the video decoding unit 52. The video decoding unit 52 decodes a moving image signal of 60 frames per second and supplies it to the progressive-interlace conversion unit 54. In the conversion unit 54, a moving image of 60 frames per second is alternately changed to an odd field,
An even field is read out and an image of 60 fields per second is displayed on the display device. FIG. 10 shows the decoding process.

In the moving picture decoding apparatus shown in FIG. 9, as is clear from FIG. 10, all the encoded frames (from the upper stage to the middle stage) are decoded to obtain decoded images. Therefore, the video decoding unit 52 is different from the video decoding unit 6 of the present embodiment in that:
High-speed processing is required. For example, in an adder that adds an inter-frame difference value and a motion-compensated image signal, an operation is particularly necessary for all pixels. Therefore, in processing at 60 frames per second, a plurality of adders must be used, for example, in parallel. . In this embodiment, the number of adders or the degree of parallelism can be reduced to 2/3, for example.

That is, the amount of hardware can be reduced. In addition, the other parts may have a processing capacity of about 2/3. For example, the writing and reading speed of the frame memory can be reduced to simplify the control. Similarly, the writing speed of data to the memory in the display control unit 8 of this embodiment is lower than the writing speed of the progressive-interlace converter 54 shown in FIG. It can be.

FIG. 6 shows another embodiment of the moving picture decoding apparatus according to the present invention. The difference between the moving picture decoding apparatus of the present embodiment and the above embodiment is that the frame discarding unit 42 discards all B pictures and the video decoding unit 44 decodes only I and P pictures. And that the display control unit 46 reads three fields from one frame.

More specifically, the stream analysis unit 40 extracts the code of each coded frame from the coded stream 400 and supplies it to the frame discarding unit 42 in the same manner as described above. At this time, in the above embodiment, the processing according to the order of the I, P, and B pictures was instructed. However, in this embodiment, only an instruction of that type may be used, and an instruction to the display control unit 46 is required. And not.

The frame discarding unit 42 includes a stream analyzing unit 40
Is a B picture discarding circuit that discards the code when the frame is a B picture in accordance with the instruction from, and supplies all the remaining I and P pictures to the video decoding unit 44.
For example, a switching circuit.

The video decoding unit 44 decodes an I picture in a frame and decodes a P picture by forward prediction.
This is a picture decoding circuit. Therefore, the frame memory only needs to have an area for the previous frame, and does not need a memory area for storing the subsequent frame.

The display control unit 46 includes a frame memory for sequentially storing the image signals of the frames decoded by the video decoding unit 44. For the odd-numbered decoded frames, the odd-numbered field, the even-numbered field, and the odd-numbered field are read and displayed. In the even-numbered decoded frame, the signal control circuit reads an even field first, then reads an odd field, and further reads an even field, and displays three fields for each frame.

That is, the process will be described with reference to FIG. 7. First, as shown in the upper part of the figure, the stream analysis unit 40 sends the encoded streams I1, B2, B3,.
Is supplied, the stream analysis unit 40 detects each encoded frame in that order,
Supply 42.

Next, upon receiving the I1 picture, the frame discarding unit 42 connects this to the video decoding unit 44 and outputs it.
Upon receiving the B2 picture, it switches to the discard side and discards it.
Subsequently, when a B3 picture is received, it is discarded while being connected to the discarding side, and when a P4 picture is received, it is again connected to the video decoding unit 44 and output. Similarly, when the B5 picture and the B6 picture are discarded and the P7 picture is received, the picture is switched to the video decoding unit 44 and output. Similarly, B
When a picture is received, it is discarded. When a P picture is received, the picture is switched to the video decoding unit 44 and sequentially output. Thereby, the encoded frames of I1, P4, P7,... Are sequentially supplied to the video decoding unit 44 as shown in the middle part of the figure.

Next, upon receiving the I1 picture, the video decoding section 44 performs Huffman decoding on the code, performs inverse quantization, and performs inverse orthogonal transform in the same manner as in the above-described embodiment to reproduce the original image signal. The decoded frame of the reproduced I1 picture is
The data is stored in the frame memory and supplied to the display control unit 46.

Next, when the P4 picture is received, the sign of the difference value is decoded by Huffman decoding, inverse quantization, and inverse orthogonal transform like the I1 picture. On the other hand, the code of the motion vector is decoded, the previous frame obtained by decoding the I1 picture is corrected by the motion vector, the image signal is added to the difference value, and the original image signal is reproduced. The decoded frame of the reproduced P4 picture is stored in the frame memory and supplied to the display control unit 46.

Similarly, the P7 picture is decoded and output by forward prediction using the decoded frame of the P4 picture as the previous frame, and the P10 picture is decoded and output using the decoded frame of the P7 picture as the previous frame. Decoded in the same way as the P16 picture,
Output to 46.

Next, when receiving the decoded frame of the I1 picture, the display control section 46 temporarily stores the decoded frame, reads out the odd field, and displays it on the display device.
Next, the even field is read and displayed on the display device, and the odd field is read again and displayed.

During this time, the decoded frame of the P4 picture is accumulated, and when the display of the third field of the decoded frame of the I1 picture is completed, the even field of the accumulated decoded frame of the P4 picture is read and displayed on the display device. As a result, in the display device, accurate interlaced display is performed without overlapping with the odd field of the previous field. Next, the odd fields of the decoded frame of the P4 picture are read and displayed, and the even fields are again read and displayed.

Next, when displaying the decoded frame of the P7 picture, the odd field of the P7 picture is read out and displayed following the third field of the P4 picture. Next, as in the case of the I1 picture, the even field is displayed, and the odd field is displayed again.

Similarly, when the odd field is displayed as the third field in the previous frame, in the subsequent frame, the even field is read out, then the odd field, and then the even field is read out. Is displayed. If the even field is displayed as the third field in the previous frame, in the subsequent frame, the odd field, the even field, and the odd field are read out and read out.
It is displayed for each field.

As a result, the video signal of 60 fields per second is decoded from the coded stream of the video signal of 60 frames per second, and is effectively displayed on a display device such as a television receiver of the current interlaced display. .

As described above, according to the moving picture decoding apparatus of the present embodiment, after the codes of all B pictures are discarded by the frame discarding unit 42, only the remaining I and P pictures are sent to the video decoding unit 44. Therefore, the processing performance of the video decoding unit 44 can be reduced to almost one third as compared with the case where all the encoded frames are decoded. As a result, the number of adders and the like or the degree of parallelism can be further reduced as compared with the above embodiment, and the amount of hardware can be reduced. Further, the control of the frame memory can be simplified, and the video decoding unit 44 further controls the I, P
Since only pictures are decoded, an area for storing subsequent frames for bidirectional prediction is not required, and an inexpensive storage circuit can be applied.

In the above embodiments, the case where each part is configured by hardware has been described as an example. However, in the present invention, the case where some or all of the parts are replaced with software and applied is applied. Of course including.

[0067]

As described above, according to the moving picture decoding apparatus of the present invention, when decoding a coded stream obtained by coding a moving picture signal of progressive scanning at a predetermined frame frequency or higher, a frame is decoded before decoding. After the B picture is discarded by the discarding means, only the remaining encoded frames are decoded by the decoding means and displayed on a display device of a predetermined interlaced scanning based on the decoded frame. Performance or processing speed may be lower than that of decoding all encoded frames. Therefore, an inexpensive decoding means can be applied, and an effect that an inexpensive device can be provided is achieved.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing an embodiment of a moving picture decoding apparatus according to the present invention.

FIG. 2 is a functional block diagram illustrating an example of an encoding device that forms an encoded stream applied to the embodiment in FIG. 1;

FIG. 3 is a timing chart showing an encoding order in the encoding device of FIG. 2;

FIG. 4 is a functional block diagram illustrating an example of a video decoding unit in the video decoding device of FIG. 1;

FIG. 5 is a timing chart showing the order of decoding processing and display in the video decoding apparatus of FIG. 1;

FIG. 6 is a functional block diagram showing another embodiment of the moving picture decoding apparatus according to the present invention.

7 is a timing chart showing the order of decoding processing and display in the video decoding device of FIG. 7;

FIG. 8 is a diagram for explaining a video format defined by the ATSC.

FIG. 9 is a functional block diagram illustrating an example of a conventional video decoding device.

10 is a timing chart showing the order of decoding processing and display in the video decoding device of FIG. 9;

[Explanation of symbols]

 2, 40 stream analysis unit 4, 42 frame discarding unit 6, 44 video decoding unit 8, 46 display control unit

 ──────────────────────────────────────────────────続 き Continued on front page F term (reference) 5C053 FA20 GA11 GA19 GB06 GB29 GB37 JA22 KA04 KA21 KA24 LA06 LA11 5C059 KK15 KK40 MA04 MA14 MA23 ME02 NN28 PP05 RB03 RC31 RC39 RE07 SS03 SS26 UA05 UA32 5C063 AA01 AB03 AC07 CA36

Claims (6)

[Claims] 1. A moving picture signal represented by sequential scanning at a predetermined frame frequency or higher receives a coded stream coded by a predetermined coding method and is decoded into a moving picture signal of a lower frame frequency. A moving picture decoding apparatus for displaying on a display device of interlaced scanning, the coding apparatus decodes a code of each coded frame from a coded stream of a moving image signal coded by a predetermined coding method. Stream analyzing means for detecting, discarding means for discarding the code of an encoded frame for each predetermined frame among the encoded frames from the stream analyzing means, excluding the code of the encoded frame discarded by the discarding means Decoding means for receiving a code of an encoded frame from the stream analyzing means and decoding a moving image signal of a forward dimension frame; and a moving image signal decoded by the decoding means. Video decoding apparatus characterized by comprising a display control means for displaying on the display device and converts each sequence fields each frame based on. 2. The moving picture decoding apparatus according to claim 1, wherein the moving picture signal is obtained by encoding a progressively scanned moving image signal of 60 frames per second by an encoding method including inter-frame encoding. Receiving a video signal of interlaced scanning of 60 fields per second from the stream and displaying the decoded video signal on the display device. 3. The moving picture decoding apparatus according to claim 2, wherein said discarding means comprises a plurality of B-pictures which have been inter-coded by bidirectional prediction among respective coded frames from said stream analyzing means. A discarding means for discarding some of the above, and sequentially discarding a code of a B picture corresponding to a frame next to a frame to be displayed on the display means. 4. The moving picture decoding apparatus according to claim 3, wherein the display control means includes a forward direction corresponding to a frame next to the discarded B picture in the moving picture signal decoded by the decoding means. Inter-coded P by prediction
A moving picture decoding apparatus characterized in that a moving picture signal of a remaining decoded frame, excluding a moving picture signal obtained by decoding a picture, is read out for each field and displayed on the display means. 5. The moving picture decoding apparatus according to claim 2, wherein the discarding unit discards all the codes of the inter-frame coded B pictures of the coded frames from the stream analyzing unit by bidirectional prediction. The decoding means is an I, P picture decoding means for sequentially decoding only I-pictures coded intra-frames and P-pictures coded inter-frames by forward prediction. A video decoding device characterized by the above-mentioned. 6. The moving picture decoding apparatus according to claim 5, wherein the display control unit reads out the decoded frames of the I picture and the P picture decoded by the decoding unit as three or more fields, respectively. A moving image decoding device for displaying on a display device.