KR100202306B1 - Moving information variable coder for mpeg-2 image compression apparatus - Google Patents

Abstract

The present invention relates to a structure of a variable length encoding apparatus of motion information used in a video encoding apparatus according to the MPEG standard.

The configuration of the present invention is an internal controller for generating a control signal in accordance with the state transition; A serial-to-parallel conversion unit for converting serial motion data from the motion estimation / compensation unit in parallel; A first register for receiving the macroblock data in parallel from the serial-to-parallel converter; A second register having the same configuration as the first register and receiving data from the first register; A third register having the same configuration as the first register and receiving data from the second register; A difference calculator which calculates a difference between motion information of the second and third registers and variably encodes the difference with reference to a lookup table; An additional information controller which receives an output of the difference calculator and adds additional information according to an external input control signal and motion information; A CBP lookup table for variable length encoding the input CBP information; And an output unit for selectively outputting the outputs of the additional information controller and the CBP lookup table to an output unit.

Description

Motion information variable length encoder for MPEG-2 video compressor

The present invention relates to a motion information variable length coding apparatus employed in a variable length coding (VLC) apparatus used in a video encoding apparatus that conforms to the MPEG-2 standard among video signal compression algorithms.

Recently, with the rapid development of semiconductor technology, each core device in the signal processing field is being implemented as a single application specific integrated circuit (ASIC) chip at the existing large system or board level. Accordingly, it is necessary to design high-speed, high-capacity hardware suitable for high density semiconductor (VLSI) implementation. The structure of the variable length encoder proposed by the present invention is not a system or board-level low-volume hardware but a special structure suitable for high-speed processing, and can be effectively employed as part of a high-speed video encoder.

SUMMARY OF THE INVENTION An object of the present invention is to provide a hardware structure for implementing a VLSI of a variable length coding apparatus that can be applied to a digital TV, a high definition television (HDTV), and can reduce chip area and enable high speed operation.

1 is an input / output signal interface diagram of a motion information variable length encoder.

2 is an input signal definition diagram of a motion information encoder.

3 is a detailed block diagram of a motion information encoder.

4 is a motion prediction type for each image structure.

5 is an update of the movement vector.

6 is a data bit determination condition next to the mv and pmv registers.

7 is a condition for determining a difference calculator according to a picture structure.

8 is a motion vector field selection decision condition.

9 to 12 show variable length encoding of a motion vector.

13 shows variable length coding of CBP coefficients.

14 is a timing diagram of a motion information encoder.

15 is a state diagram of a motion information encoding unit.

16 is a state table of the motion encoder.

* Explanation of symbols for main parts of the drawings

1: Serial-to-parallel conversion unit 2: First register

3: 2nd register 4: 3rd register

5: difference calculation part 6: look-up table

7,8: additional information control unit 9: motion information detection unit

10: CBP lookup table 11: output section

12: internal controller 13: loading control unit

In order to achieve the above object, the present invention provides a motion information variable length encoding apparatus for MPEG-2 video compression; The encoding device is:

An internal controller 12 which generates a control signal in response to a state transition;

A serial-to-parallel converter 1 for converting serial motion data from the motion estimation / compensation part in parallel;

A first register (2) for receiving macroblock data in parallel from the serial-to-parallel converter;

A second register having the same configuration as the first register and receiving data from the first register;

A third register having the same configuration as the first register and receiving data from the second register;

A difference calculator (5) for calculating the difference between the motion information of the second register and the third register and variably encoding the difference with reference to a lookup table (LUT) 6;

An additional information controller (7, 8) for inputting the output of the difference calculator and adding additional information according to an external input control signal and motion information;

A CBP lookup table 1 for variable length encoding the input CBP information; And,

And an output unit 11 for selectively outputting the additional information control unit and the output of the CBP lookup table to the output unit.

In addition, the apparatus may further include a motion information detector 9 which generates and outputs a motion vector presence signal from the output of the second register.

In addition, it may further include a loading control unit 13 for generating a loading timing to the first, second, third registers (2, 3, 4) by the control of the internal controller (12).

Additionally, the internal controller 12 may be configured as a state transition controller for outputting a control signal in each state while the state transitions according to an external input.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 illustrates an interface of a motion information variable length encoder according to the present invention, and FIG. 2 illustrates an output signal sent to an output unit and a signal received from an external module (system controller, motion estimation / compensation module) in the encoder of FIG.

3 is a detailed diagram illustrating an embodiment of a motion information variable length encoder according to the present invention in blocks. The variable-length coded information according to the present invention checks whether a motion vector and CBP data (coded block pattern: coefficients other than '0' among 64 block unit information are present to determine whether the corresponding block is coded or non-coded). Data represented by binary information of '1' and '0'. Referring to FIG. 3, the motion information variable length encoder uses the data transmitted from the system controller, the variable length controller (controller of the entire variable length encoder), and the motion estimation / compensator to determine the difference between the current macroblock and the previous macroblock. The variable length coding is performed on the CBP value, and the data, the data length, and the enable signal are output to the output unit.

Since mvtype and mvdata inputted into registers receive values before two macroblocks, the values of mvtype and mvdata before two macroblocks should be stored rather than the macroblock to be coded. While the mvdata_en value is valid, mvtype and mvdata, which come in serial by 1 bit, are converted into parallel 29bit data by shifting sck2. If you receive all four, it will take 29 sck2.

Among the motion vector values, the horizontal component always uses all 7 bits as mvdata, and the vertical component uses all 7 bits according to the conditions of the motion vector type (mvtype) and the picstr signal representing the picture structure, or 6 bits of mvdata and 1 Determines whether to use the bit's mv_field_sel value. Here, the signal mvforward, that is, the motion vector is output, is output to the guitar information encoder using the motion vector values before the macroblock. If coding_cond3 and coding_end1 are 1, the values of the mv register and the pmv register are sequentially subtracted, and then code_len indicating valid bits among 4 or 2 pieces of data and 32-bit mode through the lookup table (LUT) and valid intervals of data. It outputs a data_en signal indicating a CBP value according to coding_cond4 and then outputs a coding_end2 signal to the DCT encoder.

Next, a motion vector determination and update algorithm will be described. The classification of the motion vector according to the condition of the picstr signal and the motion vector type (mvtype) indicating the picture structure described above is as follows.

1) Classification by mv_type

-Frame video motion estimation mode (11)

'0': frame based prediction

'1': Field root prediction

In field video motion estimation mode (01, 10)

'0': 16 X 16 MC prediction

'1': 16 X 8 MC prediction

2) mvdata

It is defined as follows according to the motion estimation mode and the motion prediction mode (mvtype).

-Horizontal component values of the motion estimation vector and vertical component values when the motion estimation format is a frame in FIG. The motion estimation vector component value represents a pixel distance on a frame and may have a value of 0.5 unit of -32.0 to 31.5. Component values are expressed in two's complement of half pixel units.

-Vertical component values when the motion estimation format is a field in FIG.

The motion estimation vector component value represents this pixel distance on the field and has a 0.5 unit value of -16.0 to 15.5. The component value is represented by two's complement of half-pixel units and constitutes upper six bits, and the lower one bit represents an mv_field_sel value which is an estimated field. The definition of the lower 1 bit is as follows.

'0': parent field

'1': Subfield

3) Update the motion vector and reset the pmv register

The condition for updating the motion vector data of the mv register to the pmv register after the macroblock is coded is shown in FIG.

The pmv register is also reset when mvforward = 0 in a non-intra macroblock when the macro block is skipped in the P picture when the slice clock is generated.

-Moving data bit decision condition

FIG. 6 shows the conditions for determining whether the data passing through the mv register and the pmv register uses 6 bits or all 7 bits according to the horizontal component and the vertical component. FIG. 7 shows the conditions of picstr and mv_type. The difference calculation decision condition according to the values is shown. FIG. 8 shows the selection of the mv_field_sel value, which is the motion vector field selection value.

-Coding of the difference of motion vector and CBP value

A motion code (motion_code), a sign bit, and a motion_residual shown in FIGS. 9 to 12 are output according to the difference between the pmv value and the mv value selected by the difference calculator, and the input CBP value Is printed after referring to the table in FIG.

14 is a timing diagram of a motion information variable length encoder. When vlck occurs, register A, register B, mv register and pmv register are loaded. When coding_cond3 and coding_end1 are 1 at the same time, the horizontal component remains as it is when the difference is calculated from the mvdata value output from the mv register and the pmv register. All 7 bits are used to calculate the difference, and the vertical component determines whether to use 7 bits or 6 bits according to the values of pic_str and mvtype.

The data (difference value between mv and pmv) is added to one bit of the motion vector selection signal (mv_field_sel) according to the pic_str value and mvtype value with reference to the look up table (LUT), or output as it is. After coding four or four mvdata, the CBP value received from the variable length coding controller is coded with reference to coding_cond4.

After the CBP coding is completed, the coding_end2 signal is output to the DCT coefficient encoding unit, and when vlck occurs, the n-1 th mvdata and mvtype in the serial / parallel change unit are loaded into register A before. At the same time, when vlck occurs, the pmv register value is also updated, and the mvdata of the macro block is input to the mv register. FIG. 14 shows the timing when all four motion vectors are coded in the motion information variable length coding apparatus. 15 shows a state transition diagram of the internal controller 12 for such timing. The controller of the present invention is implemented as a dedicated hardware controller having nine states. In FIG. 16, the output signals according to the input conditions of the transition of each state shown in FIG. 15 and their operations are described.

As described in detail above, the present invention implements a variable length encoder of motion information employed in an MPEG-2 standard video encoding apparatus using a VLSI structure that can be employed in a high-speed ASIC using dedicated hardware. Including a dedicated control device having nine states enables high-speed operation and reduces chip size.

In addition, a preferred embodiment of the present invention is disclosed for the purpose of illustration, those skilled in the art will be able to make various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the following claims You will have to look.

Claims (4)

A motion information variable length encoding apparatus for MPEG-2 video compression; The encoder comprises: an internal controller for generating a control signal in response to a state transition; A serial-to-parallel conversion unit for converting serial motion data from the motion estimation / compensation unit in parallel; A first register for receiving the macroblock data in parallel from the serial / parallel change unit; A second register having the same configuration as the first register and receiving data from the first register; A third register having the same configuration as the first register and receiving data from the second register; A difference calculator which calculates a difference between motion information of the second and third registers and variably encodes the difference with reference to a lookup table; An additional information controller configured to input an output of the difference calculator and add additional information according to an external input control signal and motion information; A CBP lookup table for variable length encoding the input CBP information; And an output unit for selectively outputting the output of the additional information control unit and the CBP lookup table to an output unit. The apparatus of claim 1, further comprising a motion information detector for generating and outputting a motion vector presence signal from the output of the second register. The variable length coding for MPEG-2 image compression according to claim 1, further comprising a loading control unit for generating a loading timing in the first, second and third registers under the control of the internal controller. Device. The variable length coding for MPEG-2 image compression according to claim 1, wherein the internal controller is configured as a state transition controller which outputs a control signal in each state while the state is changed according to an external input. Device.