KR100243464B1 - Dpcm of mpeg-2 - Google Patents

Abstract

According to an embodiment of the present invention, a latch unit 30 receives input image data Org_data1 and Org_data2 in frame units or field units from the frame memory or the motion estimator ME by 8 bits; Subtraction means 32 for subtracting the original image data Org_data1 and Org_data2 from the latch unit 30 and the motion compensation data MCed_data1 and MCed_data2 from the motion compensation means MC; First and second data stored by the latch unit 30 and the subtraction means 32 by the write address signal Wads from the RAM controller 40 and output by the read address signal Radrs. RAM 34 and 36; A third multiplexer 38 for selectively outputting image data of the first and second RAMs 34 and 36 by a coding identification signal inter_intra input from a system controller; Alignment means (42) for aligning image data from the third multiplexer (38) by a latch enable signal (latch_en) from the ram controller (40); A fourth multiplexer (44) for selectively outputting the image data from the alignment means (42) by the selection signal (SEL) from the ram controller (42); RAM controller 40 for aligning the image data stored in the first and second RAM (34, 36) to the alignment means 42 through the third multiplexer 38 and then output by the fourth multiplexer (44) It is characterized by consisting of).

Description

Differential pulse coding modulator in MPEG-2 encoder

The present invention relates to a differential pulse code modulator (DPCM) in an MPEG-2 encoder. In particular, data input to a differential pulse code modulator in an MPEG-2 encoder is stored by a write address signal from a RAM controller (RAMCON). The present invention relates to a differential pulse code modulator in an MPEG-2 coder, which is stored in a RAM) and aligned to an alignment means by a read address signal, so that a discrete cosine transform can be easily performed.

1 is a block diagram illustrating a general video encoder, wherein the video encoder includes a frame memory unit 100, a differential pulse code modulator 120, a discrete cosine transformer 130 (DCT), a quantizer 140 (Q), and a variable length. It consists of an encoder 150 (VLC), an inverse quantizer 160 (IQ), an inverse discrete cosine transformer 170 (IDCT), an adder 180, and a motion compensator 190 (MC).

Meanwhile, as is well known, the video encoder is inputted to the differential pulse code modulator 120 from the current video signal inputted through the frame memory unit 100 and the previous video signal inputted from the motion compensator 190 (MC). Then, the image data from the differential pulse code modulator 120 is input to the discrete cosine converter 130 to be discrete cosine transform. Next, the discrete cosine-converted image data by the discrete cosine converter 130 is input to the quantizer 140 to perform quantization. Will be performed.

As described above, in the MPEG-2 standard video encoder, a differential pulse code modulator is required which is output as it is for an I-picture and outputs a difference video signal between images in the case of a P-picture and a B-picture. It became.

In addition, the image signal input to the differential pulse code modulator is divided into an I-picture, a P-picture, and a B-picture. Such a video signal, for example, a previous screen, a difference screen, and a current screen, are output as it is. However, when the discrete cosine converter is designed, the discrete cosine transform is efficiently performed, and thus the output value from the differential pulse code modulator needs to be adjusted to reduce the conversion time.

When the original image data input from the frame memory is frame data or field data and the motion compensation data input from the motion compensator is data predicted in the form of a field, for example, the picture structure Pic_str is a frame picture, and the frame motion type frm_motion_type In the case of the field-based form, the input form is different and an appropriate address conversion is required.

Accordingly, the present invention is to solve the above problems, even if the original image data input from the frame memory in the MPEG-2 encoder is frame data or field data and motion compensation data input from the motion compensator is predicted in the form of a field Differential pulses in the MPEG-2 coder, which are stored in the storage means RAM by the write address signal from the controller RAMCON and then aligned and output to the alignment means by the read address signal, so that discrete cosine conversion can be easily performed. Its purpose is to provide a code modulator.

According to an aspect of the present invention, there is provided a latch unit for inputting 8-bit original image data in frame units or field units from a frame memory or a motion estimator; Subtraction means for subtracting the original image data from the latch portion and the motion compensation data from the motion compensating means: storing data from the latching portion and the subtracting means by a write address signal from a ram controller, First and second RAM output by the; A third multiplexer for selectively outputting image data of the first and second RAMs by a coding identification signal input from a system controller; Alignment means for aligning image data from the third multiplexer according to a latch enable signal from the ram controller; A fourth multiplexer for selectively outputting image data from the alignment means in response to a selection signal from the ram controller; And a RAM controller for aligning the image data stored in the first and second RAMs with the alignment means through the third multiplexer and outputting the image data by the fourth multiplexer.

According to the present invention configured as described above, even when the original image data input from the frame memory in the MPEG-2 encoder is frame data or field data and motion compensation data input from the motion compensator is predicted in the form of a field, writing from the RAM controller is performed. After being stored in the RAM by the address signal and aligned to the alignment means by the read address signal, the discrete cosine conversion can be easily performed.

1 is a block diagram showing a general video encoder.

2 is a block diagram showing an embodiment of a differential pulse code modulator in an MPEG-2 encoder according to the present invention.

3 is a block diagram showing a RAM controller RAMCON shown in FIG.

4 is a timing diagram showing the operation timing of the ram controller shown in FIG.

FIG. 5 is a diagram showing a data sorting procedure of the alignment unit shown in FIG.

<Explanation of symbols for main parts of drawing>

10 to 13: first to fourth FIFO 20: write address generator

22: read address generator 23: write address converter

24: read address converter 25, 26, 38, 44: multiplexer

27: input data determination unit 30: latch unit

32: subtractor 34,36: RNM

40: RAMCON 42: alignment unit

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.

First, when the discrete cosine transform is performed by the discrete cosine transform (DCT), the conversion is performed in 8 × 8 block units, the processing of 8 × 8 block units is the same in the differential pulse code modulator (DPCM) Will be applied.

And the following Table 1 shows the addresses for the 8 × 8 image block data input to the differential pulse code modulator.

Here, when the 8x8 image block data is input from a frame memory or a motion estimator (ME) to a differential pulse code modulator, the data is placed in a latch so that the data can be easily converted by a discrete cosine converter. After sorting it will be printed.

On the other hand, the data of the currently designed encoder is processed by 2 pixels, when the data of these 2 pixels is input to the differential pulse code modulator, the data of the following address is input in the following order.

(0, 1), (2, 3), (4, 5), (6, 7), (8, 9), (a, b), (c, d),...

Here, the number represents an address of each pixel of 8 bits.

After the data of the address is input to the differential pulse code modulator, the differential pulse code modulator outputs the data of the address in the following order in order to facilitate calculation by a discrete cosine transformer.

(0, 4), (1, 5), (2, 6), (3, 7), (8, c), (9, d), (a, e),...

Here, the number represents an address of each pixel of 8 bits.

2 is a block diagram showing an embodiment of a differential pulse code modulator in an MPEG-2 encoder according to the present invention, wherein the code modulator includes a latch unit 30, a subtractor 32, first and second ones. RAM 34 and 36, first and second multiplexers 38 and 44, a RAM controller 40 (RAMCON), and an alignment unit 42.

First, motion compensation data inputted from the frame memory or the motion estimator ME to the latch unit 30 by frame 8 by the original image data Org_data1 and Org_data2 in units of 8 bits, and also from the motion compensator MC. The MCed_data1 and MCed_data2 are input to the subtraction unit 32 by 8 bits.

The latch unit 30 inputs the original image data Org_data1 and Org_data2 into the first RAM 34 and inputs the subtractor 32 to the latch unit 32. The difference data between the original image data Org_data1 and Org_data2 from 30 and the motion compensation data MCed_data1 and MCed_data2 from the motion compensator MC are input to the second RAM 36. Here, the first RAM 34 stores original image data (Org_data1, Org_data2), that is, I-picture from the latch unit 30, and the second RAM 36 stores the subtractor 32. Difference data from the P-picture and the B-picture.

Thereafter, I-pictures, P-pictures, and B-pictures stored in the first and second RAMs 34 and 36 are selectively output by the first multiplexer 38, and the first pultiplexer 38 is output. Is an intra coding method by a coding identification signal inter _intra input from a system controller (not shown), and outputs data of the first RAM 34 in which original image data Org_data1 and Org_data2, which are I-pictures, are stored. In the case of the inter coding method, the data of the second RAM 36 in which the difference image data, which is a P-picture or a B-picture, is output. That is, in the case of the intra coding scheme, for example, when the coding identification signal inter_intra output from the system controller is "1", the first multiplexer 38 outputs the data of the first RAM 34 and intercodes it. In the case of the scheme, for example, when the coding identification signal inter_intra output from the system controller is "0", the first multiplexer 38 outputs data of the second RAM 36.

On the other hand, the RAM controller 40 (RAMCON) outputs the write address signal Waders, so that the image data of the latch unit 30 and the subtractor 32 is transferred to the addresses of the first and second RAMs 34 and 36. Will be saved. The image data stored in the first and second RAMs 34 and 36 may be aligned through the first multiplexer 38 in units of four clocks by the latch enable signal latch_en of the RAM controller 40. It is inputted to 42 to be aligned.

Thereafter, the image data input to the alignment unit 42 is processed by 2 pixels, and the input data is in the order of (0, 1), (2, 3), (4, 5), (6, 7). After inputting, the output is sorted by (0, 4), (1, 5), (2, 6), (3, 7). Here, the number represents the address of each pixel of 8 bits.

FIG. 3 is a block diagram illustrating the RAM controller illustrated in FIG. 2, wherein the RAM controller 40 includes a write address generator 20, a read address generator 22, a write address converter 23, and a read controller. An address conversion section 24, third and fourth multiplexers 25 and 26, and an input data determination section 27 are provided. First, in order to facilitate understanding, each component block and signals inputted to and outputted from the component block will be described.

In FIG. 3, "CLK" is a system clock and "RST" is a reset signal operated at an active low. The "macroblock start signal (MBS)" indicates the start of input of the image data by output when the image data is input from the frame memory to the latch unit 30 and the subtraction unit 32. After the start signal MBS is generated, storage to the first and second RAMs 34 and 36 starts from the ninth clock. The "write address signal Wadrs" is an address signal in which data of the latch unit 30 and the subtraction unit 32 is stored in the first and second RAMs 34 and 36, and the "write enable signal WREN". ) "Is a signal that enables data storage of the latch unit 30 and the subtraction unit 32 at the 9th clock after the macroblock start signal MBS. &Quot; Lead address signal Radrs " is an address signal for reading data stored in the first and second RAMs 34 and 36, and " panel block start signal PBS " The signal starts to output the data stored in the first and second RAMs 34 and 36 from the 140th clock after the MBS. The "latch enable signal" latch_en "is a signal for selecting and outputting data stored in the alignment unit 42, and the" SEL "signal is a data input from the alignment unit 42 to the second multiplexer 44 is optional. It is a selection signal that is allowed to go out.

Meanwhile, the characteristics of motion estimation in MPEG-2 are classified based on a picture structure and a picture coding type, so that field prediction and frame prediction can be supported. As a unit of encoding different from the existing frame, a frame picture is encoded in a frame unit, and a field picture is encoded in a field unit. In addition, pictures are classified as shown in Table 2 according to the picture structure of the picture coding extension in the MPEG-2 bit stream structure (MPEG IS: Table 6-13).

As shown in Table 2, a picture is divided into a frame structure picture and a field structure picture (Top fied and Bottom field) by the picture structure. The above-mentioned field picture is only a field structure, but a frame picture field structure and a frame structure are possible. Do. Therefore, only field prediction is possible in field pictures, but frame prediction and field prediction are possible in frame pictures.

On the other hand, when the picture structure signal Pic_str is a frame picture signal, for example, "11", and the frame motion type signal frm_motion_type is a field base signal, for example, "01", the input form is different so that the input data determination unit 27 Outputs the write address selection signal Wads_sel.

Therefore, when the write address selection signal Wadrs_sel is outputted, the first multiplexer 25 outputs the write address signal Wads from the write address converting unit 23, for example, the frame picture field address converting unit. When the write address selection signal is not output, the write address signal Wads from the write address generator 20 is output.

The write address converting unit 23 converts the frame data address into the field data address using a programmed logic array (PLA) shown in Table 3 below.

In addition, the field frame selection signal field_frame is a signal indicating the type of the discrete cosine transform (Dct_ type), for example, the field discrete cosine transform (field DCT) or the frame discrete cosine transform (frame DCT), and the input data is a frame picture. The read address Radrs signal from the read address converting section 24 is outputted, and in the case of a field picture, the read address Radrs signal from the read address generating section 22 is outputted.

The read address converter 24 reads out and outputs the field data address by the programmable logic array PLA shown in Table 4 below.

Meanwhile, when the macroblock start signal MBS is input, data is stored in the first and RAMs 34 and 36 after a delay of 9 clocks, which causes the input data to be delayed while passing through the latch unit 30. It is for.

Subsequently, when the data of the first and the RAMs 34 and 36 are read, after the macroblock start signal MBS is output, the 140-th clock panel block start signal PBS is output. Two pixels are output for one clock and two addresses are output at a time.

FIG. 4 is a timing diagram illustrating an operation timing of the RAM controller shown in FIG. 3, in which a write address signal Wads is output at ninth clock after the start of the macroblock start signal MBS, and the macroblock start signal MBS is output. After that, the panel block start signal PBS is output at the 140th clock time, and the read address signal Radrs is output.

FIG. 5 shows a data sorting sequence of the alignment unit shown in FIG. 2, in which the first and second multiplexers 38 and 44 and the alignment unit 42 are shown. In addition, the alignment unit 42 may include first to fourth FIFOs 10 to 13. First, data stored in the first and second RAMs through the first multiplexer 38 by the read address signal Radrs of the RAM controller 40 is first FIF0 10 and the third FIFO 12 in units of 2 pixels. ), The second FIFO 11 and the fourth FIFO 13 are stored in this order.

Then, the first data, the second data, the third and fourth FIFOs 12 and 13 of the first and second FIFOs 10 and 11 by the latch enable signal latch_en of the RAM controller 40. The first data and the second data will be output in order.

On the other hand, the reference numerals written in the components of the claims of the present application to facilitate the understanding of the present invention, and are not written in the intention to limit the technical scope of the present invention to the embodiments shown in the drawings.

As described above, according to the present invention, even when the original image data input from the frame memory in the MPEG-2 encoder is frame data or field data and motion compensation data input from the motion compensator is predicted in the form of a field, After being stored in the RAM by the write address signal and aligned with the read means by the read address signal, the discrete cosine conversion can be easily performed.

Claims (3)

An image encoder configured to receive an original image signal and a motion compensated image signal and perform discrete cosine conversion of a differential image signal or an original image signal, comprising: a latch unit 30 for receiving original image data in a frame unit or a field unit; A subtraction unit 32 which subtracts motion compensated data from the original image data input from the latch unit 30; The first RAM 34 and the second RAM 36 are configured to store the original video signal of the latch unit 30 in the first RAM by a write address signal Wads and from the subtracting means 32. Data storage means for storing difference data in the second RAM and outputting data stored by read address signals Radrs, respectively; A first multiplexer (38) for selecting an output of the first RAM during intracoding and an output of the second RAM during encoding according to a coding identification signal inter_intra; An alignment unit 42 for aligning image data from the first multiplexer 38 by a latch enable signal latch_en; A second multiplexer 44 for selectively outputting image data from the alignment unit by a selection signal SEL; And the write address signal and reads such that the image data stored in the first and second RAMs 34 and 36 are aligned in the alignment unit through the first multiplexer 38 and then output through the first multiplexer 44. And a RAM controller (40) for providing an address signal, a latch enable signal, and a selection signal. The write address generating means of claim 1, wherein the RAM controller 40 outputs the write address signal Wads and the write enable signal WREN at the ninth clock after the macroblock start signal MBS is output. 20); Write address converting means (23) for converting the frame picture write address signal from said write address generating means (20) into a field picture write address signal; Read address generating means (22) for outputting a panel block start signal (PBS) at the 140th clock after the macroblock start signal (MBS) is output and a read address signal (Radrs); Read address converting means (24) for converting the frame picture read address signal from said read address generating means (22) into a field read address signal; Input data determination means (27) for outputting a write address selection signal (Wadrs_sel) when the picture structure signal (Pic_str) is a frame picture signal and the frame motion type signal (frm_motion_type) is a field-based signal; The write address signal from the write address converting means 23 and the write address signal from the write address generator 20 are selectively outputted by the write address selection signal Wads_sel from the input data determining means 27. A third multiplexer 25; And a fourth multiplexer 26 for selectively outputting the read address signal from the read address converting means 24 and the read address signal from the read address generator 22 by a field frame selection signal field_frame. A differential pulse code modulator of an MPEG-2 encoder. 3. The differential pulse code of claim 2, wherein the write address converting means and the read address converting means are implemented by a programmable direct array (PLA) for converting an address according to a predetermined address conversion table. Modulator.