KR100235487B1 - Half-pel compensator of a motion compensator - Google Patents

Abstract

The present invention relates to a half-pixel compensator of a motion compensator, wherein, in motion compensation in n × n block units, horizontal axis half-pixel compensation is performed according to a horizontal half-pixel flag (H_half_flag) by receiving n + 1 pixel data in parallel on a horizontal line. A horizontal half-pixel compensator 632 for selectively outputting the calculated n pixel data or the originally input n pixel data; The vertical line switching unit 634 which receives the n pixel data provided from the horizontal half-pixel compensation unit 632 and demultiplexes the odd line n pixels or the even line n pixels according to the vertical line selection signal Line_sel. ; The vertical line half pixel compensation is calculated by using the even line n pixel data and the odd line n pixel data provided from the vertical line switching unit 634, and the vertical line switching unit 634 according to the vertical half pixel flag V_half_flag. A vertical half pixel compensator 636 for alternatively outputting the provided odd line n pixels or vertical axis half pixel compensated n pixel data; And a multiplexer 638 for selectively outputting the even line n pixels or the n pixel data output from the vertical half-pixel compensator 636 according to a vertical line selection signal Line_sel. The present invention relates to a horizontal half-pixel flag. According to the vertical half-pixel flag signal, half-pixel compensation can be efficiently processed in units of blocks, and the hardware can be easily implemented.

Description

Half-pel compensator of a motion compensator

The present invention provides a motion compensation apparatus for performing motion compensation (MC) using video data obtained by inverse discrete cosine transform (IDCT) and a motion vector (MV) in a video decoder. It relates to a half-pixel compensator for performing the horizontal and vertical axis half-pixel compensation of.

In general, the video compression method, in particular, the temporal redundancy in the MPEG-2 image compression technique is removed by motion compensated prediction, and motion estimation and compensation for the motion compensation prediction are based on the current input image. Compare each macroblock with the reference macroblock in the search area of the macroblock and the past image to find the difference between each pixel, and place the relative position of the corresponding macroblock having the smallest value as the motion vector (MV). Create The process of estimating a motion vector includes estimating a motion vector (MV) in units of integer-pels and estimating a motion vector in units of half-pels.

The encoder encodes and transmits the motion vector, and transmits the difference between each pixel between the corresponding macroblock and the reference macroblock through a discrete cosine transform (DCT), quantization (Q), and variable length coding (VLC) processes. . The decoder restores the original image by performing motion compensation with the transmitted motion vector.

1 is a block diagram of a typical MPEG-2 video decoder, in which an encoded bit stream transmitted from an image encoder (not shown) is output as a buffered bit stream through a buffer 10, and demultiplexed and The variable length decoding block 20 receives a buffered bit stream and performs demultiplexing and variable length decoding (VLD) to perform a quantization level, a discrete cosine transform mode, and motion compensation. Print information about. The inverse quantization block 30 dequantizes the variable length decoded image data according to the quantization level provided from the demultiplexing and the variable length decoding block 20, and the inverse discrete cosine transform block 40 performs the demultiplexing and the variable length. The inverse discrete cosine transform is performed on the dequantized image data according to the discrete cosine transform mode information (information on whether the field DCT mode or the frame DCT mode) is output from the decoding block 20. The motion compensation block 50 is inverse discrete from the inverse discrete cosine transform block 40 according to the motion compensation information (motion vector (MV) and various flags) provided from the demultiplexing and variable length decoding block 20. Motion compensation is performed by receiving the cosine-converted image data. The selection block 60 selects and outputs image data provided from the inverse discrete cosine transform block 40 in the case of an intra frame, and the motion compensation block 50 in the case of an inter frame. Selects and outputs the motion compensated image data provided from FIG.

Since the motion compensation block 50 in the video decoder has a large amount of computation and data, hardware complexity is a problem. Therefore, the motion compensation block 50 should be able to efficiently process motion compensation while reducing hardware complexity. In particular, there is a need for an apparatus that can process half-pixel compensation for half-pixel estimated blocks.

Accordingly, the present invention has been made to meet the necessity as described above, and provides a half-pixel compensator of a motion compensation device for processing half-pixel compensation in units of blocks according to a horizontal half-pixel flag signal and a vertical half-pixel flag signal. The purpose is.

In order to achieve the above object, the present invention provides a motion compensation apparatus for performing motion compensation in units of n × n blocks, wherein n + 1 pixel data (n blocks of pixels and one pixel adjacent to the last pixel of the block) are arranged in a horizontal line of the block. Horizontal half-pixel compensation unit for selectively outputting the compensated n pixel data or the n pixel data of the originally input block by calculating horizontal half pixel compensation according to the horizontal half pixel flag (H_half_flag), and the horizontal half half A vertical line switching unit which receives n pixel data provided from the pixel compensator and demultiplexes the odd line n pixels or even line n pixels in parallel according to a vertical line selection signal Line_sel, and is provided from the vertical line switching unit Calculate vertical half-pixel compensation using even line n pixel data and odd line n pixel data A vertical half pixel compensation unit for selectively outputting the odd line n pixels or vertical half pixel compensated n pixel data provided from the vertical line switching unit according to the vertical half pixel flag V_half_flag, and a vertical line selection signal And a multiplexer for selectively outputting n-pixel data output from the even line n pixels or the vertical axis half-pixel compensator in parallel according to (Line_sel).

1 is a conceptual block diagram of a typical MPEG-2 video decoder;

2 is an overall configuration diagram of a motion compensation device including a half-pixel compensator according to the present invention;

3 is a block diagram of a half-pixel compensator of a motion compensation device according to the present invention;

4 is a structural diagram of a macroblock for explaining the operation of the present invention;

FIG. 5 is a timing diagram for describing the vertical half-pixel compensation of FIG. 3.

* Explanation of symbols for main parts of the drawings

100: motion compensation controller 200: memory controller

300: memory 400: bus control unit

500: common bus 600: motion compensation unit

610: input buffer 630: half-pixel compensation unit

632: horizontal axis half-pixel compensation unit 634: vertical line switching unit

636: vertical axis half-pixel compensation unit 638: multiplexer

650: summer 670: output buffer

A1 to A8, C1 to C8: Adders B1 to B8, D1 to D8: Dividers

MUX1 to MUX24: 2-1 Multiplexer DEMUX1 to DEMUX8: 1-2 Demultiplexer

ODD1-ODD8: odd line buffer EVN1-EVN8: even line buffer

Hereinafter, with reference to the accompanying drawings will be described in detail with respect to the present invention.

First, an overall configuration diagram of a motion compensation device will be described with reference to FIG. 2 to help understanding of the present invention. The motion compensation device of FIG. 2 is proposed by the present inventors and described in Korean Patent Application Nos. 97-11852 to 97-11854, 97-11861, which reduce the complexity of the hardware and the desired connection with externally connected chips. It is designed to perform motion compensation on a block basis for one action.

2 is an overall configuration diagram of a motion compensation device including a motion half-pixel compensator according to the present invention, wherein the motion compensation device includes a motion compensation controller 100, a memory controller 200, a memory 300, and a bus controller 400. , A common bus 500, and a motion compensator 600. The motion compensator 600 includes an input buffer 610, a half-pixel compensator 630, an adder 650, and an output. It consists of a buffer 670.

The motion compensation controller 100 receives a motion vector (MV) and various flags from a variable length decoding block (see FIG. 1), adjusts timing to control a motion compensation process, and generates various control signals. To provide. The memory controller 200 receives a motion vector MV and a flag from a variable length decoding block (see FIG. 1) 20 and generates a read / write address signal and a memory control signal of the memory 300. The memory 300 reads or writes the compensated pixel data according to the address signal from the memory controller 200 and stores four frames (I-picture, B-picture, P-picture, etc.). It is.

The common bus 500 transmits input / output data between the memory 300 and the motion compensator 600 according to the bus control signal of the bus controller 400, and the size of the common bus 500 is 12 pixels (pel). The motion compensator 600 converts the pixel data input from the common bus 500 and the IDCT input from the inverse discrete cosine transform block (see FIG. 1) 40 according to the motion compensation control signal of the motion compensation controller 100. Motion compensation is performed using the received pixel data.

The reason why the input buffer 610 and the output buffer 670 are provided inside the motion compensator 600 is that the operating speeds of the memory 300 and the motion compensator 600 are different. Specifically, the memory 300 operates at 81 MHz, and the motion compensator 600 operates at 54 MHz.

The input buffer 610 receives the pixel data of 12 pixel units from the memory 300 through the common bus 500 according to the signal block_start indicating the start of the block and performs interfacing. Convert to and print it out. The input buffer 610 may be implemented to process data in block units.

The half pixel compensator 630 performs horizontal half pixel compensation or vertical half pixel compensation on the 9 pixel data from the input buffer 610 according to a control signal related to half pixel compensation, thereby not finally performing half pixel compensation ( Clarification and purification), horizontal half-pixel compensation only (half-pixel, half-pixel), vertical half-pixel compensation only (half-pixel, half-pixel), or both horizontal and vertical half-pixel compensation (half-pixel, half-pixel) ) Is printed in 2 pixel units.

The summation unit 650 and the two-pixel data from the half-pixel compensation unit 630 according to the signal (dct_type) indicating whether the field DCT or the frame DCT and the signal (mc_type) indicating whether the motion compensation type is performed in block units and the like. Two pixel data of the inverse discrete cosine transforming unit (see FIG. 1) is added to restore the DPCM and output in units of two pixels.

The output buffer 670 outputs the output 2 pixel data of the adder 650 to the common bus 500 in units of 12 pixels in order to be stored in the memory 300. In this case, the output buffer 670 may be implemented to process pixel data in macroblock units.

3 is a block diagram of a half-pixel compensator of a motion compensator according to the present invention. The half-pixel compensator 630 of the present invention includes a horizontal half-pixel compensator 632, a vertical line switching unit 635, and a vertical half-axis compensator. A pixel compensator 636 and a multiplexer 638. Perform horizontal half pixel compensation or vertical half pixel compensation in 8 × 8 block units.

The horizontal half-pixel compensator 632 receives nine pixel data P0 to P8 in parallel on horizontal lines, and adds eight adders A1 to A8 to add two neighboring pixel values, and the adders A1 to A8. Eight dividers B1 to B8 for obtaining an average value by dividing the sum of 2 by 2 and 8 pixels compensated for the horizontal half pixel output from the eight dividers B1 to B8 according to the horizontal half-pixel flag H_half_flag. Eight 2-1 multiplexers MUX1 to MUX8 for selectively outputting data or the originally input 8-pixel data P0 to P7 are connected in parallel.

The vertical line switching unit 634 receives 8 pixel data provided from the horizontal half-pixel compensator 632 in parallel and demultiplexes the pixels according to the vertical line selection signal Line_sel to alternate the odd line 8 pixels or the even line 8 pixels. Output That is, the vertical line switching unit 635 receives eight input-output-demultiplexers (DEMUX1) which demultiplexes eight pixel data by receiving a vertical line selection signal Line_sel that repeatedly generates 0,1 every two clocks. DEMUX8), eight odd line buffers (ODD1 to ODD8) for latching odd line pixel data output from the respective demultiplexers (DEMUX1 to DEMUX8), and even line pixels output from the respective demultiplexers (DEMUX1 to DEMUX8). It consists of eight even-line buffers EVN1 to EVN8 for latching data. The odd-numbered line buffers ODD1 to ODD8 and the even-numbered line buffers EVN1 to EVN8 are generated at a low level during the first half cycle and a high period during the remaining half cycle with two clock cycles. When the enable signal is received, the odd line buffers ODD1 to ODD8 are enabled in the low state of the enable signal to latch and output the input data, and the even line buffers EVN1 to EVN8 enable the enable signal. Enables and outputs the latched input data in the high state of.

The vertical half-pixel compensator 636 receives eight even-line 8 pixel data and odd-numbered line 8 pixel data provided from the vertical line switching unit 634, and adds eight adders (C1) that add two neighboring pixel values along the vertical axis. 8 dividers D1 to D8, each of which divides the sum of the adders C1 to C8 by 2 and obtains an average value, are arranged in parallel, and the vertical is divided according to the vertical half-pixel flag V_half_flag. The odd line 8 pixel data provided from the line switching unit 634 or the vertical axis half pixel compensated 8 pixel data provided from the dividers D1 to D8 are selected and output in parallel.

The multiplexer 638 selectively outputs 8 pixel data of the even line 8 pixels of the vertical line switching unit 634 or 8 pixel data output from the vertical half-pixel compensator 636 according to the vertical line selection signal Line_sel. Two two-input one-output multiplexers (MUX17 to MUX24) are configured in parallel.

Hereinafter, the operation and effect of the half-pixel compensation device of the present invention having the configuration as described above will be described in detail.

4 is a macroblock structure diagram, which shows a 4: 2: 0 macroblock structure diagram. (a) is a format diagram for the 16x16 luminance signal Y, and (b) and (c) are format diagrams for the 8x8 color difference signals Cb and Cr. The macroblock structure determined according to the ratio of the corresponding chrominance component to the luminance component Y is 4: 2: 0, where Y has four 8x8 blocks, and Cb and Cr each have one 8x8 block. In the case of 4: 2: 2, Cb and Cr each have two 8x8 blocks, and in 4: 4: 4, Cb and Cr each have four 8x8 blocks. In principle, the motion compensation prediction, the DCT conversion, and the quantization step size are adjusted in units of macroblocks, and whether the data encoded in each block unit is transmitted is determined in units of macroblocks.

An embodiment of the present invention will be described for half-pixel compensation processing of a 4: 2: 0 macroblock in 8 × 8 block units.

Referring to FIG. 4, the luminance signal 16x16 block of (a) is divided into 32 small boxes, and each box includes four odd-numbered lines and four even-numbered lines. The color difference signal 8x8 blocks in (b) and (C) are also divided into 32 small boxes, and each box includes two pixels for each line.

Referring to FIG. 4, the luminance signal 16x16 block of (a) is divided into 32 small boxes, and each box includes four odd-numbered lines and four even-numbered lines. The color difference signal 8x8 blocks in (b) and (C) are also divided into 32 small boxes, and each box includes two pixels for each line.

The luminance signal is input in units of 9 pixels on the horizontal axis and half pixel compensated, and the color difference signal is input in units of 5 pixels on the horizontal axis and half pixel compensated. This is because the chrominance signal block for a luminance signal of 8 × 8 block units corresponds to 4 × 4 blocks in the case of 4: 2: 0. If 4: 4: 4, the chrominance signal block also uses 8 × 8 blocks. The half-pixel compensation must be done.

One block to be input for half-pixel compensation is pixels indicated by dotted lines. P8 is added to a vertical column and L9 is added to a horizontal line to obtain an average value.

The horizontal half-pixel compensator 632 receives 9 pixel data P0 to P8 in parallel on a horizontal line, adds two neighboring pixel values, and divides the added value by 2 to obtain an average value. Find the pixel value. In other words, the half-pixel P0.5 of the clarifiers P0 and P1, the half-pixel P1.5 of the clarifiers P1 and P2, and the like are obtained, and eight half-pixel values are output in parallel. Then, the eight multiplexers MUX1 to MUX8 select the refinement data P0 to P7 of the input block if the flag value is 0 according to the horizontal half-pixel flag H_half_flag, and if the flag value is 1 The half pixel compensated 8 pixel data P0.5, P1.5, ... are selected and output.

The vertical line switching unit 634 demultiplexes the input data according to the vertical line selection signal Line_sel generated by repeating '0' and '1' every two clock cycles, and the vertical line selection signal is '0'. If the switch is connected to the input line of the odd line buffers (ODD1 to ODM8), and the switch is connected to the input line of the even line buffers (EVN1 to EVN8). The odd line buffers ODD1 to ODD8 are enabled in the low state of the enable signal ENA to latch and output the inputted odd line pixels, and the even line buffers EVN1 to EVN8 are enabled. The input even line pixel which is enabled and input in the high state of the signal ENA is latched and output.

The vertical half-pixel compensator 636 receives pixels of the odd-numbered line buffers ODD1 to ODM8 and pixels of the even-numbered line buffers EVN1 to EVN8, respectively, and adds two pixel values adjacent to each other on the vertical axis. Subsequently, the added value is divided by 2 to obtain a vertical pixel-pixel compensated 8-pixel data value. Then, according to the vertical half-pixel flag V_half_flag, if the flag value is '0', the data outputted from the odd line buffers ODD1 to ODD8 are selected. If the flag value is '1', the divider D1 to The vertical half-pixel-compensated 8-pixel data output from D8) is selected and output in parallel.

Here, the input / output states of the odd-numbered line buffer ODD1 and the even-numbered line buffer EVN1 will be described with reference to FIG. 5 to help understand the process of vertical half-pixel compensation. 5 is a diagram illustrating input and output states of the vertical line switching unit 634 and the vertical axis half pixel compensation unit 636 of FIG. 4.

(A) of FIG. 5 is a clock signal, (b) is input data 700 of the first demultiplexer DEMUX1 of the vertical line switching unit 634 (see FIG. 4), and (c) is a vertical line switching unit ( A vertical line selection signal Line_sel for the first demultiplexer DEMUX1 of 634, (d) is output data 701 of the first demultiplexer DEMUX1 when the vertical line selection signal Line_sel is '0'. , (e) is output data 702 of the first demultiplexer DEMUX1 when the vertical line selection signal Line_sel is '1', and (f) is the odd line buffer (ODD1) of the vertical line switching unit 634. ) And the enable signal ENA for the even line buffer EVN1, (g) is the output data 703 of the odd line buffer ODD1, and (h) is the even line buffer EVN1. Output data 704, and (i) is the output data value 705 of the adder C1 of the vertical half-pixel compensator 636.

As shown in FIG. 4, the first vertical line is L1, the second vertical line is represented by L2, and the like, and is input to the horizontal half-pixel compensator 632 of the half-pixel compensator 630 in the first clock. Pixel data P0 to P8 of the first vertical line L1 of the block is input in parallel at CLK1, and pixel data P0 to P8 of the second vertical line L2 of the block is input in parallel at the second clock CLK2. do.

Here, FIG. 5 is a horizontal half-pixel-processed data of pixel values of columns P0 and P1 of the L1 line to explain the vertical half-pixel processing for the pixels of the first column P0 and the second column P1 of each vertical line. The values are horizontally half-pixel-processed for the pixel values of the P0 and P1 columns of the lines L1 and L2, and the horizontally half-pixelated data values of the pixel values of the P0 and P1 columns of the lines L3 and L3 are set to L3 and the like. These 1, 1, 2, 3,... , 9, etc. are input to the first demultiplexer DEMUX1 of the vertical line switching unit 634 in synchronization with a clock. Then, as shown in FIG. 5 (b), after one block of vertical axis data is input, the vertical axis data (l'1, l'2, ...) of the next block is input again to prevent data collision. Do it.

First, at the first clock CLK1, the first demultiplexer DEMUX1 is switched to the first odd-numbered line buffer ODD1 according to the vertical line select signal Line_sel '0', and at the second clock CLK2, the first demultiplexer The same operation is repeatedly performed as the DEMUX1 is switched to the first even line buffer EVN1 according to the vertical line selection signal Line_sel '1'. At this time, as shown in (c) of FIG. 5, the vertical line selection signal Line_sel is generated by repeating '0' and '1' every clock by two clock cycles from the clock at which data input starts. Therefore, as for the output data of line 0 of the first demultiplexer DEMUX1, that is, the data input to the first odd-numbered line buffer ODD1, as shown in (d) of FIG. 5, L1, L3, L5, L7 and L9 are output. One data is maintained for two clock cycles. The output data of line 1 of the first demultiplexer DEMUX1, that is, the data input to the first even line buffer EVN1 is outputted with L2, L4, L6, and L8 as shown in FIG. The data of is maintained for 2 clock cycles and output starts after one clock delay compared with (d).

Now, the enable signal of the odd-numbered line buffer (ODD1) and the even-numbered line buffer (EVN1) is generated at a low period during the first half period as two clocks as shown in FIG. Is generated high. At this time, the odd-numbered line buffer ODD1 latches and outputs the input data which is enabled in the low state of the enable signal of (f), and the output data is delayed by one clock from the input time as shown in (g) of FIG. 5. Then, l1, l3, l5, l7, l9 are output, and one data is held for two clock cycles. The even line buffer EVN1 latches and outputs the input data which is enabled and input in the high state of the enable signal of (f), and the output data is clocked from an input time point as shown in (h) of FIG. 5. After the delay, L2, L4, L6 and L8 are output and one data is held for two clock cycles.

Therefore, the adder C1 of the vertical half-pixel compensator 636 receives data output from the odd-numbered line buffer ODD1 and the even-numbered line buffer EVN1 and adds the data for one clock, and outputs the added data. As shown in FIG. 5 (i), L1 + L2, L2 + L3, L3 + L4, L4 + L5, L5 + L6, L6 + L7, L7 + L8 and L8 + L9 are output.

Now, the ninth multiplexer MUX9 receives a result obtained by dividing the output data of the adder C1 by 2, that is, an average value, and receives the output data of the odd-numbered buffer ODD1 to receive a vertical half-pixel flag V_half_flag. According to the signal, if the flag is '1', the average value is selected. If the flag is '0', the odd line data is selected and output.

The seventeenth multiplexer MUX17 of the multiplexer 638 receives the output data of the ninth multiplexer MUX9 and the output data of the even line buffer EVN1 to the vertical line select signal Line_sel. Accordingly, if '0', output data of the ninth multiplexer MUX9 is selected, and if '1', output data of the even line buffer EVN1 is selected and output. That is, when the vertical half-pixel flag signal V_half_flag is '1', a half-pixel compensated average value is output. When the vertical half-pixel flag signal V_half_flag is '0', the odd line data is displayed at the first clock of two clock cycles. Is output, and even-line data is output at the second clock.

The description so far has described only the vertical half-pixel compensation of P0 and P1 columns. You can see that the same happens for the rest of the heat.

In this way, the final output data from the multiplexer 638 is not half-pixel compensated (corrected pixel), only horizontal axis half pixel compensation (half pixel, refined pixel), vertical axis half pixel only processed (corrected pixel, half pixel) ), Or (half-pixel, half-pixel) that handles both horizontal and vertical half-pixel compensation.

As described above, according to the present invention, the horizontal axis half-pixel flag and. According to the vertical half-pixel flag signal, the half-pixel compensation is processed in parallel in units of blocks so that the hardware can be easily implemented.

Claims (6)

In a motion compensation device for performing motion compensation in units of n × n blocks, Horizontal axis half-pixel compensator for receiving n + 1 pixel data in parallel on the horizontal line and selectively outputting the compensated n pixel data or the original input n pixel data by calculating horizontal half pixel compensation according to the horizontal half pixel flag (H_half_flag) 632); The vertical line switching unit 634 which receives the n pixel data provided from the horizontal half-pixel compensation unit 632 and demultiplexes the odd line n pixels or the even line n pixels according to the vertical line selection signal Line_sel. ; The vertical line half pixel compensation is calculated by using the even line n pixel data and the odd line n pixel data provided from the vertical line switching unit 634, and the vertical line switching unit 634 according to the vertical half pixel flag V_half_flag. A vertical half pixel compensator 636 for alternatively outputting the provided odd line n pixels or vertical axis half pixel compensated n pixel data; And And a multiplexer 638 for selectively parallel outputting the even line n pixels or the n pixel data output from the vertical half-pixel compensator 636 according to a vertical line selection signal Line_sel. Half-pixel compensator of motion compensation device. The n-adder A1 to A8 of claim 1, wherein the horizontal half-pixel compensator 632 receives n + 1 pixel data P0 to P8 in parallel to a horizontal line and adds two neighboring pixel values. Wow; N dividers B1 to B8 for dividing the sum of the adders A1 to A8 by 2 to obtain an average value; And Parallel-connected n for selectively outputting the horizontal half-pixel compensated n pixel data output from the n dividers B1 to B8 or the originally input n pixel data P0 to P7 according to the horizontal half pixel flag H_half_flag. A half-pixel compensator of a motion compensation device, comprising two 2-1 multiplexers (MUX1 to MUX8). 2. The vertical line switching unit 634 of claim 1, wherein the vertical line switching unit 634 is provided with a vertical line selection signal Line_sel that repeatedly generates 0, 1 every two clocks, and outputs n one inputs to demultiplex n pixel data. Two output demultiplexers (DEMUX1 to DEMUX8); N odd line buffers (ODD1 to ODD8) connected in parallel to latch odd line pixel data output from the respective demultiplexers (DEMUX1 to DEMUX8); And And n even line buffers (EVN1 to EVN8) connected in parallel to latch even line pixel data output from each of the demultiplexers (DEMUX1 to DEMUX8). 2. The vertical axis half pixel compensation unit 636 receives two even-line n pixel data and an odd-numbered line n pixel data provided from the vertical line switching unit 634, respectively, and receives two pixel values adjacent to each other along the vertical axis. N adders C1 to C8 connected in parallel; N dividers D1 to D8 connected in parallel to obtain an average value by dividing the sum of the adders C1 to C8 by two; And Selecting and outputting the odd line n pixel data provided from the vertical line switching unit 634 or the vertical half pixel compensated n pixel data provided from the dividers D1 to D8 according to the vertical half pixel flag V_half_flag. A half-pixel compensator for a motion compensator, comprising n multiplexers MUX9 to MUX16 connected in parallel. The pixel multiplexer 638 is an even line n pixel of the vertical line switching unit 634 or n pixels output from the vertical half-pixel compensator 636 according to a vertical line selection signal Line_sel. A half-pixel compensator for a motion compensation device, characterized in that eight two-input one-output multiplexers (MUX17 to MUX24) for selectively outputting data are configured in parallel. 4. The odd line buffers (ODD1 to ODM8) and the even line buffers (EVN1 to EVN8) are generated at a low level for the first half period and high for the other half period. The enable signal ENA is generated, and the odd-numbered line buffers ODD1 to ODD8 are enabled in the low state of the enable signal ENA to latch and output the input data. And the buffers EVN1 to EVN8 latch and output data which is enabled and input in the high state of the enable signal ENA.

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