KR102789084B1 - 컨피규러블 컴퓨팅 기판을 위한 니어-메모리 강화 컴퓨팅 블록 - Google Patents

컨피규러블 컴퓨팅 기판을 위한 니어-메모리 강화 컴퓨팅 블록 Download PDF

Info

Publication number
KR102789084B1
KR102789084B1 KR1020207021744A KR20207021744A KR102789084B1 KR 102789084 B1 KR102789084 B1 KR 102789084B1 KR 1020207021744 A KR1020207021744 A KR 1020207021744A KR 20207021744 A KR20207021744 A KR 20207021744A KR 102789084 B1 KR102789084 B1 KR 102789084B1
Authority
KR
South Korea
Prior art keywords
memory
die
configurable computing
data
interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020207021744A
Other languages
English (en)
Korean (ko)
Other versions
KR20200100824A (ko
Inventor
누완 자야세나
마이클 이그나토프스키
Original Assignee
어드밴스드 마이크로 디바이시즈, 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 어드밴스드 마이크로 디바이시즈, 인코포레이티드 filed Critical 어드밴스드 마이크로 디바이시즈, 인코포레이티드
Publication of KR20200100824A publication Critical patent/KR20200100824A/ko
Application granted granted Critical
Publication of KR102789084B1 publication Critical patent/KR102789084B1/ko
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • G06F13/1694Configuration of memory controller to different memory types
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/78Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/78Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0628Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629Configuration or reconfiguration of storage systems
    • G06F3/0631Configuration or reconfiguration of storage systems by allocating resources to storage systems
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0628Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0646Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
    • G06F3/065Replication mechanisms
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0668Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671In-line storage system
    • G06F3/0673Single storage device
    • G06F3/068Hybrid storage device

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Human Computer Interaction (AREA)
  • Logic Circuits (AREA)
  • Memory System (AREA)
  • Stored Programmes (AREA)
KR1020207021744A 2018-01-16 2018-12-21 컨피규러블 컴퓨팅 기판을 위한 니어-메모리 강화 컴퓨팅 블록 Active KR102789084B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/872,943 2018-01-16
US15/872,943 US10579557B2 (en) 2018-01-16 2018-01-16 Near-memory hardened compute blocks for configurable computing substrates
PCT/US2018/067067 WO2019143442A1 (en) 2018-01-16 2018-12-21 Near-memory hardened compute blocks for configurable computing substrates

Publications (2)

Publication Number Publication Date
KR20200100824A KR20200100824A (ko) 2020-08-26
KR102789084B1 true KR102789084B1 (ko) 2025-04-01

Family

ID=67213994

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020207021744A Active KR102789084B1 (ko) 2018-01-16 2018-12-21 컨피규러블 컴퓨팅 기판을 위한 니어-메모리 강화 컴퓨팅 블록

Country Status (6)

Country Link
US (1) US10579557B2 (https=)
EP (1) EP3740876A4 (https=)
JP (1) JP7403457B2 (https=)
KR (1) KR102789084B1 (https=)
CN (1) CN111602124B (https=)
WO (1) WO2019143442A1 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114497021A (zh) * 2020-10-27 2022-05-13 安徽寒武纪信息科技有限公司 一种集成电路装置及其加工方法、电子设备和板卡
US12229069B2 (en) * 2020-10-28 2025-02-18 Intel Corporation Accelerator controller hub
US11861366B2 (en) 2021-08-11 2024-01-02 Micron Technology, Inc. Efficient processing of nested loops for computing device with multiple configurable processing elements using multiple spoke counts
CN115810016B (zh) * 2023-02-13 2023-04-28 四川大学 肺部感染cxr图像自动识别方法、系统、存储介质及终端

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140176187A1 (en) 2012-12-23 2014-06-26 Advanced Micro Devices, Inc. Die-stacked memory device with reconfigurable logic
US20150088948A1 (en) 2013-09-20 2015-03-26 Altera Corporation Hybrid architecture for signal processing
US20170123987A1 (en) * 2015-10-30 2017-05-04 Advanced Micro Devices, Inc. In-memory interconnect protocol configuration registers
US20170255397A1 (en) * 2016-03-07 2017-09-07 Advanced Micro Devices, Inc. Efficient implementation of queues and other data structures using processing near memory
US20170344301A1 (en) * 2016-05-30 2017-11-30 Samsung Electronics Co., Ltd. Semiconductor memory device and operation method thereof

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0433029A (ja) * 1990-05-24 1992-02-04 Matsushita Electric Ind Co Ltd メモリ装置とその駆動方法
US6301696B1 (en) * 1999-03-30 2001-10-09 Actel Corporation Final design method of a programmable logic device that is based on an initial design that consists of a partial underlying physical template
US7200735B2 (en) 2002-04-10 2007-04-03 Tensilica, Inc. High-performance hybrid processor with configurable execution units
US7779177B2 (en) 2004-08-09 2010-08-17 Arches Computing Systems Multi-processor reconfigurable computing system
US8683184B1 (en) 2004-11-15 2014-03-25 Nvidia Corporation Multi context execution on a video processor
US20060242611A1 (en) * 2005-04-07 2006-10-26 Microsoft Corporation Integrating programmable logic into personal computer (PC) architecture
US20070053349A1 (en) * 2005-09-02 2007-03-08 Bryan Rittmeyer Network interface accessing multiple sized memory segments
US7539967B1 (en) * 2006-05-05 2009-05-26 Altera Corporation Self-configuring components on a device
US8095735B2 (en) 2008-08-05 2012-01-10 Convey Computer Memory interleave for heterogeneous computing
US8156307B2 (en) 2007-08-20 2012-04-10 Convey Computer Multi-processor system having at least one processor that comprises a dynamically reconfigurable instruction set
US8954685B2 (en) * 2008-06-23 2015-02-10 International Business Machines Corporation Virtualized SAS adapter with logic unit partitioning
US20100070733A1 (en) * 2008-09-18 2010-03-18 Seagate Technology Llc System and method of allocating memory locations
US8105885B1 (en) * 2010-08-06 2012-01-31 Altera Corporation Hardened programmable devices
US9448947B2 (en) * 2012-06-01 2016-09-20 Qualcomm Incorporated Inter-chip memory interface structure
US10079044B2 (en) * 2012-12-20 2018-09-18 Advanced Micro Devices, Inc. Processor with host and slave operating modes stacked with memory
US9720843B2 (en) * 2012-12-28 2017-08-01 Intel Corporation Access type protection of memory reserved for use by processor logic
US9262163B2 (en) * 2012-12-29 2016-02-16 Intel Corporation Real time instruction trace processors, methods, and systems
US9224697B1 (en) * 2013-12-09 2015-12-29 Xilinx, Inc. Multi-die integrated circuits implemented using spacer dies
US9921989B2 (en) * 2014-07-14 2018-03-20 Intel Corporation Method, apparatus and system for modular on-die coherent interconnect for packetized communication
US9870325B2 (en) * 2015-05-19 2018-01-16 Intel Corporation Common die implementation for memory devices with independent interface paths
US9698790B2 (en) * 2015-06-26 2017-07-04 Advanced Micro Devices, Inc. Computer architecture using rapidly reconfigurable circuits and high-bandwidth memory interfaces

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140176187A1 (en) 2012-12-23 2014-06-26 Advanced Micro Devices, Inc. Die-stacked memory device with reconfigurable logic
US20150088948A1 (en) 2013-09-20 2015-03-26 Altera Corporation Hybrid architecture for signal processing
US20170123987A1 (en) * 2015-10-30 2017-05-04 Advanced Micro Devices, Inc. In-memory interconnect protocol configuration registers
US20170255397A1 (en) * 2016-03-07 2017-09-07 Advanced Micro Devices, Inc. Efficient implementation of queues and other data structures using processing near memory
US20170344301A1 (en) * 2016-05-30 2017-11-30 Samsung Electronics Co., Ltd. Semiconductor memory device and operation method thereof

Also Published As

Publication number Publication date
US10579557B2 (en) 2020-03-03
JP2021510863A (ja) 2021-04-30
WO2019143442A1 (en) 2019-07-25
EP3740876A4 (en) 2021-10-06
EP3740876A1 (en) 2020-11-25
CN111602124A (zh) 2020-08-28
CN111602124B (zh) 2024-09-20
JP7403457B2 (ja) 2023-12-22
KR20200100824A (ko) 2020-08-26
US20190220426A1 (en) 2019-07-18

Similar Documents

Publication Publication Date Title
KR102789084B1 (ko) 컨피규러블 컴퓨팅 기판을 위한 니어-메모리 강화 컴퓨팅 블록
US9135185B2 (en) Die-stacked memory device providing data translation
Majer et al. The Erlangen Slot Machine: A dynamically reconfigurable FPGA-based computer
US9344091B2 (en) Die-stacked memory device with reconfigurable logic
US11704535B1 (en) Hardware architecture for a neural network accelerator
US20140181453A1 (en) Processor with Host and Slave Operating Modes Stacked with Memory
US7236525B2 (en) Reconfigurable computing based multi-standard video codec
KR20170063334A (ko) 가속기 컨트롤러 및 그것의 가속기 로직 로딩 방법
JP2022511528A (ja) 集積回路、およびデータクエリを加速させる方法
US11171652B2 (en) Method and apparatus for implementing configurable streaming networks
CN117135356A (zh) 用于片上系统中的图像帧的凹式压缩的系统和方法
WO2021249192A1 (zh) 图像处理方法及装置、机器视觉设备、电子设备和计算机可读存储介质
Shahrouzi et al. An efficient embedded multi-ported memory architecture for next-generation FPGAs
CN108025210A (zh) 芯片上的游戏引擎
JP2021510863A5 (https=)
US5835734A (en) Electronic processing and control system with programmable hardware
US12436711B2 (en) Providing fine grain access to package memory
JP5706833B2 (ja) グラフィクスメモリの非グラフィクス使用
US12555036B2 (en) Weight sparsity in data processing engines
US10198219B2 (en) Method and apparatus for en route translation in solid state graphics systems
KR20250042701A (ko) 확장가능 명령어 세트 아키텍처를 갖는 재구성가능 뉴럴 엔진
KR20240041971A (ko) 다양한 전력 상태를 갖는 디바이스에 대한 계층적 상태 저장 및 복원
US12596479B2 (en) Flexible memory system
US12511100B2 (en) System-on-a-chip including soft float function circuit
TWI922046B (zh) 數據處理方法及裝置、電子設備和存儲媒體

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601