JP7403457B2 - 構成可能コンピューティング基板についてのニアメモリのハード化された計算ブロック - Google Patents

構成可能コンピューティング基板についてのニアメモリのハード化された計算ブロック Download PDF

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JP7403457B2
JP7403457B2 JP2020536026A JP2020536026A JP7403457B2 JP 7403457 B2 JP7403457 B2 JP 7403457B2 JP 2020536026 A JP2020536026 A JP 2020536026A JP 2020536026 A JP2020536026 A JP 2020536026A JP 7403457 B2 JP7403457 B2 JP 7403457B2
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memory
die
configurable computing
data
computing board
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JP2021510863A5 (https=
JP2021510863A (ja
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ジャヤセーナ ヌワン
イグナトウスキー マイケル
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1694—Configuration of memory controller to different memory types
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G06F3/0631—Configuration or reconfiguration of storage systems by allocating resources to storage systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
    • G06F3/065—Replication mechanisms
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/068—Hybrid storage device

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Human Computer Interaction (AREA)
  • Logic Circuits (AREA)
  • Memory System (AREA)
  • Stored Programmes (AREA)
JP2020536026A 2018-01-16 2018-12-21 構成可能コンピューティング基板についてのニアメモリのハード化された計算ブロック Active JP7403457B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/872,943 2018-01-16
US15/872,943 US10579557B2 (en) 2018-01-16 2018-01-16 Near-memory hardened compute blocks for configurable computing substrates
PCT/US2018/067067 WO2019143442A1 (en) 2018-01-16 2018-12-21 Near-memory hardened compute blocks for configurable computing substrates

Publications (3)

Publication Number Publication Date
JP2021510863A JP2021510863A (ja) 2021-04-30
JP2021510863A5 JP2021510863A5 (https=) 2023-05-10
JP7403457B2 true JP7403457B2 (ja) 2023-12-22

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JP2020536026A Active JP7403457B2 (ja) 2018-01-16 2018-12-21 構成可能コンピューティング基板についてのニアメモリのハード化された計算ブロック

Country Status (6)

Country Link
US (1) US10579557B2 (https=)
EP (1) EP3740876A4 (https=)
JP (1) JP7403457B2 (https=)
KR (1) KR102789084B1 (https=)
CN (1) CN111602124B (https=)
WO (1) WO2019143442A1 (https=)

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CN114497021A (zh) * 2020-10-27 2022-05-13 安徽寒武纪信息科技有限公司 一种集成电路装置及其加工方法、电子设备和板卡
US12229069B2 (en) * 2020-10-28 2025-02-18 Intel Corporation Accelerator controller hub
US11861366B2 (en) 2021-08-11 2024-01-02 Micron Technology, Inc. Efficient processing of nested loops for computing device with multiple configurable processing elements using multiple spoke counts
CN115810016B (zh) * 2023-02-13 2023-04-28 四川大学 肺部感染cxr图像自动识别方法、系统、存储介质及终端

Citations (6)

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US20140176187A1 (en) 2012-12-23 2014-06-26 Advanced Micro Devices, Inc. Die-stacked memory device with reconfigurable logic
US20150088948A1 (en) 2013-09-20 2015-03-26 Altera Corporation Hybrid architecture for signal processing
US20160380635A1 (en) 2015-06-26 2016-12-29 Advanced Micro Devices, Inc. Computer architecture using rapidly reconfigurable circuits and high-bandwidth memory interfaces
US20170123987A1 (en) 2015-10-30 2017-05-04 Advanced Micro Devices, Inc. In-memory interconnect protocol configuration registers
US20170255397A1 (en) 2016-03-07 2017-09-07 Advanced Micro Devices, Inc. Efficient implementation of queues and other data structures using processing near memory
US20170344301A1 (en) 2016-05-30 2017-11-30 Samsung Electronics Co., Ltd. Semiconductor memory device and operation method thereof

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US6301696B1 (en) * 1999-03-30 2001-10-09 Actel Corporation Final design method of a programmable logic device that is based on an initial design that consists of a partial underlying physical template
US7200735B2 (en) 2002-04-10 2007-04-03 Tensilica, Inc. High-performance hybrid processor with configurable execution units
US7779177B2 (en) 2004-08-09 2010-08-17 Arches Computing Systems Multi-processor reconfigurable computing system
US8683184B1 (en) 2004-11-15 2014-03-25 Nvidia Corporation Multi context execution on a video processor
US20060242611A1 (en) * 2005-04-07 2006-10-26 Microsoft Corporation Integrating programmable logic into personal computer (PC) architecture
US20070053349A1 (en) * 2005-09-02 2007-03-08 Bryan Rittmeyer Network interface accessing multiple sized memory segments
US7539967B1 (en) * 2006-05-05 2009-05-26 Altera Corporation Self-configuring components on a device
US8095735B2 (en) 2008-08-05 2012-01-10 Convey Computer Memory interleave for heterogeneous computing
US8156307B2 (en) 2007-08-20 2012-04-10 Convey Computer Multi-processor system having at least one processor that comprises a dynamically reconfigurable instruction set
US8954685B2 (en) * 2008-06-23 2015-02-10 International Business Machines Corporation Virtualized SAS adapter with logic unit partitioning
US20100070733A1 (en) * 2008-09-18 2010-03-18 Seagate Technology Llc System and method of allocating memory locations
US8105885B1 (en) * 2010-08-06 2012-01-31 Altera Corporation Hardened programmable devices
US9448947B2 (en) * 2012-06-01 2016-09-20 Qualcomm Incorporated Inter-chip memory interface structure
US10079044B2 (en) * 2012-12-20 2018-09-18 Advanced Micro Devices, Inc. Processor with host and slave operating modes stacked with memory
US9720843B2 (en) * 2012-12-28 2017-08-01 Intel Corporation Access type protection of memory reserved for use by processor logic
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US9224697B1 (en) * 2013-12-09 2015-12-29 Xilinx, Inc. Multi-die integrated circuits implemented using spacer dies
US9921989B2 (en) * 2014-07-14 2018-03-20 Intel Corporation Method, apparatus and system for modular on-die coherent interconnect for packetized communication
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US20140176187A1 (en) 2012-12-23 2014-06-26 Advanced Micro Devices, Inc. Die-stacked memory device with reconfigurable logic
US20150088948A1 (en) 2013-09-20 2015-03-26 Altera Corporation Hybrid architecture for signal processing
US20160380635A1 (en) 2015-06-26 2016-12-29 Advanced Micro Devices, Inc. Computer architecture using rapidly reconfigurable circuits and high-bandwidth memory interfaces
US20170123987A1 (en) 2015-10-30 2017-05-04 Advanced Micro Devices, Inc. In-memory interconnect protocol configuration registers
US20170255397A1 (en) 2016-03-07 2017-09-07 Advanced Micro Devices, Inc. Efficient implementation of queues and other data structures using processing near memory
US20170344301A1 (en) 2016-05-30 2017-11-30 Samsung Electronics Co., Ltd. Semiconductor memory device and operation method thereof

Also Published As

Publication number Publication date
KR102789084B1 (ko) 2025-04-01
US10579557B2 (en) 2020-03-03
JP2021510863A (ja) 2021-04-30
WO2019143442A1 (en) 2019-07-25
EP3740876A4 (en) 2021-10-06
EP3740876A1 (en) 2020-11-25
CN111602124A (zh) 2020-08-28
CN111602124B (zh) 2024-09-20
KR20200100824A (ko) 2020-08-26
US20190220426A1 (en) 2019-07-18

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