CN111602124B - 用于可配置计算基板的近存储器硬化计算块 - Google Patents
用于可配置计算基板的近存储器硬化计算块 Download PDFInfo
- Publication number
- CN111602124B CN111602124B CN201880086468.3A CN201880086468A CN111602124B CN 111602124 B CN111602124 B CN 111602124B CN 201880086468 A CN201880086468 A CN 201880086468A CN 111602124 B CN111602124 B CN 111602124B
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- CN
- China
- Prior art keywords
- memory
- die
- configurable computing
- data
- interface
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1694—Configuration of memory controller to different memory types
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
- G06F3/0631—Configuration or reconfiguration of storage systems by allocating resources to storage systems
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
- G06F3/065—Replication mechanisms
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/068—Hybrid storage device
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Human Computer Interaction (AREA)
- Logic Circuits (AREA)
- Memory System (AREA)
- Stored Programmes (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15/872,943 | 2018-01-16 | ||
| US15/872,943 US10579557B2 (en) | 2018-01-16 | 2018-01-16 | Near-memory hardened compute blocks for configurable computing substrates |
| PCT/US2018/067067 WO2019143442A1 (en) | 2018-01-16 | 2018-12-21 | Near-memory hardened compute blocks for configurable computing substrates |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111602124A CN111602124A (zh) | 2020-08-28 |
| CN111602124B true CN111602124B (zh) | 2024-09-20 |
Family
ID=67213994
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201880086468.3A Active CN111602124B (zh) | 2018-01-16 | 2018-12-21 | 用于可配置计算基板的近存储器硬化计算块 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US10579557B2 (https=) |
| EP (1) | EP3740876A4 (https=) |
| JP (1) | JP7403457B2 (https=) |
| KR (1) | KR102789084B1 (https=) |
| CN (1) | CN111602124B (https=) |
| WO (1) | WO2019143442A1 (https=) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114497021A (zh) * | 2020-10-27 | 2022-05-13 | 安徽寒武纪信息科技有限公司 | 一种集成电路装置及其加工方法、电子设备和板卡 |
| US12229069B2 (en) * | 2020-10-28 | 2025-02-18 | Intel Corporation | Accelerator controller hub |
| US11861366B2 (en) | 2021-08-11 | 2024-01-02 | Micron Technology, Inc. | Efficient processing of nested loops for computing device with multiple configurable processing elements using multiple spoke counts |
| CN115810016B (zh) * | 2023-02-13 | 2023-04-28 | 四川大学 | 肺部感染cxr图像自动识别方法、系统、存储介质及终端 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8738891B1 (en) * | 2004-11-15 | 2014-05-27 | Nvidia Corporation | Methods and systems for command acceleration in a video processor via translation of scalar instructions into vector instructions |
Family Cites Families (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0433029A (ja) * | 1990-05-24 | 1992-02-04 | Matsushita Electric Ind Co Ltd | メモリ装置とその駆動方法 |
| US6301696B1 (en) * | 1999-03-30 | 2001-10-09 | Actel Corporation | Final design method of a programmable logic device that is based on an initial design that consists of a partial underlying physical template |
| US7200735B2 (en) | 2002-04-10 | 2007-04-03 | Tensilica, Inc. | High-performance hybrid processor with configurable execution units |
| US7779177B2 (en) | 2004-08-09 | 2010-08-17 | Arches Computing Systems | Multi-processor reconfigurable computing system |
| US20060242611A1 (en) * | 2005-04-07 | 2006-10-26 | Microsoft Corporation | Integrating programmable logic into personal computer (PC) architecture |
| US20070053349A1 (en) * | 2005-09-02 | 2007-03-08 | Bryan Rittmeyer | Network interface accessing multiple sized memory segments |
| US7539967B1 (en) * | 2006-05-05 | 2009-05-26 | Altera Corporation | Self-configuring components on a device |
| US8095735B2 (en) | 2008-08-05 | 2012-01-10 | Convey Computer | Memory interleave for heterogeneous computing |
| US8156307B2 (en) | 2007-08-20 | 2012-04-10 | Convey Computer | Multi-processor system having at least one processor that comprises a dynamically reconfigurable instruction set |
| US8954685B2 (en) * | 2008-06-23 | 2015-02-10 | International Business Machines Corporation | Virtualized SAS adapter with logic unit partitioning |
| US20100070733A1 (en) * | 2008-09-18 | 2010-03-18 | Seagate Technology Llc | System and method of allocating memory locations |
| US8105885B1 (en) * | 2010-08-06 | 2012-01-31 | Altera Corporation | Hardened programmable devices |
| US9448947B2 (en) * | 2012-06-01 | 2016-09-20 | Qualcomm Incorporated | Inter-chip memory interface structure |
| US8922243B2 (en) | 2012-12-23 | 2014-12-30 | Advanced Micro Devices, Inc. | Die-stacked memory device with reconfigurable logic |
| US10079044B2 (en) * | 2012-12-20 | 2018-09-18 | Advanced Micro Devices, Inc. | Processor with host and slave operating modes stacked with memory |
| US9720843B2 (en) * | 2012-12-28 | 2017-08-01 | Intel Corporation | Access type protection of memory reserved for use by processor logic |
| US9262163B2 (en) * | 2012-12-29 | 2016-02-16 | Intel Corporation | Real time instruction trace processors, methods, and systems |
| CN105745843B (zh) | 2013-09-20 | 2019-06-14 | 阿尔特拉公司 | 用于信号处理的混合架构 |
| US9224697B1 (en) * | 2013-12-09 | 2015-12-29 | Xilinx, Inc. | Multi-die integrated circuits implemented using spacer dies |
| US9921989B2 (en) * | 2014-07-14 | 2018-03-20 | Intel Corporation | Method, apparatus and system for modular on-die coherent interconnect for packetized communication |
| US9870325B2 (en) * | 2015-05-19 | 2018-01-16 | Intel Corporation | Common die implementation for memory devices with independent interface paths |
| US9698790B2 (en) * | 2015-06-26 | 2017-07-04 | Advanced Micro Devices, Inc. | Computer architecture using rapidly reconfigurable circuits and high-bandwidth memory interfaces |
| US9767028B2 (en) * | 2015-10-30 | 2017-09-19 | Advanced Micro Devices, Inc. | In-memory interconnect protocol configuration registers |
| US9977609B2 (en) * | 2016-03-07 | 2018-05-22 | Advanced Micro Devices, Inc. | Efficient accesses of data structures using processing near memory |
| KR102548591B1 (ko) * | 2016-05-30 | 2023-06-29 | 삼성전자주식회사 | 반도체 메모리 장치 및 그것의 동작 방법 |
-
2018
- 2018-01-16 US US15/872,943 patent/US10579557B2/en active Active
- 2018-12-21 CN CN201880086468.3A patent/CN111602124B/zh active Active
- 2018-12-21 JP JP2020536026A patent/JP7403457B2/ja active Active
- 2018-12-21 EP EP18900755.2A patent/EP3740876A4/en active Pending
- 2018-12-21 KR KR1020207021744A patent/KR102789084B1/ko active Active
- 2018-12-21 WO PCT/US2018/067067 patent/WO2019143442A1/en not_active Ceased
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8738891B1 (en) * | 2004-11-15 | 2014-05-27 | Nvidia Corporation | Methods and systems for command acceleration in a video processor via translation of scalar instructions into vector instructions |
Also Published As
| Publication number | Publication date |
|---|---|
| KR102789084B1 (ko) | 2025-04-01 |
| US10579557B2 (en) | 2020-03-03 |
| JP2021510863A (ja) | 2021-04-30 |
| WO2019143442A1 (en) | 2019-07-25 |
| EP3740876A4 (en) | 2021-10-06 |
| EP3740876A1 (en) | 2020-11-25 |
| CN111602124A (zh) | 2020-08-28 |
| JP7403457B2 (ja) | 2023-12-22 |
| KR20200100824A (ko) | 2020-08-26 |
| US20190220426A1 (en) | 2019-07-18 |
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