JP2021510863A5 - - Google Patents

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Publication number
JP2021510863A5
JP2021510863A5 JP2020536026A JP2020536026A JP2021510863A5 JP 2021510863 A5 JP2021510863 A5 JP 2021510863A5 JP 2020536026 A JP2020536026 A JP 2020536026A JP 2020536026 A JP2020536026 A JP 2020536026A JP 2021510863 A5 JP2021510863 A5 JP 2021510863A5
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JP
Japan
Prior art keywords
memory
die
configurable computing
data
computing board
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JP2020536026A
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English (en)
Japanese (ja)
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JP2021510863A (ja
JP7403457B2 (ja
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Priority claimed from US15/872,943 external-priority patent/US10579557B2/en
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Publication of JP2021510863A publication Critical patent/JP2021510863A/ja
Publication of JP2021510863A5 publication Critical patent/JP2021510863A5/ja
Application granted granted Critical
Publication of JP7403457B2 publication Critical patent/JP7403457B2/ja
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JP2020536026A 2018-01-16 2018-12-21 構成可能コンピューティング基板についてのニアメモリのハード化された計算ブロック Active JP7403457B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/872,943 2018-01-16
US15/872,943 US10579557B2 (en) 2018-01-16 2018-01-16 Near-memory hardened compute blocks for configurable computing substrates
PCT/US2018/067067 WO2019143442A1 (en) 2018-01-16 2018-12-21 Near-memory hardened compute blocks for configurable computing substrates

Publications (3)

Publication Number Publication Date
JP2021510863A JP2021510863A (ja) 2021-04-30
JP2021510863A5 true JP2021510863A5 (https=) 2023-05-10
JP7403457B2 JP7403457B2 (ja) 2023-12-22

Family

ID=67213994

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2020536026A Active JP7403457B2 (ja) 2018-01-16 2018-12-21 構成可能コンピューティング基板についてのニアメモリのハード化された計算ブロック

Country Status (6)

Country Link
US (1) US10579557B2 (https=)
EP (1) EP3740876A4 (https=)
JP (1) JP7403457B2 (https=)
KR (1) KR102789084B1 (https=)
CN (1) CN111602124B (https=)
WO (1) WO2019143442A1 (https=)

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US12229069B2 (en) * 2020-10-28 2025-02-18 Intel Corporation Accelerator controller hub
US11861366B2 (en) 2021-08-11 2024-01-02 Micron Technology, Inc. Efficient processing of nested loops for computing device with multiple configurable processing elements using multiple spoke counts
CN115810016B (zh) * 2023-02-13 2023-04-28 四川大学 肺部感染cxr图像自动识别方法、系统、存储介质及终端

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US7200735B2 (en) 2002-04-10 2007-04-03 Tensilica, Inc. High-performance hybrid processor with configurable execution units
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CN105745843B (zh) 2013-09-20 2019-06-14 阿尔特拉公司 用于信号处理的混合架构
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