KR102677429B1 - Digital converting apparatus of sensor signal and converting method therefor - Google Patents

Abstract

A digital conversion device that converts a time difference between a start signal and a stop signal input from at least one sensor into a digital value includes: a clock signal generator that generates a first clock signal by multiplying the frequency of the input oscillator signal; a time difference generator that receives the start signal and the stop signal and generates a first time difference signal that is a time difference between the start signal and the stop signal; Correction for receiving the output of the first oscillator and the first clock signal and generating a correction signal to correct the error of the first time difference signal according to the error between the output of the first oscillator and the first clock signal. signal generator; and a correction time difference generator configured to receive the correction signal and the first time difference signal and generate a second time difference signal by correcting the first time difference signal.

Description

Digital conversion device for sensor signals and method for converting the same {DIGITAL CONVERTING APPARATUS OF SENSOR SIGNAL AND CONVERTING METHOD THEREFOR}

The present invention relates to a device for digitally converting sensor signals and a method for converting the same.

A sensor signal digital conversion device is a device that measures the time difference between a start signal and a stop signal, which are two input signals input from at least one sensor, and is used for measurements such as distance and pressure using a sensor.

However, when a sensor signal digital conversion device is integrated into a semiconductor chip, it is necessary to robustly respond to the manufacturing process, operating temperature, and voltage. Additionally, a digital conversion device for sensor signals requires time measurement with a precision of about 25 ps for measurement for various purposes. In other words, for measurement for various purposes, a digital conversion device for sensor signals needs to output time differences with high resolution.

Domestic registered patent No. 10-2204827-0000: 8-bit two-stage time-to-digital converter using pulse movement time difference repeating circuit with 5ps resolution (registered on January 13, 2021).

The present invention is aimed at solving the technical problems described above. When integrated into a semiconductor chip, the present invention can respond robustly to the manufacturing process, operating temperature and voltage, etc., and can detect the time difference between the start signal and the stop signal with high resolution. The purpose is to provide a digital conversion device for sensor signals that can output and a method for converting the same.

A digital conversion device that converts a time difference between a start signal and a stop signal input from at least one sensor into a digital value includes: a clock signal generator that generates a first clock signal by multiplying the frequency of the input oscillator signal; a time difference generator that receives the start signal and the stop signal and generates a first time difference signal that is a time difference between the start signal and the stop signal; Receives the output of the first oscillator and the first clock signal, and generates a correction signal to correct the error of the first time difference signal according to the error between the output of the first oscillator and the first clock signal. Correction signal generator; and a correction time difference generator configured to receive the correction signal and the first time difference signal and generate a second time difference signal by correcting the first time difference signal.

Specifically, the correction signal includes a first correction signal that is the first portion of the correction signal and a second correction signal that is the second portion of the correction signal. In addition, the correction time difference generator adds the first time difference signal multiplied by the first correction signal and a value obtained by adding the first time difference signal to the second correction signal to generate the second time difference. It is desirable to generate a difference signal.

Additionally, the correction signal generator includes a fifth divider that divides the output of the first oscillator; a second counter that receives the first clock signal as a clock signal and outputs a second counting value obtained by counting the output of the fifth divider; and a correction signal calculator that calculates the correction signal using a ratio between a preset second value and the second counting value.

In addition, the digital conversion device uses the first clock signal and a signal obtained by inverting the first clock signal to generate a first clock signal, which is a value corresponding to the time value of the period of the first clock signal or the half-cycle of the first clock signal. It may further include a reference time value calculation unit that calculates a time value.

Specifically, the reference time value calculation unit includes L delay cells connected in series in a chain structure and delaying the input data signal by the delay time and outputting the data, and the data of the frontmost delay cell among the L delay cells. After the first clock signal, which is a signal, is activated, the number of cells to which the first clock signal is transmitted among the L delay cells is used at one point of the rising edge or the falling edge of the inverted signal of the first clock signal. , a 1-1 time value calculator that calculates a 1-1 time value; Alternatively, the first clock signal includes L delay cells connected in series in a chain structure and each delaying the input data signal by the delay time and outputting it, wherein the first clock signal is the data signal of the frontmost delay cell among the L delay cells. After the inversion signal is activated, at one point of the rising edge or the falling edge of the first clock signal, using the number of cells in which the inversion signal of the first clock signal is transmitted among the L delay cells, 1- a first-second time value calculator that calculates two time values; It includes at least one of the following, wherein L is a natural number of 5 or more.

In addition, the reference time value calculation unit preferably further includes a first time value calculator that calculates the first time value using the 1-1 time value and the 1-2 time value. .

In addition, the digital conversion device calculates a first start-stop value by counting between the start signal and the stop signal using the first clock signal or an inverted signal of the first clock signal. It further includes a stop value generator. Specifically, the first start-stop value is the time from the first edge after the start signal is input to the second edge before the stop signal is input. In addition, the first edge is a rising edge or falling edge of the first clock signal output for the first time after the start signal is input; Or, the rising edge or falling edge of the inverted signal of the first clock signal. Additionally, the second edge may be a rising edge or a falling edge of the first clock signal output immediately before the stop signal is input; Or, the rising edge or falling edge of the inverted signal of the first clock signal.

In addition, the digital conversion device calculates a 2-1 time value from when the start signal is input to before the first edge and a 2-2 time value from the second edge to the stop signal, It may further include a second start-stop value generator that calculates a second start-stop value by adding the 2-1 time value and the 2-2 time value.

Specifically, the second start-stop value generator includes S delay cells connected in series in a chain structure and outputting the input data signal by delaying each delay time, and the frontmost delay among the S delay cells is After the start signal is activated with the data signal of the cell, the first clock signal or the a 2-1 time value calculator that calculates the 2-1 time value using the number of cells to which the inverted signal of the first clock signal is transmitted; and S delay cells connected in series in a chain structure and outputting the input data signal by delaying it respectively by the delay time, after the stop signal is activated with the data signal of the frontmost delay cell among the S delay cells. , of the cell to which the first clock signal or the inverted signal of the first clock signal is transmitted among the S delay cells at one of the rising edge or falling edge of the first clock signal or the inverted signal of the first clock signal. a 2-2 preliminary time value calculator that calculates a 2-2 preliminary time value using the number; and a 2-2 time value calculator that calculates the 2-2 time value by subtracting the 2-2 preliminary time value from the first time value, wherein S is a natural number of 5 or more. desirable.

In addition, the digital conversion device further includes a normalization unit that calculates a second start-stop normalization value using a ratio of the second start-stop value and the first time value, but generates the time difference. The unit receives the first start-stop value and the second start-stop normalization value and generates the first time difference signal.

In addition, the clock signal generator includes P delay cells connected in series in a chain structure to each delay the input data signal by the delay time and output the oscillator signal to the frontmost delay cell among the P delay cells. a first delay receiving this data signal; A second cell comprising P delay cells connected in series in a chain structure to output an input data signal after delaying each delay time, wherein the frontmost delay cell of the P delay cells receives the oscillator signal as a data signal. delay period; a first flip-flop that receives the output of the first delayer as a data signal and the output of the second delayer as a clock signal; and a first counter that receives the oscillator signal as a clock signal and counts the output of the first flip-flop as a data signal. Specifically, the output of the first counter is input as a control signal of the second delayer, and the delay time of each of the P delay cells included in the second delayer is set by the control signal of the second delayer. . Here, P is preferably a natural number of 3 or more.

Additionally, the delay time of each of the P delay cells included in the first delay unit includes the sum of the 1-1 delay time and the 1-2 delay time. In addition, the 1-1 delay times of each of the P delay cells all have the same value. Additionally, the 1-2 delay time of each of the P delay cells may be set by a control signal input to the first delay to have a unique value of '0' or each of the P delay cells.

Preferably, the unique value of each of the P delay cells gradually increases as the position of the corresponding delay cell moves toward the rear end of the chain structure.

In addition, the clock signal generator includes P delay cells connected in series in a chain structure, each delaying the input data signal by the delay time and outputting the output, and the output of the first flip-flop is output at the most delay cells among the P delay cells. A third delay device in which the front-stage delay cell receives a data signal; And a 1-1 clock signal generator that generates a 1-1 clock signal using the output of the first flip-flop and the output of the third delay, and the output of the first counter is N The delay time of each of the P delay cells included in the third delayer can be set by the signal divided by . Here, N is preferably a natural number of 2 or more.

A digital conversion method for converting the time difference between a start signal and a stop signal input from at least one sensor into a digital value includes a clock signal generation step of generating a first clock signal by multiplying the frequency of an input oscillator signal; A time difference generating step of receiving the start signal and the stop signal and generating a first time difference signal that is a time difference between the start signal and the stop signal; Receives the output of the first oscillator and the first clock signal, and generates a correction signal to correct the error of the first time difference signal according to the error between the output of the first oscillator and the first clock signal. A correction signal generation step; and a correction time difference generating step of receiving the correction signal and the first time difference signal and generating a second time difference signal by correcting the first time difference signal.

Specifically, the correction signal includes a first correction signal that is a first portion of the correction signal and a second correction signal that is a second portion of the correction signal, and the step of generating the correction time difference includes: It is preferable to generate the second time difference signal by adding a value obtained by multiplying the signal by the first correction signal and a value obtained by adding the second correction signal to the first time difference signal.

In addition, the correction signal generating step includes a fifth dividing step of dividing the output of the first oscillator; a second counting step of receiving the first clock signal as a clock signal and outputting a second counting value obtained by counting the output of the fifth dividing step; and a correction signal calculation step of calculating the correction signal using a ratio between a preset second value and the second counting value.

In addition, the digital conversion method uses the first clock signal and a signal obtained by inverting the first clock signal to generate a first clock signal, which is a value corresponding to the time value of the period of the first clock signal or the half-cycle of the first clock signal. It is preferable to further include a reference time value calculation step of calculating a 1 time value.

Specifically, the reference time value calculation step uses L delay cells that are connected in series in a chain structure and each delay the input data signal by the delay time and output it. Among the L delay cells, the frontmost delay cell is used. After the first clock signal, which is a data signal, is activated, the number of cells to which the first clock signal is transmitted among L delay cells is used at one of the rising edge or the falling edge of the inverted signal of the first clock signal. Thus, a 1-1 time value calculation step of calculating a 1-1 time value; Alternatively, L delay cells connected in series in a chain structure, each delaying the input data signal by the delay time, are used, and the first clock signal, which is the data signal of the frontmost delay cell among the L delay cells, is used. After the inversion signal is activated, at one point of the rising edge or the falling edge of the first clock signal, using the number of cells in which the inversion signal of the first clock signal is transmitted among the L delay cells, 1- A 1-2 time value calculation step of calculating 2 time values; It includes at least one of the following, wherein L is a natural number of 5 or more. In addition, the reference time value calculating step preferably further includes a first time value calculating step of calculating the first time value using the 1-1 time value and the 1-2 time value. do.

In addition, the digital conversion method calculates a first start-stop value by counting between the start signal and the stop signal using the first clock signal or an inverted signal of the first clock signal. A stop value generation step may be further included. Here, the first edge is a rising edge or falling edge of the first clock signal output for the first time after the start signal is input; Or, the rising edge or falling edge of the inverted signal of the first clock signal. In addition, the second edge may be a rising edge or a falling edge of the first clock signal output immediately before the stop signal is input; Or, the rising edge or falling edge of the inverted signal of the first clock signal.

In addition, the digital conversion method calculates a 2-1 time value from when the start signal is input to before the first edge and a 2-2 time value from the second edge to the stop signal, It is preferable to further include a second start-stop value generating step of calculating a second start-stop value by adding the 2-1 time value and the 2-2 time value.

Specifically, the second start-stop value generation step uses S delay cells that are connected in series in a chain structure and each delay the input data signal by the delay time and output it. Among the S delay cells, the frontmost cell is used. After the start signal is activated with the data signal of the delay cell, using the number of cells to which the first clock signal or the inverted signal of the first clock signal is transmitted among the S delay cells up to the first edge, the second A 2-1 time value calculation step of calculating a -1 time value; S delay cells are connected in series in a chain structure and each outputs an input data signal delayed by the delay time. After the stop signal is activated with the data signal of the frontmost delay cell among the S delay cells, The number of cells to which the first clock signal or the inverted signal of the first clock signal is transmitted among S delay cells at one of the rising edge or falling edge of the first clock signal or the inverted signal of the first clock signal A 2-2 preliminary time value calculating step of calculating a 2-2 preliminary time value using; and a 2-2 time value calculation step of calculating the 2-2 time value by subtracting the 2-2 preliminary time value from the first time value, wherein S is a natural number of 5 or more.

In addition, the digital conversion method further includes a normalization step of calculating a second start-stop normalization value using a ratio of the second start-stop value and the first time value, but generating the time difference In the step, the first start-stop value and the second start-stop normalization value are input and the first time difference signal is generated.

Specifically, the clock signal generation step uses P delay cells that are connected in series in a chain structure and each delay the input data signal by the delay time and output it, and send the oscillator signal to the frontmost of the P delay cells. A first delay step in which a delay cell receives a data signal and delays it; P delay cells are connected in series in a chain structure, each delaying and outputting the input data signal by the delay time, and the frontmost delay cell among the P delay cells receives the oscillator signal as a data signal and delays it. a second delay stage; A flip that uses a first flip-flop, receives the output of the first delay stage as a data signal of the first flip-flop, and receives and outputs the output of the second delay stage as a clock signal of the first flip-flop. flop stage; A first counting step of receiving the oscillator signal as a clock signal and counting the output of the first flip-flop as a data signal; P delay cells are connected in series in a chain structure, each delaying the input data signal by the delay time to output it, and the output of the first flip-flop is converted into a data signal by the frontmost delay cell among the P delay cells. a third delay stage that receives input and delays it; and a 1-1 clock signal generation step of generating a 1-1 clock signal using the output of the first flip-flop and the output of the third delay step. In addition, the output of the first counting step is input as a control signal of the second delay step, and the delay time of each of the P delay cells used in the second delay step is determined by the control signal of the second delay step. is set, and P is a natural number of 3 or more. In addition, the delay time of each of the P delay cells used in the first delay step includes the sum of the 1-1 delay time and the 1-2 delay time.

Preferably, the 1-1 delay times of each of the P delay cells all have the same value, and in the first delay step, the control signal of the first delay step is input, and the The 1-2 delay time of each of the P delay cells may be set to '0' or a unique value for each of the P delay cells by a control signal.

In addition, it is preferable that the unique value of each of the P delay cells gradually increases as the position of the corresponding delay cell moves toward the rear end of the chain structure.

In addition, in the third delay step, a signal obtained by dividing the output of the first counting step by N is input as a control signal of the third delay step, and is input to the third delay step by the control signal of the third delay step. The delay time of each of the P delay cells included is set, and N is a natural number of 2 or more.

According to a digital conversion device for a sensor signal and its conversion method, when integrated into a semiconductor chip, it can robustly respond to manufacturing processes, operating temperature and voltage, etc., and output the time difference between a start signal and a stop signal with high resolution.

1 is a configuration diagram of a sensor signal digital conversion device according to an embodiment.
Figure 2 is a configuration diagram of a clock signal generator.
Figure 3 is a configuration diagram of a first delay device according to an embodiment.
Figure 4 is a configuration diagram of a correction signal generator according to an embodiment.
Figure 5 is a configuration diagram of a reference time value calculation unit according to an embodiment.
Figure 6 is a configuration diagram of a 1-1 time value calculator according to an embodiment.
Figure 7 is a configuration diagram of a first start-stop value generator according to an embodiment.
Figure 8 is a configuration diagram of a second start-stop value generator according to an embodiment.
9 is an output timing diagram of the first start-stop value generator and the second start-stop value generator.

Hereinafter, a sensor signal digital conversion device and a conversion method according to an embodiment of the present invention will be described in detail with reference to the attached drawings.

Of course, the following examples of the present invention are only intended to embody the present invention and do not limit or limit the scope of the present invention. Anything that can be easily inferred by an expert in the technical field to which the present invention belongs from the detailed description and examples of the present invention will be interpreted as falling within the scope of the rights of the present invention.

First, Figure 1 shows a configuration diagram of a sensor signal digital conversion device 100 according to an embodiment.

The sensor signal digital conversion device 100 is a device that measures the time difference between a start signal (Sig(Start)) and a stop signal (Sig(Stop)), which are two input signals input from at least one sensor. In other words, the sensor signal digital conversion device 100 is a device that receives a start signal (Sig (Start)) and a stop signal (Sig (Stop)) from at least one sensor and converts the time difference into a digital signal. .

Each component of the sensor signal digital conversion device 100 according to an embodiment may be implemented by one of a circuit, a processor, and a combination of a circuit and a processor. In addition, the sensor signal digital conversion device 100 according to one embodiment may be implemented in the form of a single semiconductor chip.

As can be seen from FIG. 1, the sensor signal digital conversion device 100 according to one embodiment includes a clock signal generator 10, a correction signal generator 20, a reference time value calculator 30, and a clock signal generator 10. It is configured to include a 1 start-stop value generation unit 40, a second start-stop value generation unit 50, a normalization unit 60, a time difference generation unit 70, and a correction time difference generation unit 80. .

Figure 2 shows a configuration diagram of the clock signal generator 10.

The clock signal generator 10 serves to generate a first clock signal by multiplying the frequency of the input oscillator signal.

As can be seen from FIG. 2, the clock signal generator 10 generates one of the output of the first oscillator (Sig(OSC1)) and the output of the second oscillator (Sig(OSC2)) through the mux (M). It is input as an oscillator signal.

The first oscillator may be a crystal oscillator outside the semiconductor in which the sensor signal digital conversion device 100 is integrated, and the second oscillator may be a ring oscillator implemented inside the same semiconductor chip as the sensor signal digital conversion device 100. Examples include: That is, the first oscillator is not affected by the semiconductor chip manufacturing process, but the second oscillator is affected by the semiconductor chip manufacturing process.

Specifically, the clock signal generator 10 includes first to sixth delays (11a, 11b, 11c, 11d, 11e, 11f), a first flip-flop 12, a first counter 13, and a first -1 to 1-4 clock signal generators (14a, 14b, 14c, 14d) and first to fourth dividers (15a, 15b, 15c, 15d).

Figure 3 shows a configuration diagram of the first delay 11a according to one embodiment.

The first delay 11a includes P delay cells D11_1, D11_2, ..., D11_P, which are connected in series in a chain structure and each delay the input data signal by the delay time and output it. In addition, one of the oscillator signal output from the mux (M), the output of the first oscillator (Sig(OSC1)) and the output of the second oscillator (Sig(OSC2)), is connected to P delay cells (D11_1, D11_2, ..., D11_P). ), the front-most delay cell (D11_1) receives the data signal. Here, P is a natural number of 3 or more.

The delay time of each of the P delay cells (D11_1, D11_2, ..., D11_P) included in the first delay 11a includes the sum of the 1-1 delay time and the 1-2 delay time. That is, the 1-1 delay times of each of the P delay cells (D11_1, D11_2, ..., D11_P) all have the same value. For example, the 1-1 delay time may be the delay time by one gate.

In addition, the 1st-2nd delay time of each of the P delay cells (D11_1, D11_2, ..., D11_P) is set to '0' or the first delay time to have a unique value for each of the P delay cells (D11_1, D11_2, ..., D11_P). It can be set by the control signal (Sig(I)) input to the delayer (11a). P is a natural number of 3 or more.

For example, if P is 3 and the control signal (Sig(I)) input to the first delay cell (11a) is '101', the 1-2 delay times of the first delay cell (D11_1) and the third delay cell are It has a unique value, and the 1-2 delay time of the second delay cell (D11_2) is '0'.

The eigenvalue of each of the P delay cells (D11_1, D11_2, ..., D11_P) gradually increases as the position of the corresponding delay cells (D11_1, D11_2, ..., D11_P) moves toward the rear end of the chain structure. For example, when P is 3, depending on the order of delay cells (D11_1, D11_2, ..., D11_P), the eigenvalue is 2 of the previous delay cells (D11_1, D11_2, ..., D11_P), such as 50ps, 100ps, 200ps It can be designed to have a delay time of two times. In addition, it is preferable that the eigenvalue of each of the P delay cells (D11_1, D11_2, ..., D11_P) is significantly larger than the 1-1 delay time. By designing the eigenvalues in the order of the delay cells (D11_1, D11_2, ..., D11_P) to have a delay time twice that of the previous delay cells (D11_1, D11_2, ..., D11_P), each delay cell (D11_1) , D11_2, …, D11_P) correspond to a kind of binary place value. Depending on the characteristics of these delay cells (D11_1, D11_2, ..., D11_P), it is possible to set the output of the second delayer (11b) to have an inverted value of the output of the first delayer (11a).

In addition, when all of the P delay cells (D11_1, D11_2, ..., D11_P) are set by the control signal (Sig(I)) input to the first delayer (11a) to have unique values, the P delay cells (D11_1) , D11_2, ..., D11_P) It is preferable that the sum of all eigenvalues is smaller than the half cycle of the output of the first delay 11a and larger than the half cycle of the output of the 1-1 clock signal generator 14a. When the sensor signal digital conversion device 100 is integrated and implemented on a semiconductor chip by setting these eigenvalues, it is robust to the temperature of the semiconductor manufacturing process and the operating temperature and voltage of the sensor signal digital conversion device 100. We can respond.

For reference, the characteristics of the P delay cells (D11_1, D11_2, ..., D11_P) included in the second delay (11b) to the sixth delay (11f) are the P delay cells of the first delay (11a). Same as (D11_1, D11_2, …, D11_P). That is, the first delayers 11a to 6th delayers 11f have the same configuration.

Specifically, the second delayer 11b includes P delay cells (D11_1, D11_2, ..., D11_P) connected in series in a chain structure and delaying the input data signal by the delay time and outputting the oscillator signal. Among the P delay cells (D11_1, D11_2, ..., D11_P), the frontmost delay cell (D11_1) receives the data signal.

The first flip-flop 12 receives the output of the first delay 11a as a data signal and the output of the second delay 11b as a clock signal.

The first counter 13 receives the oscillator signal as a clock signal and counts the output of the first flip-flop 12 as a data signal. In addition, the output of the first counter 13 is input as the control signal of the second delayer 11b, and the P delays included in the second delayer 11b are calculated by the control signal of the second delayer 11b. The delay time for each cell (D11_1, D11_2, ..., D11_P) is set. For reference, due to the feedback effect of the first counter 13, the second delayer 11b inverts the output of the first delayer 11a and outputs it.

The third delay unit 11c includes P delay cells D11_1, D11_2, ..., D11_P, which are connected in series in a chain structure and each delay the input data signal by the delay time and output it. In addition, the third delay 11c receives as a control signal a signal obtained by dividing the output of the first counter 13 by N by the first divider 15a, and Among the delay cells (D11_1, D11_2, ..., D11_P), the frontmost delay cell (D11_1) receives the output of the first flip-flop 12 as a data signal. In addition, the delay time of each of the P delay cells (D11_1, D11_2, ..., D11_P) included in the third delay device 11c is set by the control signal of the third delay device 11c. Additionally, N is a natural number of 2 or more. However, it is preferable that N is 2.

The 1-1 clock signal generator 14a generates the 1-1 clock signal using the output of the first flip-flop 12 and the output of the third delay 11c. The 1-1st to 1-4th clock signal generators 14a, 14b, 14c, and 14d calculate and output the exclusive OR of two inputs. Accordingly, when N is 2, the 1-1 clock signal is twice faster than the output frequency of the first delayer 11a and is a signal shifted by 1/4 cycle of the output of the first delayer 11a. It is output.

Through this process, the 1-4th clock signal generator 14d outputs the 1-4th clock signal with a frequency that is 2 ⁵ times the output of the first flip-flop 12. In addition, the 1-4th clock signal is used as the first clock signal in other blocks.

The fourth delayers 11d to 6th delayers 11f also have P delay cells (D11_1, D11_2, ..., D11_P) connected in series in a chain structure and each delaying the input data signal by the delay time and outputting it. Includes. However, the fourth delayer (11d) receives a signal obtained by dividing the output of the first divider (15a) by N by the second divider (15b) as the control signal, and uses the data signal as the 1-1 clock. The output of the signal generator 14a is received. In addition, the fifth delay 11e receives a signal obtained by dividing the output of the second divider 15b by N by the third divider 15c as the control signal, and uses the data signal to generate a 1-2 clock signal. The output of the signal generator 14b is received. In addition, the sixth delay (11f) receives a signal obtained by dividing the output of the third divider (15c) by N by the fourth divider (15d) as the control signal, and generates 1-3 clock signals as the data signal. The output of the signal generator 14c is input.

Figure 4 shows a configuration diagram of the correction signal generator 20 according to one embodiment.

The correction signal generator 20 receives the output (Sig(OSC1)) of the first oscillator and the first clock signal, and generates a signal according to the error between the output (Sig(OSC1)) of the first oscillator and the first clock signal. , generate a correction signal to correct the error of the first time difference signal.

The correction signal generator 20 includes a fifth divider 21 that divides the output (Sig(OSC1)) of the first oscillator; a second counter (22) that receives the first clock signal as a clock signal and outputs a second counting value obtained by counting the output of the fifth divider (21); and a correction signal calculator 23 that calculates a correction signal using the ratio of the preset second value (V(2)) and the second counting value.

Specifically, the correction signal includes a first correction signal (C1), which is a first part, and a second correction signal (C2), which is a second part. That is, the first part is the real part of the correction signal, and the second part is the integer part of the correction signal.

If the first clock signal is a signal generated from the output (Sig(OSC1)) of the first oscillator, the ratio of the preset second value (V(2)) and the second counting value is '1', and the first part becomes '0' and the second part becomes '1'.

If the first clock signal is a signal generated from the output (Sig(OSC2)) of the second oscillator, since the second oscillator is integrated inside the semiconductor chip, it is affected by processes, etc. However, the output (Sig(OSC1)) of the first oscillator corresponding to the reference oscillator is used to generate a correction signal to correct the error of the output (Sig(OSC2)) of the second oscillator, and this is used for correction. .

If the output (Sig(OSC2)) frequency of the second oscillator is slower than the output (Sig(OSC1)) frequency of the first oscillator, the ratio of the preset second value (V(2)) and the second counting value is '1. ' It will be a larger value. For example, the correction signal becomes '1.05', the first part becomes '0.05', and the second part becomes '1'.

Figure 5 shows a configuration diagram of the reference time value calculation unit 30 according to one embodiment.

The reference time value calculation unit 30 uses the first clock signal and a signal obtained by inverting the first clock signal to calculate a first time value corresponding to the time value of the period of the first clock signal or the half-cycle of the first clock signal. Calculate the value (Sig(Tref1)).

The reference time value calculator 30 includes a 1-1 time value calculator 31, a 1-2 time value calculator 32, and a first time value calculator 33.

Figure 6 shows a configuration diagram of the 1-1 time value calculator 31 according to an embodiment.

The 1-1 time value calculator 31 includes L delay cells (D31_1, D31_2, ..., D31_L) connected in series in a chain structure and each delaying the input data signal by the delay time and outputting it. In addition, it is desirable that the delay times of the L delay cells (D31_1, D31_2, ..., D31_L) are all the same. L is a natural number greater than or equal to 5.

In addition, the 1-1 time value calculator 31 is activated after the first clock signal, which is the data signal of the frontmost delay cell (D31_1) among the L delay cells (D31_1, D31_2, ..., D31_L), is activated. The number of cells to which the first clock signal is transmitted among L delay cells (D31_1, D31_2, ..., D31_L) at either the rising edge or the falling edge of the inverted signal of the first clock signal. Using , the 1-1 time value is calculated. To this end, a latch and adder 311 that latches one of the rising edge or falling edge of the inverted signal of the first clock signal, receives the output value of each delay cell (D31_1, D31_2, ..., D31_L) and adds them. 1-1 It needs to be provided in the time value calculator 31.

For example, let L be 5. After the first clock signal goes from a low state to a high state, at the point of the rising edge of the inverted signal of the first clock signal, the cell to which the first clock signal is transmitted among the L delay cells (D31_1, D31_2, ..., D31_L) If the number is 3, the input of the latch and adder 311 is '11100', and if the delay time of each cell (D31_1, D31_2, ..., D31_L) is 50 ps, the second signal corresponding to the half cycle of the first clock signal 1-1 The time value is 150ps.

The 1-2 time value calculator 32 also has the same structure as the 1-1 time value calculator 31. That is, the 1-2 time value calculator 32 includes L delay cells connected in series in a chain structure and each delaying the input data signal by the delay time and outputting it. In addition, the 1-2 time value calculator 32 generates the rising edge or falling edge of the first clock signal after the inverted signal of the first clock signal, which is the data signal of the frontmost delay cell among the L delay cells, is activated. At one point, the 1-2 time value is calculated using the number of cells in which the inverted signal of the first clock signal is transmitted among the L delay cells.

The first time value calculator 33 calculates the first time value (Sig(Tref1)) using the 1-1 time value and the 1-2 time value. For example, the first time value (Sig(Tref1)) may be calculated as the average of the 1-1 time value and the 1-2 time value. By calculating the first time value (Sig(Tref1)) as the average of the 1-1 time value and the 1-2 time value, the half-cycle or period of the first clock signal can be measured more accurately.

7 to 9 are a configuration diagram of a first start-stop value generation unit 40 according to an embodiment, a configuration diagram of a second start-stop value generation unit 50 according to an embodiment, and a first The output timing diagram of the start-stop value generator 40 and the second start-stop value generator 50 is shown.

The first start-stop value generation unit 40 and the second start-stop value generation unit 50 will be described with reference to FIGS. 7 to 9.

The first start-stop value generator 40 generates a first clock signal or a first clock signal between a start signal (Sig (Start)) and a stop signal (Sig (Stop)) input from at least one sensor. The first start-stop value is calculated by counting using the inverted signal. The first start-stop value is the time from the first edge after the start signal (Sig(Start)) is input to the second edge before the stop signal (Sig(Stop)) is input. The first edge and the second edge are respectively a rising edge or a falling edge of the first clock signal; Or, the rising edge or falling edge of the inverted signal of the first clock signal. Specifically, the first edge is the rising edge or falling edge of the first clock signal output for the first time after the start signal (Sig(Start)) is input; Or, the rising edge or falling edge of the inverted signal of the first clock signal; and the second edge is the rising edge or falling edge of the first clock signal output immediately before the stop signal (Sig(Stop)) is input; Or, the rising edge or falling edge of the inverted signal of the first clock signal. That is, the first edge is the first edge output after the start signal (Sig(Start)) is input, and the second edge is the edge output just before the stop signal (Sig(Stop)) is input.

The first start-stop value generator 40 includes a 1-1 start-stop value counter 41, a 1-2 start-stop value counter 42, and a first stop-stop value calculator 43. ) and consists of

The 1-1 start-stop value counter 41 counts between the start signal (Sig (Start)) and the stop signal (Sig (Stop)) using the first clock signal, and calculates the 1-1 start-stop value Calculate . The 1-2 start-stop value counter 42 counts between the start signal (Sig (Start)) and the stop signal (Sig (Stop)) using the inverted signal of the first clock signal, Calculate the start stop value. The first start-stop value calculator 43 adds up the 1-1 start stop value and the 1-2 start stop value, but the 1-1 start stop value and the 1-2 start stop value overlap. The section is included only once, and the first stud-stop value is calculated.

The second start-stop value generator 50 generates a 2-1 time value from the time the start signal (Sig(Start)) is input until before the first edge and the stop signal (Sig(Stop)) from the second edge. ), the 2-2 time value is calculated, and the second start-stop value is calculated by adding the 2-1 time value and the 2-2 time value.

The second start-stop value generator 50 includes a 2-1 time value calculator 51, a 2-2 preliminary time value calculator 52, a 2-2 time value calculator 53, and It includes a second start-stop value calculator 54. In addition, the 2-1 time value calculator 51 and the 2-2 preliminary time value calculator 52 have a similar structure to the 1-1 time value calculator 31 described above.

Specifically, the 2-1 time value calculator 51 includes S delay cells connected in series in a chain structure and each delaying the input data signal by the delay time and outputting it. After the start signal (Sig (Start)) is activated as the data signal of the frontmost delay cell among the S delay cells of the 2-1 time value calculator 51, the first clock signal or the inversion of the first clock signal The 2-1 time value is calculated using the number of cells in which the first clock signal or the inverted signal of the first clock signal is transmitted among the S delay cells at one of the rising edge or the falling edge of the signal. That is, the 2-1 time value calculator 51 uses a start signal (Sig(Start)) as the data signal of the frontmost delay cell among the S delay cells of the 2-1 time value calculator 51. Calculate the time from activation to the first edge. At this time, S is a natural number of 5 or more, and all S delay cells included in the 2-1 time value calculator 51 have the same delay time.

The 2-2 preliminary time value calculator 52 includes S delay cells connected in series in a chain structure and each delaying the input data signal by the delay time and outputting it. After the stop signal (Sig (Stop)) is activated as the data signal of the frontmost delay cell among the S delay cells of the 2-2 preliminary time value calculator 52, the first clock signal or the first clock signal The 2-2 preliminary time value is calculated using the number of cells to which the first clock signal or the inverted signal of the first clock signal is transmitted among the S delay cells at one of the rising edge or the falling edge of the inverted signal. . All of the S delay cells included in the 2-2 preliminary time value calculator 52 have the same delay time.

The 2-2 time value calculator 53 subtracts the 2-2 preliminary time value from the first time value (Sig(Tref1)) to calculate the 2-2 time value.

In addition, the second start-stop value calculator 54 adds the 2-1 time value and the 2-2 time value to calculate the second start-stop value.

The second start-stop value generator 50 can calculate the second start-stop value, which is a fine part of the entire first time difference signal, so that the sensor signal digital conversion device 100 can convert the start signal and the start signal with high resolution. The time difference between stop signals can be output.

The normalization unit 60 calculates a second start-stop normalization value using the ratio of the second start-stop value and the first time value (Sig(Tref1)). That is, the normalization unit 60 divides the second start-stop value by the first time value (Sig(Tref1)) to calculate the second start-stop normalization value. Through normalization by the normalization unit 60, the second start-stop value is a value corresponding to the first start-stop value calculated as a number by counting using the first clock signal or the inverted signal of the first clock signal. will be converted. For example, if the second start-stop value is 1 ns and the first time value (Sig(Tref1)) is 10 ns, the second start-stop normalization value becomes '0.1', corresponding to the first start-stop value. do.

The time difference generator 70 receives a first clock signal, a start signal (Sig(Start)), and a stop signal (Sig(Stop)), and generates a start signal (Sig(Start)) and a stop signal (Sig(Stop)). )) generates a first time difference signal, which is the time difference between.

Specifically, the time difference generator 70 receives the first start-stop value and the second start-stop normalization value and generates a first time difference signal. That is, the time difference generator 70 generates a first time difference signal by adding the first start-stop value and the second start-stop normalization value.

The correction time difference generator 80 receives a correction signal and a first time difference signal and generates a second time difference signal by correcting the first time difference signal. That is, since the first time difference signal is a signal calculated from the first clock signal, errors due to the semiconductor process may be included, so it is a correction signal that corresponds to the output (Sig(OSC1)) of the first oscillator, which is an absolute clock signal. The second time difference signal is generated by .

Specifically, the correction time difference generator 80 adds the first time difference signal multiplied by the first correction signal C1 and the first time difference signal plus the second correction signal C2. Thus, a second time difference signal is generated. That is, this second time difference signal is output as the time difference between the final start signal (Sig(Start)) and the stop signal (Sig(Stop)).

The correction time difference generator 80 generates an amplifier for generating a value obtained by multiplying the first time difference signal by the first correction signal C1, and the output of the amplifier and a second correction signal C2 to the first time difference signal. It may be configured to include an adder for summing the added values.

Below, a method for digitally converting a sensor signal according to an embodiment will be described. The method of digitally converting a sensor signal according to an embodiment uses the device 100 for digitally converting a sensor signal according to the above-described embodiment. Therefore, even without separate explanation, the digital conversion method of a sensor signal according to an embodiment ( Of course, it includes all the features of 100).

A method of digitally converting a sensor signal according to an embodiment includes a clock signal generation step, a correction signal generation step, a reference time value calculation step, a first start-stop value generation step, a second start-stop value generation step, a normalization step, It includes a time difference generation step and a correction time difference generation step.

In the clock signal generation step, the frequency of the input oscillator signal is multiplied to generate a first clock signal. In addition, in the clock signal generation step, one of the output of the first oscillator (Sig(OSC1)) and the output of the second oscillator (Sig(OSC2)) can be input as an oscillator signal.

Specifically, the clock signal generation step includes a first to sixth delay step, a flip-flop step, a first counting step, a 1-1 to 1-4 clock signal step, and a first to fourth dividing step. do.

In the first delay stage, P delay cells (D11_1, D11_2, ..., D11_P) connected in series in a chain structure and each delaying and outputting the input data signal by the delay time are used, and the oscillator signal of the first oscillator is used. The frontmost delay cell (D11_1) among the P delay cells (D11_1, D11_2, …, D11_P) receives one of the output (Sig(OSC1)) and the output (Sig(OSC2)) of the second oscillator as a data signal. delay.

Additionally, the delay time of each of the P delay cells (D11_1, D11_2, ..., D11_P) used in the first delay step includes the sum of the 1-1 delay time and the 1-2 delay time. Specifically, the 1-1 delay times of each of the P delay cells (D11_1, D11_2, ..., D11_P) all have the same value. In addition, in the first delay stage, the control signal of the first delay stage is input, and each of the P delay cells (D11_1, D11_2, ..., D11_P) is controlled by the control signal (Sig(I)) of the first delay stage. 1-2 The delay time can be set to '0' or to have a unique value for each of the P delay cells (D11_1, D11_2, ..., D11_P). The eigenvalue of each of the P delay cells (D11_1, D11_2, ..., D11_P) gradually increases as the position of the corresponding delay cells (D11_1, D11_2, ..., D11_P) moves toward the rear end of the chain structure. Here, P is a natural number of 3 or more.

In addition, the second delay stage uses P delay cells (D11_1, D11_2, ..., D11_P) that are connected in series in a chain structure and output the input data signal by delaying it respectively by the delay time, and transmits the oscillator signal to P number of delay cells. Among the delay cells (D11_1, D11_2, ..., D11_P), the frontmost delay cell (D11_1) receives the data signal and delays it.

In addition, the flip-flop stage uses the first flip-flop 12, receives the output of the first delay stage as a data signal of the first flip-flop 12, and receives the output of the first delay stage as a clock signal of the first flip-flop 12. The output of the second delay stage is received and output.

In the first counting step, the oscillator signal is input as a clock signal, and the output of the first flip-flop 12 is input as a data signal, counted, and output.

In addition, the output of the first counting step is input as the control signal of the second delay step, and by the control signal of the second delay step, P delay cells (D11_1, D11_2, ..., D11_P) used in the second delay step are Each delay time is set.

In the third delay stage, P delay cells (D11_1, D11_2, ..., D11_P) connected in series in a chain structure and each delaying the input data signal by the delay time and outputting it are used, and a first flip-flop 12 is used. The frontmost delay cell (D11_1) among the P delay cells (D11_1, D11_2, ..., D11_P) receives the output as a data signal and delays it. In addition, the signal obtained by dividing the output of the first counting step by N is input as the control signal of the third delay step, and the P delay cells (D11_1, D11_2, …, D11_P) Each delay time is set. Here, N is a natural number of 2 or more.

The 1-1 clock signal generation step generates the 1-1 clock signal using the output of the first flip-flop 12 and the output of the third delay step.

For reference, in the 1-1st to 1-4th clock signal generation steps, the exclusive OR of the two inputs is calculated and output. Accordingly, when N is 2, the 1-1 clock signal is twice faster than the output frequency of the first delay stage and is output as a signal shifted by 1/4 cycle of the output of the first delay stage.

Through this process, in the 1-4th clock signal generation step, the 1-4th clock signal with ^a frequency equal to the output of the first flip-flop 12 is output. In addition, the 1-4th clock signal is used as the first clock signal in other blocks.

The fourth to sixth delay stages also include P delay cells (D11_1, D11_2, ..., D11_P) connected in series in a chain structure, each delaying the input data signal by the delay time and outputting it. However, in the fourth delay step, a signal obtained by dividing the output of the first dividing step by N by the second dividing step is input as a control signal, and the output of the 1-1 clock signal generation step is received as a data signal. In addition, the fifth delay stage receives a signal obtained by dividing the output of the second dividing stage by N by the third dividing stage as the control signal, and receives the output of the 1-2 clock signal generation stage as the data signal. In addition, the sixth delay stage receives a signal obtained by dividing the output of the 1-3 dividing stage by N by the fourth dividing stage as the control signal, and inputs the output of the 1-3 clock signal generation stage as the data signal. Receive.

The correction signal generation step receives the output (Sig(OSC1)) of the first oscillator and the first clock signal, and generates a first signal according to the error between the output (Sig(OSC1)) of the first oscillator and the first clock signal. Generates a correction signal to correct errors in the time difference signal.

Specifically, the correction signal generation step includes a fifth dividing step of dividing the output (Sig(OSC1)) of the first oscillator; a second counting step of receiving the first clock signal as a clock signal and outputting a second counting value obtained by counting the output of the fifth dividing step; and a correction signal calculation step of calculating a correction signal using the ratio of the preset second value (V(2)) and the second counting value.

The reference time value calculation step is to calculate a first time value (Sig), which is a value corresponding to the time value of the period of the first clock signal or the half period of the first clock signal, using the first clock signal and the inverted signal of the first clock signal. (Tref1)).

Specifically, the reference time value calculation step uses L delay cells (D31_1, D31_2, ..., D31_L) that are connected in series in a chain structure and output the input data signal with a delay corresponding to the delay time, respectively. After the first clock signal, which is the data signal of the frontmost delay cell (D31_L) among the cells (D31_1, D31_2, ..., D31_L), is activated, at one of the rising edge or falling edge of the inverted signal of the first clock signal A 1-1 time value calculation step of calculating a 1-1 time value using the number of cells to which the first clock signal is transmitted among the L delay cells (D31_1, D31_2, ..., D31_L); Alternatively, L delay cells connected in series in a chain structure, each delaying and outputting the input data signal by the delay time, are used, but the first clock signal, which is the data signal of the frontmost delay cell among the L delay cells, is inverted. After the signal is activated, at one point of the rising edge or the falling edge of the first clock signal, using the number of cells to which the inverted signal of the first clock signal is transmitted among the L delay cells, a 1-2 time value A 1-2 time value calculation step of calculating; Contains at least one of Here, L is a natural number of 5 or more.

In addition, the reference time value calculation step further includes a first time value calculation step of calculating a first time value (Sig(Tref1)) using the 1-1 time value and the 1-2 time value. .

The first start-stop value generation step is to generate a first clock signal or an inverted signal of the first clock signal between a start signal (Sig (Start)) and a stop signal (Sig (Stop)) input from at least one sensor. The first start-stop value is calculated by counting. Here, the first edge is the rising edge or falling edge of the first clock signal output for the first time after the start signal (Sig(Start)) is input; Or, the rising edge or falling edge of the inverted signal of the first clock signal. In addition, the second edge is the rising edge or falling edge of the first clock signal output immediately before the stop signal (Sig(Stop)) is input; Or, the rising edge or falling edge of the inverted signal of the first clock signal.

The first start-stop value generating step includes a 1-1 start-stop value counting step, a 1-2 start-stop value counting step, and a first stop-stop value calculating step.

The 1-1 start-stop value counting step calculates the 1-1 start-stop value by counting between the start signal (Sig (Start)) and the stop signal (Sig (Stop)) using the first clock signal. do. The 1-2 start-stop value counting step counts between the start signal (Sig (Start)) and the stop signal (Sig (Stop)) using the inverted signal of the first clock signal, Calculate the value. In the first start-stop value calculation step, the 1-1 start stop value and the 1-2 start stop value are added, and the section where the 1-1 start stop value and the 1-2 start stop value overlap is By including only one time, the first stud-stop value is calculated.

The second start-stop value generation step is a 2-1 time value from after the start signal (Sig(Start)) is input to before the first edge and from the second edge to the stop signal (Sig(Stop)). A 2-2 time value is calculated, and a second start-stop value is calculated by adding the 2-1 time value and the 2-2 time value.

Specifically, the second start-stop value generation step includes a 2-1 time value calculation step, a 2-2 preliminary time value calculation step, a 2-2 time value calculation step, and a second start-stop value calculation step. Includes.

In the 2-1 time value calculation step, S delay cells connected in series in a chain structure and outputting the input data signal by delaying each delay time are used, and the data of the frontmost delay cell among the S delay cells is used. After the start signal (Sig(Start)) is activated as a signal, using the number of cells to which the first clock signal or the inverted signal of the first clock signal is transmitted among the S delay cells until the first edge, 2-1 time Calculate the value. Additionally, S is preferably a natural number of 5 or more.

In the 2-2 preliminary time value calculation step, S delay cells connected in series in a chain structure and each delaying and outputting the input data signal by the delay time are used, and the frontmost delay cell among the S delay cells is used. After the stop signal (Sig(Stop)) is activated as a data signal, the first clock signal or the first clock signal among S delay cells is activated at one of the rising edge or falling edge of the first clock signal or the inverted signal of the first clock signal. The 2-2 preliminary time value is calculated using the number of cells to which the inverted signal of 1 clock signal is transmitted.

Additionally, in the 2-2 time value calculation step, the 2-2 time value is calculated by subtracting the 2-2 preliminary time value from the first time value.

In addition, in the second start-stop value calculation step, the 2-1 time value and the 2-2 time value are added to calculate the second start-stop value.

In the normalization step, the second start-stop normalization value is calculated using the ratio of the second start-stop value and the first time value.

In the time difference generation step, a start signal (Sig(Start)) and a stop signal (Sig(Stop)) are input, and the time difference between the start signal (Sig(Start)) and the stop signal (Sig(Stop)) is generated. 1 Generate a time difference signal.

Specifically, the time difference generating step receives the first start-stop value and the second start-stop normalization value and generates a first time difference signal.

In the correction time difference generation step, a correction signal and a first time difference signal are input, and a second time difference signal is generated by correcting the first time difference signal.

Specifically, the correction signal includes a first correction signal C1, which is the first part of the correction signal, and a second correction signal C2, which is the second part of the correction signal.

In addition, the correction time difference generating step is to add the first time difference signal multiplied by the first correction signal C1 and the first time difference signal plus the second correction signal C2 to obtain a second Generates a time difference signal.

As described above, according to the sensor signal digital conversion device 100 and its conversion method, when integrated into a semiconductor chip, it can respond robustly to the manufacturing process, usage temperature, and voltage, etc., and can generate a start signal (Sig (Start)) with high resolution. ) and the stop signal (Sig(Stop)) can be output.

100: Digital conversion device of sensor signal
10: clock signal generator 20: correction signal generator
30: Reference time value calculation unit 40: First start-stop value generation unit
50: second start-stop value generation unit 60: normalization unit
70: Time difference generator 80: Correction time difference generator
11a: first delay unit 11b: second delay unit
11c: third delay period 11d: fourth delay period
11e: 5th delay period 11f: 6th delay period
12: first flip-flop 13: first counter
14a: 1-1 clock signal generator 14b: 1-2 clock signal generator
14c: 1st-3rd clock signal generator 14d: 1st-4th clock signal generator
15a: first divider cycle 15b: second divider cycle
15c: 3rd division cycle 15d: 4th division cycle
21: 5th minute cycle 22: 2nd counter
23: Correction signal calculator 31: 1-1 time value calculator
32: 1st-2nd time value calculator 33: 1st time value calculator
41: 1-1 start-stop value counter 42: 1-2 start-stop value counter
43: 1st stud-stop value calculator 51: 2-1 time value calculator
52: 2-2 preliminary time value calculator 53: 2-2 time value calculator
54: second start-stop value calculator

Claims (30)

In a digital conversion device that converts the time difference between a start signal and a stop signal input from at least one sensor into a digital value,
a clock signal generator that generates a first clock signal by multiplying the frequency of an oscillator signal output from one of the output of the first oscillator and the output of the second oscillator;
a time difference generator that receives the start signal and the stop signal and generates a first time difference signal that is a time difference between the start signal and the stop signal;
Receives the output of the first oscillator and the first clock signal, and generates a correction signal to correct the error of the first time difference signal according to the error between the output of the first oscillator and the first clock signal. a correction signal generating unit; and
A correction time difference generator configured to receive the correction signal and the first time difference signal and generate a second time difference signal by correcting the first time difference signal,
The correction signal is,
A first correction signal that is a first portion of the correction signal and a second correction signal that is a second portion of the correction signal,
The correction time difference generator,
A digital conversion device that generates the second time difference signal by adding a value obtained by multiplying the first time difference signal by the first correction signal and a value obtained by adding the second correction signal to the first time difference signal. . delete delete According to paragraph 1,
The correction signal generator,
a fifth divider that divides the output of the first oscillator;
a second counter that receives the first clock signal as a clock signal and outputs a second counting value obtained by counting the output of the fifth divider; and
A digital conversion device comprising: a correction signal calculator that calculates the correction signal using a ratio of a preset second value and the second counting value. According to paragraph 1,
The digital conversion device,
A reference for calculating a first time value, which is a value corresponding to a time value of a period of the first clock signal or a half period of the first clock signal, using the first clock signal and a signal obtained by inverting the first clock signal. A digital conversion device further comprising a time value calculation unit. According to clause 5,
The reference time value calculation unit,
It includes L delay cells connected in series in a chain structure, each delaying the input data signal by the delay time and outputting it, wherein the first clock signal, which is the data signal of the frontmost delay cell among the L delay cells, is activated. Afterwards, the 1-1 time value is calculated using the number of cells in which the first clock signal is transmitted among the L delay cells at one of the rising edge or the falling edge of the inverted signal of the first clock signal. 1-1 time value calculator; or,
It includes L delay cells connected in series in a chain structure, each delaying the input data signal by the delay time and outputting it, and an inversion signal of the first clock signal, which is the data signal of the frontmost delay cell among the L delay cells. After is activated, at one point of the rising edge or the falling edge of the first clock signal, using the number of cells in which the inverted signal of the first clock signal is transmitted among the L delay cells, 1-2 times A first-second time value calculator that calculates a value; Include at least one of:
A digital conversion device, wherein L is a natural number of 5 or more. According to clause 6,
The reference time value calculation unit,
A digital conversion device further comprising a first time value calculator that calculates the first time value using the 1-1 time value and the 1-2 time value. According to clause 5,
The digital conversion device,
It further includes a first start-stop value generator that calculates a first start-stop value by counting between the start signal and the stop signal using the first clock signal or an inverted signal of the first clock signal. However,
The first start-stop value is,
It is the time from the first edge after the start signal is input to the second edge before the stop signal is input,
The first edge is,
a rising edge or falling edge of the first clock signal output for the first time after the start signal is input; Or, the rising edge or falling edge of the inverted signal of the first clock signal;
The second edge is,
a rising edge or falling edge of the first clock signal output immediately before the stop signal is input; Or, a rising edge or falling edge of an inverted signal of the first clock signal; a digital conversion device. According to clause 8,
The digital conversion device,
A 2-1 time value from the start signal input to before the first edge and a 2-2 time value from the second edge to the stop signal are calculated, and the 2-1 time value and A digital conversion device further comprising a second start-stop value generator that calculates a second start-stop value by adding up the 2-2 time values. According to clause 9,
The second start-stop value generator,
It includes S delay cells connected in series in a chain structure, each delaying the input data signal by the delay time and outputting it, and after the start signal is activated with the data signal of the frontmost delay cell among the S delay cells, The number of cells to which the first clock signal or the inverted signal of the first clock signal is transmitted among S delay cells at one of the rising edge or falling edge of the first clock signal or the inverted signal of the first clock signal a 2-1 time value calculator that calculates the 2-1 time value using;
It includes S delay cells connected in series in a chain structure, each delaying the input data signal by the delay time and outputting it, and after the stop signal is activated with the data signal of the frontmost delay cell among the S delay cells, The number of cells to which the first clock signal or the inverted signal of the first clock signal is transmitted among S delay cells at one of the rising edge or falling edge of the first clock signal or the inverted signal of the first clock signal a 2-2 preliminary time value calculator that calculates a 2-2 preliminary time value using; and
A 2-2 time value calculator that calculates the 2-2 time value by subtracting the 2-2 preliminary time value from the first time value,
A digital conversion device, wherein S is a natural number of 5 or more. According to clause 9,
The digital conversion device,
It further includes a normalization unit that calculates a second start-stop normalization value using the ratio of the second start-stop value and the first time value,
The time difference generator,
A digital conversion device that receives the first start-stop value and the second start-stop normalization value and generates the first time difference signal. In a digital conversion device that converts the time difference between a start signal and a stop signal input from at least one sensor into a digital value,
a clock signal generator that generates a first clock signal by multiplying the frequency of an oscillator signal output from one of the output of the first oscillator and the output of the second oscillator;
a time difference generator that receives the start signal and the stop signal and generates a first time difference signal that is a time difference between the start signal and the stop signal;
Receives the output of the first oscillator and the first clock signal, and generates a correction signal to correct the error of the first time difference signal according to the error between the output of the first oscillator and the first clock signal. a correction signal generating unit; and
A correction time difference generator configured to receive the correction signal and the first time difference signal and generate a second time difference signal by correcting the first time difference signal,
The clock signal generator,
A first delay cell comprising P delay cells connected in series in a chain structure and each delaying the input data signal by the delay time to output the oscillator signal, the frontmost delay cell of the P delay cells receiving the oscillator signal as a data signal. delay period;
A second cell comprising P delay cells connected in series in a chain structure to output an input data signal after delaying each delay time, wherein the frontmost delay cell of the P delay cells receives the oscillator signal as a data signal. delay period;
a first flip-flop that receives the output of the first delayer as a data signal and the output of the second delayer as a clock signal; and
A first counter that receives the oscillator signal as a clock signal and counts the output of the first flip-flop as a data signal,
The output of the first counter is input as a control signal of the second delayer,
The delay time of each of the P delay cells included in the second delay is set by the control signal of the second delay,
A digital conversion device, wherein P is a natural number of 3 or more. According to clause 12,
The delay time of each of the P delay cells included in the first delayer is,
Includes the sum of the 1-1 delay time and the 1-2 delay time,
The 1-1 delay times of each of the P delay cells all have the same value,
The 1-2 delay time of each of the P delay cells can be set by a control signal input to the first delay to have a unique value of '0' or each of the P delay cells, a digital conversion device. . According to clause 13,
The unique value of each of the P delay cells is,
A digital conversion device in which the position of the corresponding delay cell gradually increases toward the rear of the chain structure. According to clause 12,
The clock signal generator,
It includes P delay cells connected in series in a chain structure, each delaying the input data signal by the delay time, and outputting the output, and the frontmost delay cell among the P delay cells converts the output of the first flip-flop into a data signal. a third delay receiving input; and
It further includes a 1-1 clock signal generator that generates a 1-1 clock signal using the output of the first flip-flop and the output of the third delay,
The delay time of each of the P delay cells included in the third delay is set by a signal obtained by dividing the output of the first counter by N,
A digital conversion device, wherein N is a natural number of 2 or more. In a digital conversion method for converting the time difference between a start signal and a stop signal input from at least one sensor into a digital value,
A clock signal generation step of generating a first clock signal by multiplying the frequency of an oscillator signal output from one of the output of the first oscillator and the output of the second oscillator;
A time difference generating step of receiving the start signal and the stop signal and generating a first time difference signal that is a time difference between the start signal and the stop signal;
Receives the output of the first oscillator and the first clock signal, and generates a correction signal to correct the error of the first time difference signal according to the error between the output of the first oscillator and the first clock signal. A correction signal generation step; and
A correction time difference generating step of receiving the correction signal and the first time difference signal and generating a second time difference signal by correcting the first time difference signal,
The correction signal is,
A first correction signal that is a first portion of the correction signal and a second correction signal that is a second portion of the correction signal,
The correction time difference generation step is,
A digital conversion method for generating the second time difference signal by adding a value obtained by multiplying the first time difference signal by the first correction signal and a value obtained by adding the second correction signal to the first time difference signal. . delete delete According to clause 16,
The correction signal generation step is,
A fifth dividing step of dividing the output of the first oscillator;
a second counting step of receiving the first clock signal as a clock signal and outputting a second counting value obtained by counting the output of the fifth dividing step; and
A correction signal calculation step of calculating the correction signal using a ratio of a preset second value and the second counting value. According to clause 16,
The digital conversion method is,
A reference for calculating a first time value, which is a value corresponding to a time value of a period of the first clock signal or a half period of the first clock signal, using the first clock signal and a signal obtained by inverting the first clock signal. A digital conversion method further comprising a time value calculation step. According to clause 20,
The reference time value calculation step is,
L delay cells are connected in series in a chain structure and each delays and outputs an input data signal by the delay time, and the first clock signal, which is the data signal of the frontmost delay cell among the L delay cells, is activated. Afterwards, the 1-1 time value is calculated using the number of cells in which the first clock signal is transmitted among the L delay cells at one of the rising edge or the falling edge of the inverted signal of the first clock signal. 1-1 time value calculation step; or,
L delay cells are connected in series in a chain structure, each delaying the input data signal by the delay time and outputting it. The inverted signal of the first clock signal is the data signal of the frontmost delay cell among the L delay cells. After is activated, at one point of the rising edge or the falling edge of the first clock signal, using the number of cells in which the inverted signal of the first clock signal is transmitted among the L delay cells, 1-2 times A 1-2 time value calculation step of calculating a value; Include at least one of:
A digital conversion method, wherein L is a natural number of 5 or more. According to clause 21,
The reference time value calculation step is,
A digital conversion method further comprising a first time value calculation step of calculating the first time value using the 1-1 time value and the 1-2 time value. According to clause 21,
The digital conversion method is,
A first start-stop value generating step of calculating a first start-stop value by counting between the start signal and the stop signal using the first clock signal or an inverted signal of the first clock signal. However,
The first start-stop value is,
It is the time from the first edge after the start signal is input to the second edge before the stop signal is input,
The first edge is,
a rising edge or falling edge of the first clock signal output for the first time after the start signal is input; Or, the rising edge or falling edge of the inverted signal of the first clock signal;
The second edge is,
a rising edge or falling edge of the first clock signal output immediately before the stop signal is input; Or, a rising edge or falling edge of an inverted signal of the first clock signal; a digital conversion method. According to clause 23,
The digital conversion method is,
A 2-1 time value from the start signal input to before the first edge and a 2-2 time value from the second edge to the stop signal are calculated, and the 2-1 time value and A digital conversion method further comprising: calculating a second start-stop value by adding up the 2-2 time values. According to clause 24,
The second start-stop value generation step is,
S delay cells are connected in series in a chain structure, each delaying the input data signal by the delay time and outputting it. After the start signal is activated with the data signal of the frontmost delay cell among the S delay cells, Calculating the 2-1 time value by using the number of cells in which the first clock signal or an inverted signal of the first clock signal is transmitted among the S delay cells up to the first edge. step;
S delay cells are connected in series in a chain structure and each outputs an input data signal delayed by the delay time. After the stop signal is activated with the data signal of the frontmost delay cell among the S delay cells, The number of cells to which the first clock signal or the inverted signal of the first clock signal is transmitted among S delay cells at one of the rising edge or falling edge of the first clock signal or the inverted signal of the first clock signal A 2-2 preliminary time value calculating step of calculating a 2-2 preliminary time value using; and
A 2-2 time value calculation step of calculating the 2-2 time value by subtracting the 2-2 preliminary time value from the first time value,
A digital conversion method, wherein S is a natural number of 5 or more. According to clause 24,
The digital conversion method is,
It further includes a normalization step of calculating a second start-stop normalization value using the ratio of the second start-stop value and the first time value,
The time difference creation step is,
A digital conversion method that receives the first start-stop value and the second start-stop normalization value and generates the first time difference signal. In a digital conversion method for converting the time difference between a start signal and a stop signal input from at least one sensor into a digital value,
A clock signal generation step of generating a first clock signal by multiplying the frequency of an oscillator signal output from one of the output of the first oscillator and the output of the second oscillator;
A time difference generating step of receiving the start signal and the stop signal and generating a first time difference signal that is a time difference between the start signal and the stop signal;
Receives the output of the first oscillator and the first clock signal, and generates a correction signal to correct the error of the first time difference signal according to the error between the output of the first oscillator and the first clock signal. A correction signal generation step; and
A correction time difference generating step of receiving the correction signal and the first time difference signal and generating a second time difference signal by correcting the first time difference signal,
The clock signal generation step is,
P delay cells are connected in series in a chain structure, each delaying and outputting the input data signal by the delay time, and the frontmost delay cell among the P delay cells receives the oscillator signal as a data signal and delays it. a first delay step;
P delay cells are connected in series in a chain structure, each delaying and outputting the input data signal by the delay time, and the frontmost delay cell among the P delay cells receives the oscillator signal as a data signal and delays it. a second delay stage;
A flip that uses a first flip-flop, receives the output of the first delay stage as a data signal of the first flip-flop, and receives and outputs the output of the second delay stage as a clock signal of the first flip-flop. flop stage;
A first counting step of receiving the oscillator signal as a clock signal and counting the output of the first flip-flop as a data signal,
The output of the first counting step is input as a control signal of the second delay step,
The delay time of each of the P delay cells used in the second delay step is set by the control signal of the second delay step,
A digital conversion method, wherein P is a natural number of 3 or more. According to clause 27,
The delay time of each of the P delay cells used in the first delay step is,
Includes the sum of the 1-1 delay time and the 1-2 delay time,
The 1-1 delay times of each of the P delay cells all have the same value,
In the first delay step,
The control signal of the first delay step is input, and the 1-2 delay time of each of the P delay cells is set to '0' or a unique value of each of the P delay cells by the control signal of the first delay step. A digital conversion method that can be set to have a value. According to clause 28,
The unique value of each of the P delay cells is,
A digital conversion method in which the position of the corresponding delay cell gradually increases toward the rear of the chain structure. According to clause 27,
The clock signal generation step is,
P delay cells are connected in series in a chain structure, each delaying the input data signal by the delay time to output it, and the output of the first flip-flop is converted into a data signal by the frontmost delay cell among the P delay cells. a third delay stage that receives input and delays it; and
It further includes a 1-1 clock signal generation step of generating a 1-1 clock signal using the output of the first flip-flop and the output of the third delay stage,
In the third delay step,
A signal obtained by dividing the output of the first counting step by N is input as a control signal of the third delay step, and the delay of each of the P delay cells included in the third delay step is determined by the control signal of the third delay step. The time is set,
A digital conversion method, wherein N is a natural number of 2 or more.

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