KR102663653B1 - 비동기 파이프라인의 스테이지의 연산 속도 제어 - Google Patents

비동기 파이프라인의 스테이지의 연산 속도 제어 Download PDF

Info

Publication number
KR102663653B1
KR102663653B1 KR1020217018014A KR20217018014A KR102663653B1 KR 102663653 B1 KR102663653 B1 KR 102663653B1 KR 1020217018014 A KR1020217018014 A KR 1020217018014A KR 20217018014 A KR20217018014 A KR 20217018014A KR 102663653 B1 KR102663653 B1 KR 102663653B1
Authority
KR
South Korea
Prior art keywords
stage
stages
asynchronous pipeline
completion
speed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020217018014A
Other languages
English (en)
Korean (ko)
Other versions
KR20210074411A (ko
Inventor
그레그 사도우스키
존 카라마티아노스
쇼미트 엔. 다스
Original Assignee
어드밴스드 마이크로 디바이시즈, 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 어드밴스드 마이크로 디바이시즈, 인코포레이티드 filed Critical 어드밴스드 마이크로 디바이시즈, 인코포레이티드
Publication of KR20210074411A publication Critical patent/KR20210074411A/ko
Application granted granted Critical
Publication of KR102663653B1 publication Critical patent/KR102663653B1/ko
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3869Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3871Asynchronous instruction pipeline, e.g. using handshake signals between stages
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Image Processing (AREA)
  • Power Sources (AREA)
  • Information Transfer Systems (AREA)
  • Pipeline Systems (AREA)
KR1020217018014A 2016-07-21 2017-07-20 비동기 파이프라인의 스테이지의 연산 속도 제어 Active KR102663653B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US15/216,094 2016-07-21
US15/216,094 US10698692B2 (en) 2016-07-21 2016-07-21 Controlling the operating speed of stages of an asynchronous pipeline
PCT/US2017/042981 WO2018017785A2 (en) 2016-07-21 2017-07-20 Controlling the operating speed of stages of an asynchronous pipeline
KR1020197003111A KR102266303B1 (ko) 2016-07-21 2017-07-20 비동기 파이프라인의 스테이지의 연산 속도 제어

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
KR1020197003111A Division KR102266303B1 (ko) 2016-07-21 2017-07-20 비동기 파이프라인의 스테이지의 연산 속도 제어

Publications (2)

Publication Number Publication Date
KR20210074411A KR20210074411A (ko) 2021-06-21
KR102663653B1 true KR102663653B1 (ko) 2024-05-10

Family

ID=60988654

Family Applications (2)

Application Number Title Priority Date Filing Date
KR1020217018014A Active KR102663653B1 (ko) 2016-07-21 2017-07-20 비동기 파이프라인의 스테이지의 연산 속도 제어
KR1020197003111A Active KR102266303B1 (ko) 2016-07-21 2017-07-20 비동기 파이프라인의 스테이지의 연산 속도 제어

Family Applications After (1)

Application Number Title Priority Date Filing Date
KR1020197003111A Active KR102266303B1 (ko) 2016-07-21 2017-07-20 비동기 파이프라인의 스테이지의 연산 속도 제어

Country Status (6)

Country Link
US (2) US10698692B2 (https=)
EP (1) EP3488340B1 (https=)
JP (2) JP6893971B2 (https=)
KR (2) KR102663653B1 (https=)
CN (1) CN109478141B (https=)
WO (1) WO2018017785A2 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10503544B2 (en) * 2016-10-17 2019-12-10 Toyota Jidosha Kabushiki Kaisha Efficient mapping from task graphs to dynamic system platforms
KR102309429B1 (ko) * 2017-03-20 2021-10-07 현대자동차주식회사 차량 및 그 제어 방법
US10326452B2 (en) * 2017-09-23 2019-06-18 Eta Compute, Inc. Synchronizing a self-timed processor with an external event
US11334696B2 (en) * 2017-09-28 2022-05-17 Intel Corporation Systems and methods for dynamic voltage and frequency scaling in programmable logic devices
JP2020165713A (ja) * 2019-03-28 2020-10-08 株式会社デンソーテン 検査データ出力装置、表示システムおよび検査データ出力方法
US11467845B2 (en) * 2020-10-20 2022-10-11 Micron Technology, Inc. Asynchronous pipeline merging using long vector arbitration

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050210305A1 (en) * 2004-03-22 2005-09-22 Sharp Kabushiki Kaisha Data processor for controlling voltage supplied for processing
JP2006039754A (ja) * 2004-07-23 2006-02-09 Canon Inc 画像処理装置及びその方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04314161A (ja) * 1991-04-11 1992-11-05 Mitsubishi Electric Corp 情報処理装置
KR100239749B1 (ko) * 1997-04-11 2000-01-15 윤종용 그로스 테스트용 tft 소자 제조 방법 및 이를 형성한 액정 표시 장치 구조와 그로스 테스트 장치 및 방법
US6182233B1 (en) * 1998-11-20 2001-01-30 International Business Machines Corporation Interlocked pipelined CMOS
US6289465B1 (en) * 1999-01-11 2001-09-11 International Business Machines Corporation System and method for power optimization in parallel units
KR100729319B1 (ko) * 2000-04-25 2007-06-15 더 트러스티스 오브 컬럼비아 유니버시티 인 더 시티 오브 뉴욕 고용량 비동기 파이프라인 처리를 위한 회로 및 방법
US6369614B1 (en) 2000-05-25 2002-04-09 Sun Microsystems, Inc. Asynchronous completion prediction
US6590424B2 (en) * 2000-07-12 2003-07-08 The Trustees Of Columbia University In The City Of New York High-throughput asynchronous dynamic pipelines
US6502202B1 (en) 2000-10-06 2002-12-31 Elan Research Self-adjusting multi-speed pipeline
JP3884914B2 (ja) * 2001-01-30 2007-02-21 株式会社ルネサステクノロジ 半導体装置
EP1543390A2 (en) * 2002-09-20 2005-06-22 Koninklijke Philips Electronics N.V. Adaptive data processing scheme based on delay forecast
JP4261453B2 (ja) * 2004-09-30 2009-04-30 京セラミタ株式会社 メモリ制御装置
US8677103B1 (en) 2004-10-20 2014-03-18 Marvell Isreal (M.I.S.L) Ltd. Asynchronous pipelined data path with data transition
US8291256B2 (en) * 2006-02-03 2012-10-16 National University Corporation Kobe University Clock stop and restart control to pipelined arithmetic processing units processing plurality of macroblock data in image frame per frame processing period
GB2459652B (en) 2008-04-28 2010-09-22 Imagination Tech Ltd Controlling instruction scheduling based on the space in a trace buffer
JP5294449B2 (ja) * 2008-07-11 2013-09-18 国立大学法人 筑波大学 ネットワークシステムおよびネットワークシステムにおける電源制御方法
JP2010141641A (ja) * 2008-12-12 2010-06-24 Ricoh Co Ltd 半導体回路、半導体回路の出力バッファ波形調整方法
JP5720243B2 (ja) 2010-12-28 2015-05-20 富士通セミコンダクター株式会社 プロセッサ検証プログラム
US9117511B2 (en) * 2013-03-08 2015-08-25 Advanced Micro Devices, Inc. Control circuits for asynchronous circuits
US20150341032A1 (en) 2014-05-23 2015-11-26 Advanced Micro Devices, Inc. Locally asynchronous logic circuit and method therefor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050210305A1 (en) * 2004-03-22 2005-09-22 Sharp Kabushiki Kaisha Data processor for controlling voltage supplied for processing
JP2006039754A (ja) * 2004-07-23 2006-02-09 Canon Inc 画像処理装置及びその方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Vishal Gupta 외 1명. Energy Conservation in Asynchronous Systems using Self-Adaptive Fine-Grain Voltage Scaling. 2013년

Also Published As

Publication number Publication date
EP3488340A4 (en) 2020-08-19
EP3488340A2 (en) 2019-05-29
KR102266303B1 (ko) 2021-06-17
US10698692B2 (en) 2020-06-30
CN109478141B (zh) 2024-06-04
US20210089324A1 (en) 2021-03-25
JP7465848B2 (ja) 2024-04-11
CN109478141A (zh) 2019-03-15
KR20190022858A (ko) 2019-03-06
EP3488340B1 (en) 2023-09-06
JP6893971B2 (ja) 2021-06-23
KR20210074411A (ko) 2021-06-21
US20180024837A1 (en) 2018-01-25
US11842199B2 (en) 2023-12-12
JP2019521454A (ja) 2019-07-25
WO2018017785A2 (en) 2018-01-25
WO2018017785A3 (en) 2018-03-08
JP2021166053A (ja) 2021-10-14

Similar Documents

Publication Publication Date Title
KR102663653B1 (ko) 비동기 파이프라인의 스테이지의 연산 속도 제어
US6247134B1 (en) Method and system for pipe stage gating within an operating pipelined circuit for power savings
Trivedi et al. Design & analysis of 16 bit RISC processor using low power pipelining
JP6092649B2 (ja) 演算装置、アレイ型演算装置およびその制御方法、情報処理システム
US8701069B1 (en) Systems and methods for optimizing allocation of hardware resources to control logic in parallel pipelined hardware
US7958476B1 (en) Method for multi-cycle path and false path clock gating
US10659396B2 (en) Joining data within a reconfigurable fabric
Pinto et al. Low-power modified shift-add multiplier design using parallel prefix adder
CN109948200B (zh) 一种细粒度控制电源供应的低功耗处理器
Macii et al. Integrating clock gating and power gating for combined dynamic and leakage power optimization in digital cmos circuits
US20150341032A1 (en) Locally asynchronous logic circuit and method therefor
Samanth et al. Power reduction of a functional unit using rt-level clock-gating and operand isolation
US9208125B2 (en) Methods for operating and configuring a reconfigurable processor
US11308025B1 (en) State machine block for high-level synthesis
CN103440210A (zh) 异步时钟控制的寄存器堆读隔离方法
US9496851B2 (en) Systems and methods for setting logic to a desired leakage state
US10312886B2 (en) Asynchronous clock gating circuit
US20070085583A1 (en) System for and method of automatically reducing power to a semiconductor device
Parikh Low-Power Techniques for FPGA and ASIC Design: A Comprehensive Survey
JP2009301192A (ja) シミュレーション装置およびシミュレーション方法
Park et al. Hybrid asynchronous circuit generation amenable to conventional EDA flow
Jovanović et al. Standard cell-based low power embedded controller design
Nag et al. An Autonomous Power and Clock Gating Technique in SRAM-Based FPGA
JP2010113405A (ja) 半導体集積回路合成装置
CN120872287A (zh) 弹性进位链电路及可配置运算系统

Legal Events

Date Code Title Description
A107 Divisional application of patent
PA0104 Divisional application for international application

Comment text: Divisional Application for International Patent

Patent event code: PA01041R01D

Patent event date: 20210611

Application number text: 1020197003111

Filing date: 20190130

PG1501 Laying open of application
A201 Request for examination
PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 20210702

Comment text: Request for Examination of Application

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 20211227

Patent event code: PE09021S01D

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 20220728

Patent event code: PE09021S01D

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 20230331

Patent event code: PE09021S01D

E90F Notification of reason for final refusal
PE0902 Notice of grounds for rejection

Comment text: Final Notice of Reason for Refusal

Patent event date: 20230926

Patent event code: PE09021S02D

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 20240131

GRNT Written decision to grant
PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 20240430

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 20240502

End annual number: 3

Start annual number: 1

PG1601 Publication of registration