KR102625995B1 - Semiconductor package structures, methods, devices and electronic products - Google Patents

Abstract

This application provides semiconductor package structures, methods, devices, and electronic products. In the semiconductor package structure, package elements are fixed in a one-to-one correspondence within a recess on a substrate; The active surface of the package element faces away from the substrate, the package element and the recess in which it is located are separated by an insulating material, each package element has a first pad located on the active surface, and all first pads are positioned on the active surface. The surface of the pad facing away from the substrate is on the same plane; The redistribution layer is located on the side facing away from the substrate of the package element, a plurality of second pads are formed on the first side of the redistribution layer, and a plurality of third pads are formed on the second side facing the first side of the redistribution layer. is formed, the second pad corresponds one-to-one with the first pad and is in electrical contact; The passivation layer is located on the side of the redistribution layer facing away from the substrate; The substrate is made of a semiconductor material or an insulating material, and the thermal expansion coefficients of the substrate and the semiconductor material in the package element are the same or close to it. The semiconductor package structure has a small degree of distortion, good heat dissipation performance, and high reliability.

Description

Semiconductor package structures, methods, devices and electronic products}

This application belongs to the field of semiconductor manufacturing technology, and specifically relates to semiconductor package structures, methods, devices, and electronic products.

In a conventional semiconductor package manufacturing process, a semiconductor device must be obtained by packaging a package device (for example, a bare chip, also called a die). A typical process involves fixing the package element to a substrate, leadframe, or interposer, and then packaging the package element using a series of processes such as interconnection and molding, thereby completing the packaging. This is a method of acquiring semiconductor devices.

The purpose of this application is to provide semiconductor package structures, methods, devices, and electronic products.

In order to solve the above technical challenges, this application adopts the following technical solutions:

The semiconductor package structure includes a substrate, at least one package element, a redistribution layer, and a passivation layer, and at least one recess is opened in the substrate, and the package element is fixed in a one-to-one correspondence within the recess. ;

The active surface of the package element faces away from the substrate, the package element and the recess in which it is located are separated by an insulating material, each of the package elements has a first pad located on the active surface, The surfaces of all of the first pads facing away from the substrate are on the same plane;

The redistribution layer is located on a side of the package device that faces away from the substrate, a plurality of second pads are formed on a first side of the redistribution layer, and a plurality of second pads are formed on a second side of the redistribution layer facing the first side. A third pad is formed, the second pad is in electrical contact with the first pad in one-to-one correspondence, and the redistribution layer further includes a trace electrically connecting the second pad and the third pad;

the passivation layer is located on a side of the redistribution layer that faces away from the substrate;

Here, the substrate is formed of a semiconductor material or an insulating material, and the thermal expansion coefficients of the substrate and the semiconductor material in the package element are the same or close to it.

In order to solve the above technical problems, this application adopts the following technical solutions: The semiconductor packaging method is,

forming at least one recess in the substrate;

fixing at least one package element in a one-to-one correspondence within the recess, wherein the active surface of the package element faces away from the substrate and an insulating material separates the package element and the recess in which it is located, each wherein the packaged elements all have first pads located on active surfaces, and the surfaces of all the first pads facing away from the substrate are on the same plane;

forming a planar surface exposing the first pad;

A redistribution layer is formed, wherein a plurality of second pads are formed on a first side of the redistribution layer, a plurality of third pads are formed on a second side of the redistribution layer facing the first side, and the second pad is formed on a second side of the redistribution layer. The pad is in electrical contact with the first pad in one-to-one correspondence, and the redistribution layer further includes a trace electrically connecting the second pad and the third pad;

It includes forming a passivation layer,

Here, the substrate is formed of a semiconductor material or an insulating material, and the thermal expansion coefficients of the substrate and the semiconductor material in the package element are the same or close to it.

In order to solve the above technical problems, this application adopts the following technical solution: a semiconductor package structure includes a substrate, at least one first package element, at least one second package element, a redistribution layer and a passivation layer; At least one first recess and at least one second recess are opened in the substrate, the first package element is fixed in a one-to-one correspondence within the first recess, and the second package element is fixed in the second recess. They are fixed in a one-to-one correspondence, the first package element is in a bare chip state, and the second package element is in a package state and has a second electrode structure exposed to the outside;

The active surface of the first package element faces away from the substrate, the first package element and the first recess in which it is located are separated by an insulating material, and the second package element and the second recess in which it is located are separated by an insulating material. separated by an insulating material, each of the first package elements having a first pad located on an active surface, each of the first pads having a surface facing away from the substrate and all of the second electrode structures having The surface facing away from the substrate is on the same plane;

The redistribution layer is located on a side of the package device that faces away from the substrate, a plurality of second pads are formed on a first side of the redistribution layer, and a plurality of second pads are formed on a second side of the redistribution layer facing the first side. A third pad is formed, the first pad is in electrical contact with some of the second pads in a one-to-one correspondence, the second electrode structure is in electrical contact with the remaining second pads in a one-to-one correspondence, and the redistribution layer is It further includes a trace electrically connecting the second pad and the third pad, and a trace electrically connecting the second pad and the second electrode structure;

the passivation layer is located on a side of the redistribution layer that faces away from the substrate;

Here, the substrate is formed of a semiconductor material or an insulating material, and the thermal expansion coefficients of the substrate and the semiconductor material in the package element are the same or close to it.

In order to solve the above technical problems, this application adopts the following technical solutions: The semiconductor packaging method is,

forming at least one first recess and at least one second recess in the substrate;

Fixing at least one first package element in a one-to-one correspondence within the first recess, and fixing at least one second package element in a one-to-one correspondence within the second recess, wherein the first package element is a bare chip. state, the second package element has a second electrode structure exposed to the outside while in a package state, the active surface of the first package element faces away from the substrate, the first package element and the first electrode structure on which it is located The recesses are separated by an insulating material, and the second package element and the second recess in which it is located are separated by an insulating material, and each of the first package elements has a first pad located on the active surface. wherein surfaces of all first pads and all second electrode structures facing away from the substrate are on the same plane;

forming a flat surface exposing the first pad and the second electrode structure;

A redistribution layer is formed, wherein a plurality of second pads are formed on a first side of the redistribution layer, a plurality of third pads are formed on a second side of the redistribution layer facing the first side, and the first The pad is in electrical contact with some of the second pads in a one-to-one correspondence, the second electrode structure is in electrical contact with the remaining second pads in a one-to-one correspondence, and the redistribution layer electrically connects the second pad and the third pad. further providing a trace and a trace electrically connecting the second pad and the second electrode structure;

It includes forming a passivation layer,

Here, the substrate is formed of a semiconductor material or an insulating material, and the thermal expansion coefficients of the substrate and the semiconductor material in the package element are the same or close to it.

In order to solve the above technical problems, this application adopts the following technical solutions: In the semiconductor device, the semiconductor device includes the semiconductor package structure described above.

In order to solve the above technical challenges, this application adopts the following technical solutions:

In electronic products, the electronic products include the above-described semiconductor devices.

Compared with the prior art, the beneficial effects of the present application are as follows: The thermal expansion coefficients of the semiconductor material and the substrate in the package element are the same or close (e.g., they are made of the same semiconductor material), so that after packaging is completed, The semiconductor package structure has relatively much smaller distortion caused by temperature changes, which is advantageous for increasing the yield and electrical and mechanical reliability of semiconductor devices. At the same time, in some embodiments, the semiconductor substrate has better heat dissipation performance compared to molding materials in conventional package formats.

1A and 1B are structural diagrams of two types of semiconductor package structures according to an embodiment of the present application, respectively.
Figure 2 is a flow diagram of a semiconductor packaging method according to an embodiment of the present application.
FIGS. 3A to 3G are diagrams illustrating product states at different packaging stages of the semiconductor package structure shown in FIG. 1A.
FIGS. 4A to 4G are diagrams illustrating product states at different packaging stages of the semiconductor package structure shown in FIG. 1B.
5A and 5B are structural diagrams of two types of semiconductor package structures according to an embodiment of the present application.
Figure 6 is a flowchart of a semiconductor packaging method according to an embodiment of the present application.
FIGS. 7A to 7F are diagrams illustrating product states at different packaging stages of the semiconductor package structure shown in FIG. 5A.
FIGS. 8A to 8F are diagrams illustrating product states at different packaging stages of the semiconductor package structure shown in FIG. 5B.

In this application, terms such as “comprise” or “comprise” are intended to indicate that there are features, numbers, steps, actions, members, parts, or combinations thereof disclosed in this specification, or one or more other It does not exclude the possibility of features, numbers, steps, actions, members, parts or combinations thereof.

Additionally, it should be further explained that, as long as there is no conflict, the embodiments in this application and the features in the embodiments can be combined with each other. Hereinafter, the present application will be described in detail with reference to the accompanying drawings and combination of examples.

Hereinafter, the present application will be described in more detail by combining the embodiments shown in the accompanying drawings.

Embodiments of the present application provide a semiconductor package structure, which includes a substrate, at least one package element, a redistribution layer and a passivation layer, wherein at least one recess is opened in the substrate, and the package elements have a one-to-one correspondence within the recess. and is fixed; The active surface of the packaged element faces the substrate, the packaged element and the recess in which it is located are separated by an insulating material, each packaged element has a first pad located on the active surface, and the substrate of all the first pads. The surfaces facing away from are on the same plane; The redistribution layer is located on the side facing away from the substrate of the package element, a plurality of second pads are formed on the first side of the redistribution layer, and a plurality of third pads are formed on the second side facing the first side of the redistribution layer. The second pad and the first pad are in electrical contact in a one-to-one correspondence, the passivation layer is located on the side of the redistribution layer facing away from the substrate, and the redistribution layer has a trace that electrically connects the second pad and the third pad. Equipped with more; Here, the substrate is formed of a semiconductor material or an insulating material, and the thermal expansion coefficients of the substrate and the semiconductor material in the package element are the same or close to it.

Since the thermal expansion coefficients of the semiconductor material and the substrate within the package element are the same or close to it (for example, they are made of the same semiconductor material), after packaging is completed, the distortion caused by temperature changes in the semiconductor package structure is relatively much smaller. , It is advantageous to increase the yield and electrical and mechanical reliability of semiconductor devices. At the same time, in some embodiments, the semiconductor substrate has better heat dissipation performance than molding materials in conventional package formats.

For example, the semiconductor material in the substrate and the semiconductor material in the package element are the same.

In this embodiment, the package element is placed within a recess formed in the substrate, and the top of the package element is covered by a redistribution layer. The basic materials within the substrate and package elements are all the same semiconductor material.

The term “same semiconductor material” in this application refers to those whose chemical components are the same, for example, they are all made of silicon material, or they are all made of gallium arsenide material. However, this is not limited to completely matching the purity, density, or crystallization state of these semiconductor materials.

Also, for example, the semiconductor material in the package device is silicon or gallium arsenide, and the material of the substrate is engineering heat-resistant glass. Their thermal expansion coefficients are of the same order of magnitude.

In this application, the fact that the thermal expansion coefficients of two materials are close means that the absolute value of the ratio of the difference between the two and the smaller absolute value of the two is less than 9.

In some embodiments, the packaged device is a bare chip.

In some embodiments, when a single package element is included in a single semiconductor package structure, the role of the redistribution layer is simply to draw out the first pad on the package element.

In some embodiments, a single semiconductor package structure includes a plurality of package elements, and in this case, a line in the redistribution layer may serve to interconnect signals between first pads of the plurality of package elements.

In some embodiments, if the number of package elements is plural and the thickness is the same, the depth of each recess is the same.

Referring to FIGS. 1A and 3A , the thickness of the package element 21 and the package element 22 are the same, and the depth of the recess 10 where they are located is the same.

Of course, the package element 21 and the package element 22 may be of the same model or may be of different models. Because the thickness of the package element 21 and the package element 22 is the same, each recess 10 can be formed using the same recess formation (eg, etching) process.

If the initial thickness of these package elements does not match, their thicknesses can be made the same through a thinning process.

Of course, even if the initial thickness of these package elements 21 and 22 is the same, their thickness can be reduced and made the same through a thinning process. In this way, the groove depth of the recess 10 opened in the substrate 1 can be reduced.

In some embodiments, the number of package elements is plural, and at least two of the package elements have different thicknesses. Here, the depths of the at least two recesses are different so that the upper surface of the first pad of each package element is on the same plane.

Referring to FIGS. 1B and 4A , the thickness of the package element 21 and the package element 22 are different from each other, and the depth of the recess 10 where they are located is also different. The package element 21 is thicker, and the depth of the recess 10 in which it is located is correspondingly deeper.

Recesses 10 with different depths can be formed by controlling the recess formation process (for example, step-by-step etching or double etching).

In some embodiments, after the passivation layer covers the third pad on top of the redistribution layer, the semiconductor package structure can be sold as a stand-alone product.

In some embodiments, referring to FIGS. 1A and 1B, the semiconductor package structure further includes an electrode structure 5 located on a side of the passivation layer 4 facing away from the substrate 1, and the passivation layer 4 A through via is opened in the area facing the third electrode 32, the electrode structure 5 has a one-to-one correspondence with the third electrode 32, and the electrode structure 5 has a corresponding third electrode through the through via. It is electrically connected to (32).

Specifically, the electrode structure 5 includes, for example, an under bump metal (UBM) covering the third pad, and a solder ball located on top of the under bump metal. Of course, the electrode structure may be a pad formed on the third pad.

In some embodiments, the package element and the groove bottom of the recess in which it is located are separated by an insulating adhesive layer. In other words, the package element is fixed with an insulating adhesive layer to achieve insulation between the package element and the bottom of the groove of the recess.

In some embodiments, the package element and the side of the recess in which it is located are separated by a cured resin material (eg, epoxy resin) or an inorganic insulating material. That is, the gap between the package element and the recess where it is located can be filled with a resin material and hardened, or an inorganic insulating material (for example, silicon dioxide) can be deposited in the gap.

In some embodiments, the conductors in the redistribution layer are separated by a polymer. The polymer in the redistribution layer is, for example, polyimide (PI) or polyparaphenylene benzobisoxazole (PBO). Also, for example, in the redistribution layer, conductors are separated from each other by a molding compound.

At least one layer of metal trace within the redistribution layer, and a metal trace connecting the different layers (if there is a multi-layer metal trace), a through via connecting the metal trace and the second pad, and a through via connecting the metal trace and the third pad. Includes. The traces in the redistribution layer may implement interconnection of the second pad and the third pad, interconnection of the second pad and the second pad, and interconnection of the third pad and the third pad.

Referring to FIG. 2, an embodiment of the present application further provides a semiconductor packaging method. The packaging method can manufacture the semiconductor package structure provided in the above-described embodiment. The manufacturing method includes the following steps.

Step 1000: Forming at least one recess in the substrate;

Step 1001: Fixing at least one package element in a one-to-one correspondence within the recess, wherein the active surface of the package element is turned away from the substrate, the package element and the recess in which it is located are separated by an insulating material, and each package The device has first pads all located on the active surface, the substrate-facing surfaces of all first pads being coplanar;

Step 1002: Forming a flat surface exposing the first pad;

Step 1003: Forming a redistribution layer, wherein a plurality of second pads are formed on a first side of the redistribution layer, a plurality of third pads are formed on a second side facing the first side of the redistribution layer, and the second pad is in electrical contact with the first pad in one-to-one correspondence, and the redistribution layer further includes a trace electrically connecting the second pad and the third pad;

Step 1004: forming a passivation layer;

Here, the substrate is formed of a semiconductor material or an insulating material, and the thermal expansion coefficients of the substrate and the semiconductor material in the package element are the same or close to it.

For example, the semiconductor material in the substrate and the semiconductor material in the package element are the same.

Also, for example, the semiconductor element in the package element is silicon or gallium arsenide, and the material of the substrate is engineering heat-resistant glass.

Since the package element and the substrate are made of the same semiconductor material, and their thermal expansion coefficients are the same, after packaging is completed, the distortion caused by temperature changes in the semiconductor element is relatively much smaller, improving the yield and electrical and mechanical properties of the semiconductor element. It is advantageous for increasing reliability.

Comparatively, the thermal conductivity coefficient of silicon and engineering heat-resistant glass is greater than that of conventional molding materials, so the heat dissipation performance of the semiconductor package structure is also higher.

In some embodiments, the packaging method also includes:

Step 1005: Forming at least one through via in a one-to-one correspondence with a third pad in the passivation layer, exposing the third pad corresponding to the through via;

Step 1006: It further includes forming an electrode structure in electrical contact with the third pad.

In some embodiments, the number of package elements is plural, the depth of the recess in which they are located is the same, and the packaging method includes performing thinning on at least some of the package elements so that the thickness of each package element is the same. It further includes.

In some embodiments, the quantity of the package elements is plural, the thickness of the at least two package elements is different, and when forming the recess in the substrate, the upper surface of the first pad of each package element is on the same plane, at least The depths of the two recesses are different.

In some embodiments, fixing at least one package element in a one-to-one correspondence within the recess includes:

Forming an insulating adhesive layer at the bottom of the groove of the recess;

Attaching the packaged element to the insulating adhesive layer, wherein an air gap remains between the packaged element and the side of the recess in which it is located;

It includes filling an insulating material between the package element and the side of the corresponding recess.

In some embodiments, filling the insulating material between the package element and the side of the corresponding recess includes:

It includes filling and curing a resin material between the package element and the corresponding recess side, or depositing an inorganic oxide insulating material into the void between the package element and the corresponding recess side.

In some embodiments, forming a planar surface exposing the first pad includes removing insulating material and substrate material higher than the first pad through a grinding process and then performing surface treatment.

In some embodiments, a large area of the substrate may allow for the formation of a large number of recesses. The manufacturing further includes obtaining a plurality of semiconductor package structures through a cutting process, wherein each semiconductor package structure includes at least one package element, a recess in which the included package element is located, and the included package. It includes a redistribution layer electrically connected to the device, and a passivation layer on top of the included redistribution layer.

In some embodiments, the packaged device is a bare chip.

In some embodiments, the insulating material in the redistribution layer includes a polymer or molding compound.

In some embodiments, referring to FIGS. 3A to 3G and 1A, a specific implementation process of the method for packaging a semiconductor device is as follows.

First step: Referring to FIG. 3A, this is a step of forming a plurality of recesses 10 in the substrate 1 using an etching process, and the depth of the plurality of recesses 10 is the same.

Second step: Referring to FIG. 3B, an insulating adhesive layer 111 is formed at the bottom of the groove of the recess 10.

Third step: Referring to FIG. 3C, the package element 21 and the package element 22 are each placed in the recess 10 and attached to the insulating adhesive layer 111. Here, the first pad 211 of the package element 21 and the first pad 221 of the package element 22 face upward, and the thicknesses of the package element 21 and 22 are the same. A gap remains between the package element 21 and the package element 22 and the recess 10 where they are located.

Step 4: Referring to FIG. 3D, the insulating material 112 is filled inside the recess 10 and cured. For example, liquid epoxy resin is injected dropwise into the gap between the recess 10 and the package elements 21 and 22, and the epoxy resin is hardened through heating, or the recess 10 and the package are An inorganic insulating material (for example, silicon dioxide) is deposited into the gaps between the elements 21 and 22.

Step 5: Referring to Figure 3e, the insulating material higher than the first pads 211 and 221 and the substrate material higher than the first pads 211 and 221 are removed through grinding, chemical cleaning, and polishing. A surface treatment process such as the above is performed to obtain a flat surface exposing the first pads 211 and 221.

Step 6: Referring to Figure 3f, a redistribution layer 3 is formed on this flat surface, so that the second electrode 31 of the redistribution layer 3 is electrically connected to the first pads 211 and 221, respectively. Implementing contact, the third electrode 32 of the redistribution layer 3 is interconnected with the second electrode 31.

Specifically, for example, one layer of polyimide thin film is formed, and then, through a patterning process (e.g., photoresist application, exposure, development, etching), first pads 211 and 221 are formed on the polyimide thin film. ) forming a through via exposing the Afterwards, one layer of metal thin film is deposited, and a trace 33 connected to each of the first pads 211 and 221 is formed through a patterning process, and the second electrode 31 is made of a metal material in the through-via of the lower layer. ) is formed. Afterwards, one layer of polyimide thin film and one layer of trace 33 are formed again; Afterwards, one layer of polyimide thin film is formed, then a patterning process is performed to expose some areas of the lower trace 33, and finally, one layer of metal thin film is deposited, and a patterning process is performed to expose the lower trace 33. A third electrode 32 connected to is formed.

Multilayer traces 33 may be included in the redistribution layer.

Of course, first, a pattern of the second electrode 31 is formed using a patterning process, then a polyimide thin film is formed, and then a through via is formed to expose the second electrode 31 to the polyimide thin film, A pattern of the traces 33 of the first layer may be formed.

A person skilled in the art can fabricate a redistribution layer according to prior art.

Step 7: Referring to FIG. 3g, a passivation layer 4 is formed on the redistribution layer 3. The material of the passivation layer 4 may be, for example, silicon nitride or polyimide. The passivation layer 4 serves to protect the underlying device.

Step 8: Referring to FIG. 1A, a through via is etched in the passivation layer 4 to expose each third electrode 32, and an electrode structure 5 is formed on the third electrode 32. The electrode structure 5 includes, for example, an under bump metal (UBM) on the third electrode 32 and a solder ball on the under bump metal, and of course the electrode structure 5 may be in the form of a pad. .

In some embodiments, referring to FIGS. 4A to 4G and 1B, a specific implementation process of the method for packaging a semiconductor device is as follows.

Step 1: Referring to FIG. 4A, a plurality of recesses 10 are formed on the substrate 1 by controlling the recess formation process (for example, step-by-step etching or double etching), and a plurality of recesses 10 are formed on the substrate 1. ) has different depths.

Second step: Referring to FIG. 4b, an insulating adhesive layer 111 is formed at the bottom of the groove of the recess 10.

Step 3: Referring to FIG. 4C, the package element 21 and the package element 22 are each placed in the recess 10 and attached to the insulating adhesive layer 111, where the first part of the package element 21 is attached. The first pad 211 and the first pad 221 of the package device 22 face upward and are located on the same plane, and the thicknesses of the package device 21 and 22 are different.

Step 4: Referring to FIG. 4D, the insulating material 112 is filled into the recess 10 and cured. For example, epoxy resin in a liquid state is injected into the gap between the recess 10 and the package elements 21 and 22, and the epoxy resin is cured through heating.

Step 5: Referring to Figure 4e, the insulating material 112 higher than the first pads 211 and 221 and the substrate material higher than the first pads 211 and 221 are removed through grinding, and the A surface treatment process such as cleaning or polishing is performed to obtain a flat surface exposing the first pads 211 and 221.

Step 6: Referring to FIG. 4F, a redistribution layer 3 is formed on this flat surface, and the second electrode 31 of the redistribution layer 3 is in electrical contact with the first pads 211 and 221, respectively. is implemented, and the third electrode 32 of the redistribution layer 3 is interconnected with the second electrode 31.

Specifically, for example, one layer of polyimide thin film is formed, and then, through a patterning process (e.g., photoresist application, exposure, development, etching), first pads 211 and 221 are formed on the polyimide thin film. ) forming a through via exposing the Afterwards, one layer of metal thin film is deposited, and a trace 33 connected to each of the first pads 211 and 221 is formed through a patterning process, and the second electrode 31 is made of a metal material in the through-via of the lower layer. ) is formed. Afterwards, one layer of polyimide thin film is formed, then a patterning process is performed to expose some areas of the lower trace 33, and finally, a layer of metal thin film is deposited, and a patterning process is performed to expose the lower trace 33. A third electrode 32 connected to is formed.

A plurality of trace layers 33 may be included in the redistribution layer.

Step 7: Referring to FIG. 4g, a passivation layer 4 is formed on the redistribution layer 3. The material of the passivation layer 4 may be, for example, silicon nitride or polyimide. The passivation layer 4 serves to protect the underlying device.

Step 8: Referring to FIG. 1B, a through via is etched in the passivation layer 4 to expose each third electrode 32, and an electrode structure 5 is formed on the third electrode 32. The electrode structure 5 includes, for example, an under bump metal (UBM) on the third electrode 32 and a solder ball on the under bump metal, and the electrode structure 5 may be in the form of a pad (Bonding Pad). .

Embodiments of the present application provide a semiconductor package structure, including a substrate, at least one first package element, at least one second package element, a redistribution layer and a passivation layer, and having at least one first recess and a passivation layer in the substrate. At least one second recess is opened, the first package element is fixed in a one-to-one correspondence within the first recess, the second package element is fixed in a one-to-one correspondence within the second recess, and the first package element is a bare chip. state, and the second package element has a second electrode structure exposed to the outside while being in a package state; The active surface of the first package element faces away from the substrate, between the first package element and the first recess in which it is located is separated by an insulating material, and between the second package element and the second recess in which it is located is an insulating material. and each first package element has a first pad located on an active surface, and the substrate-facing surface of all first pads and the substrate-facing surface of all second electrode structures are the same. is on a plane; The redistribution layer is located on the side facing away from the substrate of the package element, a plurality of second pads are formed on the first side of the redistribution layer, and a plurality of third pads are formed on the second side of the redistribution layer facing the first side. is formed, the first pad is in electrical contact with some of the second pads in a one-to-one correspondence, the second electrode structure is in electrical contact with the remaining second pads in a one-to-one correspondence, and the redistribution layer is connected to the second pad and the third pad. It further includes a trace electrically connecting a trace, and a trace electrically connecting the second pad and the second electrode structure; The passivation layer is located on the side of the redistribution layer facing away from the substrate; Here, the substrate is formed of a semiconductor material or an insulating material, and the thermal expansion coefficients of the substrate and the semiconductor material in the package element are the same or close to it.

For example, the semiconductor material in the substrate and the semiconductor material in the package element are the same.

Also, for example, the semiconductor material in the package device is silicon or gallium arsenide, and the material of the substrate is engineering heat-resistant glass.

In this embodiment, the first package element is disposed in a first recess formed in the substrate, the second package element is disposed in the second recess formed in the substrate, and the top of the first package element and the second package element is a redistribution layer. covered by The basic materials in the substrate and the first package element are all the same semiconductor material.

The first package device is in a bare chip state, and the second package device is a device whose packaging has already been completed. The semiconductor package structure of the present application implements primary packaging for the first package element and secondary packaging for the second package element, and implements interconnection between the first package element and the second package element.

The package format of the second package element is, for example, a surface mount package, a ceramic package, etc. The second package element may be, for example, a chip resistor, a chip-type multilayer ceramic capacitor, or other elements that are already in a packaged state.

The present application is not limited to the shape and position of each second electrode structure of the same second package element, and this second electrode structure has a surface located on the same plane, so that it is in common with the first pad of the first package element. All you have to do is be able to implement immunity.

The term “same semiconductor material” in this application refers to those whose chemical components are the same, for example, they are all made of silicon material, or they are all made of gallium arsenide material. However, this is not limited to completely matching the purity, density, or crystallization state of these semiconductor materials.

Since the thermal expansion coefficients of the first package element and the substrate are the same or close to it, after packaging is completed, the distortion of the semiconductor element due to temperature changes is relatively much smaller, increasing the yield and electrical and mechanical reliability of the semiconductor package structure. It is advantageous. At the same time, in some embodiments, the semiconductor substrate has better heat dissipation performance compared to molding materials in conventional package formats.

In addition, the semiconductor package structure implements secondary packaging for the second package element and interconnection between the first package element and the second package element, so that the semiconductor packaging result has a higher degree of integration.

In some embodiments, the number of first package elements is plural and the thickness is the same, and the depth of each first recess is the same.

Referring to FIGS. 5A and 7A , the first package elements 22a and 23a have the same thickness, and the depth of the first recess H1 where they are located is the same.

Of course, the first package element 22a and the first package element 23a may be of the same model or may be of different models. Since the first package element 23a and the first package element 22a have the same thickness, each first recess 10 may be formed using the same recess formation (eg, etching) process.

If the initial thickness of the first package elements does not match, their thicknesses can be made the same through a thinning process.

Of course, even if the initial thickness of these package elements 22a and 23a is the same, their thickness can be reduced and made the same through a thinning process. In this way, the groove depth of the recess 10 opened in the substrate 1 can be reduced.

Because the second package element is in a packaged state, its external size is relatively fixed. Therefore, the depth of the second recess is relatively fixed, and the adjustable margin is relatively small. Therefore, it is desirable to insert a relatively thin second package element into the semiconductor package structure.

In some embodiments, the number of first package elements is plural, and the at least two first package elements have different thicknesses. Here, the depths of the at least two recesses are different so that the upper surface of the first pad of each first package element is on the same plane.

Referring to FIGS. 5B and 8A , the thickness of the first package element 22a and 23a are different from each other, and the depth of the first recess H1 where the first package element 22a and 23a are located is also different. The first package element 22a is thicker, and the depth of the first recess H1 in which it is located is correspondingly deeper.

The first recess H1 and the second recess H2 of different depths can be formed by controlling the recess forming process (for example, step-by-step etching or double etching).

In some embodiments, after covering the third pad on top of the redistribution layer with a passivation layer, the semiconductor package structure may be sold as a stand-alone product.

In some embodiments, referring to FIGS. 5A and 5B, the semiconductor package structure further includes a first electrode structure 5 located on the side of the passivation layer 4 facing away from the substrate 1, and the passivation layer ( 4) A through via is opened in the area opposite to the third electrode 32 on the top, the first electrode structure 5 corresponds one to one with the third electrode 32, and the first electrode structure 5 has a through via. It is electrically connected to the corresponding third electrode 32 through.

Specifically, the first electrode structure 5 includes, for example, an under bump metal (UBM) covering the third pad, and a solder ball located on top of the under bump metal. Of course, the first electrode structure may be a pad formed on the third pad.

In some embodiments, the first package element and the groove bottom of the first recess in which it is located are separated by an insulating adhesive layer, and the second package element and the groove bottom of the second recess in which it is located are separated by an insulating adhesive layer. separated. That is, the first package element and the second package element are fixed with an insulating adhesive layer, insulation is implemented between the first package element and the groove bottom of the first recess, and insulation is provided between the second package element and the second recess groove bottom. Implement.

In some embodiments, the first package element and the side of the first recess in which it is located are separated by a cured resin material (eg, epoxy resin) or an inorganic insulating material; The second package element and the side of the second recess are separated by a cured resin material (eg, epoxy resin) or an inorganic insulating material. That is, the gap between each package element and the recess where it is located can be filled with a resin material and hardened, or an inorganic insulating material (for example, silicon dioxide) can be deposited in the gap.

In some embodiments, the conductors in the redistribution layer are separated by a polymer. The polymer in the redistribution layer is, for example, polyimide (PI) or polyparaphenylene benzobisoxazole (PBO). Also, for example, in the redistribution layer, conductors are separated from each other by a molding compound.

At least one layer of metal trace within the redistribution layer, and a metal trace connecting the different layers (if there is a multi-layer metal trace), a through via connecting the metal trace and the second pad, and a through via connecting the metal trace and the third pad. is included. The traces in the redistribution layer may implement the interconnection of the second pad and the third pad, the interconnection of the second pad and the second electrode structure, and, of course, the interconnection of the second pad and the second pad.

Referring to FIG. 6, an embodiment of the present application further provides a semiconductor packaging method. The packaging method can implement the semiconductor package structure provided in the above-described embodiment. The manufacturing method is

Step 1000: Forming at least one first recess and at least one second recess in the substrate;

Step 1001: Fixing at least one first package element in a one-to-one correspondence within the first recess, and fixing at least one second package element in a one-to-one correspondence within the second recess, wherein the first package element is bare. It is in a chip state, and the second package element is in a package state and has a second electrode structure exposed to the outside. The active surface of the first package element faces the substrate, and the area between the first package element and the first recess where it is located is separated by an insulating material, and separated by an insulating material between the second package element and the second recess in which it is located, each first package element having a first pad located on an active surface, and each first package element having a first pad located on an active surface, The surface facing away from the substrate of the first pad and the second electrode structure is on the same plane;

Step 1002: Forming a flat surface exposing the first pad and second electrode structures;

Step 1003: Forming a redistribution layer, wherein a plurality of second pads are formed on the first side of the redistribution layer, and a plurality of third pads are formed on the second side facing the first side of the redistribution layer, and the first pad is The second electrode structure is in electrical contact with some of the second pads in a one-to-one correspondence, the second electrode structure is in electrical contact with the remaining second pads in a one-to-one correspondence, and the redistribution layer includes a trace electrically connecting the second pad and the third pad, and a second electrode structure. further providing a trace electrically connecting the two pads and the second electrode structure;

Step 1004: forming a passivation layer;

Here, the substrate is formed of a semiconductor material or an insulating material, and the thermal expansion coefficients of the substrate and the semiconductor material in the package element are the same or close to it.

For example, the semiconductor material in the substrate and the semiconductor material in the package element are the same.

Also, for example, the semiconductor material in the package device is silicon or gallium arsenide, and the material of the substrate is engineering heat-resistant glass.

Since the semiconductor material and the substrate inside the first package element have the same or close thermal expansion coefficient, after packaging is completed, the distortion caused by temperature changes in the semiconductor package structure is relatively much smaller, improving the yield and electrical stability of the semiconductor package structure. , It is advantageous to increase mechanical reliability.

Comparatively, the heat conductivity coefficient of semiconductor materials and engineering heat-resistant glass is higher than that of conventional molding materials, so the heat dissipation properties of the semiconductor package structure are also better.

In some embodiments, the packaging method also includes:

Step 1005: Forming at least one through via in a one-to-one correspondence with a third pad in the passivation layer, exposing the third pad to which the through via corresponds;

Step 1006: It further includes forming a first electrode structure in electrical contact with the third pad.

In some embodiments, the number of first package elements is plural, the depth of the first recess in which they are located is the same, and the packaging method includes performing thinning on at least some of the first package elements, so that each first package A step of ensuring that the thickness of the devices is the same is further included.

In some embodiments, the thickness of at least two of the first package elements and the second package elements is different, and when forming the first recess and the second recess on the substrate, the upper portion of the first pad of each first package element The depths of the at least two recesses are different so that the surface and the top surface of each second electrode structure are on the same plane.

In some embodiments, fixing at least one first package element in a one-to-one correspondence within the first recess includes:

forming an insulating adhesive layer on the bottom of the groove of the first recess;

Attaching the first packaged element to the insulating adhesive layer, wherein an air gap remains between the first packaged element and the side of the first recess where it is located;

It includes filling an insulating material between the first package element and the side of the corresponding first recess.

In some embodiments, filling the insulating material between the first package element and the side of the corresponding first recess includes:

Comprising filling and curing a resin material between the first package element and the corresponding first recess side, or depositing an inorganic oxide insulating material into the void between the first package element and the corresponding first recess side. do.

In some embodiments, fixing at least one second package element in a one-to-one correspondence within the second recess includes:

forming an insulating adhesive layer on the groove bottom of the second recess;

Attaching a second package element to an insulating adhesive layer, wherein an air gap is provided between the second package element and a side of the second recess;

It includes filling an insulating material between the second package element and the side of the corresponding second recess.

In some embodiments, filling an insulating material between the second package element and the corresponding second recess side includes:

Filling and curing a resin material between the second package element and the corresponding side of the second recess, or depositing an inorganic oxide insulating material into the void between the second package element and the corresponding side of the second recess. Includes.

In some embodiments, forming a flat surface exposing the first pad and second electrode structures includes removing the insulating material and substrate material higher than the first pad and second electrode structures through a grinding process, followed by surface treatment. It includes steps to perform.

In some embodiments, if the area of the substrate is large, a large number of first recesses and second recesses may be formed. The fabrication also includes obtaining a plurality of semiconductor package structures through a cutting process, wherein the at least one semiconductor package structure includes at least one first package element, at least one second package element, a first recess in which the included first package element is located, a second recess in which the included second package element is located, a redistribution layer electrically connected to the included first package element and the included second package element, and It includes a passivation layer on top of the redistribution layer.

In some embodiments, the insulating material in the redistribution layer includes a polymer or molding compound.

In some embodiments, referring to FIGS. 7A to 7F and 5A, a specific implementation process of the semiconductor packaging method is as follows.

Step 1: Referring to FIG. 7A, a first recess (H1) and a second recess (H2) are formed in the substrate 1 using an etching process, and the depth of the plurality of first recesses (H1) is is the same, but is different from the depth of the second recess (H2).

Second step: Referring to FIG. 7B, an insulating adhesive layer 111 is formed at the bottom of the grooves of the first recess H1 and the second recess H2.

Step 3: Referring to FIG. 7B, the first package elements 22a and 23a are respectively placed in the first recess H1, and the second package element 21a is placed in the second recess H2. By arranging, all of the first package elements 22a, 23a and the second package element 21a are attached to the insulating adhesive layer 111. Here, the first pad 221a of the first package element 22a and the first pad 231a of the first package element 23a face upward, and the first package element 22a and the first package element 23a The thickness is the same, and the upper surfaces of each of the first pads 221a, 231a and the second electrode structure 211a are on the same plane. A gap remains between the first package elements 22a and 23a and the second package elements 21a and the side walls of the recesses H1 and H2.

Step 4: Referring to FIG. 7C, the insulating material 112 is filled inside the first recess (H1) and the second recess (H2) and cured. For example, liquid epoxy resin is injected dropwise into the gap between the first recess (H1) and the first package elements (22a, 23a), and liquid epoxy resin is injected into the second recess (H2). The epoxy resin is cured by dropwise injection into the gap between the second package elements 21a and heating. Alternatively, an inorganic insulating material (for example, silicon dioxide) is deposited in the gap between the first recess (H1) and the first package elements (22a) and (23a), and the second recess (H2) and the second package element are deposited. An inorganic insulating material is deposited into the gap between (21a).

Step 5: Referring to FIG. 7D, the insulating material 112 and the first pads 221a, 231a and the like are higher than the first pads 221a and 231a and the second electrode structure 211a through grinding. After removing the substrate material higher than the second electrode structure 211a, surface treatment processes such as chemical cleaning and polishing are performed to create a flat surface exposing the first pads 221a, 231a and the second electrode structure 211a. Obtain the surface.

Step 6: Referring to FIG. 7E, a redistribution layer 3 is formed on this flat surface, so that the second electrode 31 of the redistribution layer 3 is the first pad 221a, 231a, and the second pad, respectively. Electrical contact is made with the electrode structure 211a, and the third electrode 32 of the redistribution layer 3 is interconnected with the second electrode 31.

Specifically, for example, one layer of polyimide thin film is formed, and then, through a patterning process (e.g., photoresist application, exposure, development, etching), first pads 221a and 231a are formed on the polyimide thin film. ) and forming a through via exposing the second electrode structure 211a; Afterwards, one layer of metal thin film is deposited and a patterning process is performed to form one layer of trace 33 connected to each of the first pads 221a and 231a and the second electrode structure 211a, and the lower layer of the trace 33 is formed. The second electrode 31 is formed from a metal material in the through via. Afterwards, one layer of polyimide thin film is formed again, the through via exposing the lower layer trace is etched, one layer of metal thin film is deposited, and a third electrode is connected to the lower layer trace 33 through a patterning process. It forms (32). One or multiple layers of traces 33 may be provided within the redistribution layer.

Of course, first, a pattern of the second electrode 31 is formed using a patterning process, then a polyimide thin film is formed, and then a through via is formed to expose the second electrode 31 to the polyimide thin film, A pattern of the first layer trace 33 may be formed.

A person skilled in the art can fabricate a redistribution layer according to prior art.

Step 7: Referring to FIG. 7F, a passivation layer 4 is formed on the redistribution layer 3. The material of the passivation layer 4 may be, for example, silicon nitride or polyimide. The passivation layer 4 serves to protect the underlying device.

Step 8: Referring to FIG. 5A, a through via is etched in the passivation layer 4 to expose each third electrode 32, and an electrode structure 5 is formed on the third electrode 32. The electrode structure 5 includes, for example, an under bump metal (UBM) on the third electrode 32 and a solder ball on the under bump metal, and of course the electrode structure 5 may be in the form of a pad. .

In some embodiments, referring to FIGS. 8A to 8F and 5B, a specific implementation process of the packaging method for a semiconductor device is as follows.

First step: Referring to FIG. 8A, a recess formation process (for example, step-by-step etching or double etching) is controlled to form a plurality of first recesses (H1) and second recesses (H2) on the substrate 1. , and the depths of the plurality of recesses 10 are different.

Second step: Referring to FIG. 8B, an insulating adhesive layer 111 is formed at the bottom of the grooves of the first recess H1 and the second recess H2.

Step 3: Referring to FIG. 8B, the first package element 22a and the first package element 23a are each disposed in one first recess H1, and the second package element 21a is placed in the second recess H1. It is placed in the recess H2, and the first package elements 22a, 23a, and the second package element 21a are all attached to the insulating adhesive layer 111. Here, the first pad 221a of the first package element 22a and the first pad 231a of the first package element 23a face upward, and the first pads 221a, 231a and the second electrode The upper surface of the structure 211a is on the same plane, the thickness of the first package elements 22a, 23a and the second package element 21a are different, and the depth of the recess in which they are located is also different.

Step 4: Referring to FIG. 8C, the insulating material 112 is filled into the first recess (H1) and the second recess (H2) and cured. For example, epoxy resin in a liquid state is injected dropwise into the gap between the first recess (H1) and the first package elements (22a) and (23a), and the second recess (H2) and the second package element (21a) ) is injected dropwise into the gap, and the epoxy resin is cured through heating.

Step 5: Referring to FIG. 8D, the insulating material 112 and the first pads 221a, 231a and the like are higher than the first pads 221a and 231a and the second electrode structure 211a through grinding. The substrate material higher than the second electrode structure 211a is removed, and then a surface treatment process such as chemical cleaning and polishing is performed to expose the first pads 221a, 231a and the second electrode structure 211a. Obtain a flat surface.

Step 6: Referring to Figure 8e, a redistribution layer 3 is formed on this flat surface, and the second electrode 31 of the redistribution layer 3 is the first pad 221a, 231a, and the second pad, respectively. Electrical contact is made with the electrode structure 211a, and the third electrode 32 of the redistribution layer 3 is interconnected with the second electrode 31. The redistribution layer 3 includes at least one layer of trace 33, a through via connecting the trace 33 and the second electrode 31, and a through via connecting the trace 33 and the third electrode 32. do.

Step 7: Referring to FIG. 8F, a passivation layer 4 is formed on the redistribution layer 3. The material of the passivation layer 4 may be, for example, silicon nitride or polyimide. The passivation layer 4 serves to protect the underlying device.

Step 8: Referring to FIG. 5B, through-vias are etched in the passivation layer 4 to expose each third electrode 32 and form an electrode structure 5 on the third electrode 32. The first electrode structure 5 includes, for example, an under bump metal (UBM) on the third electrode 32 and a solder ball on the under bump metal, and the first electrode structure 5 is a pad (Bonding Pad). It may be possible.

Embodiments of the present application further provide a semiconductor device including the above-described semiconductor package structure. That is, by performing additional processing on the above-described semiconductor package structure, for example, it can be combined with other semiconductor package structures to form an assembly or module.

Embodiments of the present application further provide electronic products including the above-described semiconductor devices. Electronic products include various types of electronic products, such as mobile phones, computers, servers, and smart watches.

As the stability of the semiconductor package structure is improved, the stability of these semiconductor devices and electronic products is also correspondingly improved.

Each embodiment of the present application has been described in a progressive manner, the same or similar parts between each embodiment can be referred to, and each embodiment has been described with emphasis on the parts that are different from other embodiments.

The scope of protection of the present application is not limited to the above embodiments, and it is obvious that a person skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the concept and scope of the present application. If such changes and modifications fall within the scope of the claims and equivalent technical solutions of this application, the description of this application also includes such changes and modifications.

1: Substrate 3: Redistribution layer
4: Passivation layer 5: Electrode structure
10: Recess 21, 22: Package element
21a: second package element 22a, 23a: first package element
31: second electrode 32: third electrode
33: Traces 111, 112: Insulating material
211, 221: first pad 221a, 231a: first pad
211a: Second electrode structure

Claims (48)

In the semiconductor package structure,
It includes a substrate, at least one package element, a redistribution layer, and a passivation layer, wherein at least one recess is opened in the substrate, and the package element is fixed in a one-to-one correspondence within the recess;
The active surface of the package element faces away from the substrate, the package element and the recess where the package element is located are separated by an insulating material, and each of the package elements has a first pad located on the active surface. wherein the surfaces of all of the first pads facing away from the substrate are on the same plane;
The redistribution layer is located on a side of the package device that faces away from the substrate, a plurality of second pads are formed on a first side of the redistribution layer, and a plurality of second pads are formed on a second side of the redistribution layer facing the first side. A third pad is formed, the second pad is in electrical contact with the first pad in a one-to-one correspondence, the redistribution layer further includes a trace electrically connecting the second pad and the third pad, and the The conductors in the wiring layer are separated from each other by a polymer or molding compound, and the first surface of the redistribution layer has an area covering the surface of all of the first pads facing away from the substrate;
the passivation layer is located on a side of the redistribution layer that faces away from the substrate;
Here, the substrate is formed of a semiconductor material or an insulating material, and the thermal expansion coefficient of the substrate and the semiconductor material in the package element is the same or close to the semiconductor package structure. According to paragraph 1,
A semiconductor package structure, characterized in that the semiconductor material in the substrate and the semiconductor material in the package element are the same. According to paragraph 1,
A semiconductor package structure, wherein the semiconductor material in the package element is silicon or gallium arsenide, and the material of the substrate is engineering heat-resistant glass. According to paragraph 1,
A semiconductor package structure, characterized in that the number of package elements is plural, the thickness is the same, and the depth of each recess is the same. According to paragraph 1,
The quantity of the package elements is plural, and the thickness of the at least two package elements is different, wherein the depth of the at least two recesses is different, such that the upper surface of the first pad of each of the package elements is on the same plane. A semiconductor package structure characterized by: According to paragraph 1,
It further includes an electrode structure located on a side of the passivation layer facing away from the substrate, wherein a through via is opened in an area facing the third pad on the passivation layer, and the electrode structure corresponds one to one with the third pad. , The electrode structure is electrically connected to the corresponding third pad through the through via. According to paragraph 1,
A semiconductor package structure, wherein the package element is in a bare chip state. According to paragraph 1,
A semiconductor package structure, characterized in that the package element and the groove bottom of the recess are separated by an insulating adhesive layer. According to paragraph 1,
A semiconductor package structure, characterized in that the package element and the side of the recess are separated by a cured resin material or an inorganic insulating material. delete In the semiconductor packaging method,
forming at least one recess in the substrate;
Fixing at least one package element in one-to-one correspondence within the recess, wherein the active surface of the package element faces away from the substrate, and the package element and the recess in which the package element is located are separated by an insulating material. wherein each of the package elements has a first pad located on an active surface, and the surfaces of all of the first pads facing away from the substrate are on the same plane;
forming a planar surface exposing the first pad;
A redistribution layer is formed, wherein a plurality of second pads are formed on a first side of the redistribution layer, a plurality of third pads are formed on a second side of the redistribution layer facing the first side, and the second pad is formed on a second side of the redistribution layer. The pad is in electrical contact with the first pad in one-to-one correspondence, the redistribution layer further includes a trace electrically connecting the second pad and the third pad, and a polymer or molding compound is formed between the conductors in the redistribution layer. is separated by, and the first surface of the redistribution layer has an area covering the surface of all the first pads facing away from the substrate;
It includes forming a passivation layer,
Here, the substrate is formed of a semiconductor material or an insulating material, and the thermal expansion coefficient of the substrate and the semiconductor material in the package element is the same or close to the semiconductor packaging method. According to clause 11,
A semiconductor packaging method, characterized in that the semiconductor material in the substrate and the semiconductor material in the package element are the same. According to clause 11,
A semiconductor packaging method, wherein the semiconductor material in the package element is silicon or gallium arsenide, and the material of the substrate is engineering heat-resistant glass. According to clause 11,
The quantity of the package elements is plural, the depth of the recess in which each of the package elements is located is the same, and the method involves thinning at least some of the package elements so that the thickness of each of the package elements is the same. A semiconductor packaging method, characterized in that it further comprises the step of: According to clause 11,
The number of the package elements is plural, the thickness of at least two of the package elements is different, and when forming a recess in the substrate, the upper surface of the first pad of each of the package elements is on the same plane, at least two A semiconductor packaging method, characterized in that the depths of the recesses are different. According to clause 11,
The step of fixing at least one package element in one-to-one correspondence within the recess,
forming an insulating adhesive layer on the bottom of the groove of the recess;
Attaching the package element to the insulating adhesive layer; Here, an air gap is provided between the package element and a side of the recess;
A semiconductor packaging method comprising: filling an insulating material between the package element and the side of the corresponding recess. According to clause 16,
The step of filling an insulating material between the package element and the side of the corresponding recess,
Comprising the step of filling and curing a resin material between the package element and the side of the corresponding recess, or depositing an inorganic oxide insulating material into the gap between the package element and the side of the corresponding recess. , semiconductor packaging method. According to clause 11,
Forming a flat surface exposing the first pad includes:
A semiconductor packaging method comprising removing an insulating material and a substrate material higher than the first pad through a grinding process and then performing surface treatment. According to clause 11,
forming at least one through via in the passivation layer one-to-one corresponding to the third pad, and exposing the third pad to which the through via corresponds;
A semiconductor packaging method further comprising forming an electrode structure in electrical contact with the third pad. According to claim 11 or 19,
It further includes obtaining a plurality of semiconductor package structures through a cutting process, wherein each semiconductor package structure includes at least one of the package elements, a recess in which the included package elements are located, and an electrical connection with the included package elements. A semiconductor packaging method comprising a redistribution layer connected to and a passivation layer on top of the included redistribution layer. delete According to clause 11,
A semiconductor packaging method, wherein the package element is in a bare chip state. In the semiconductor package structure,
It includes a substrate, at least one first package element, at least one second package element, a redistribution layer, and a passivation layer, wherein at least one first recess and at least one second recess are opened in the substrate, 1 package element is fixed in a one-to-one correspondence within the first recess, the second package element is fixed in a one-to-one correspondence within the second recess, the first package element is in a bare chip state, and the second package element has a second electrode structure that is exposed to the outside while being in a package state;
The active surface of the first package element faces away from the substrate, the first package element and the first recess where the first package element is located are separated by an insulating material, and the second package element and the first recess are separated from each other by an insulating material. A second recess in which two package elements are located is separated by an insulating material, each of the first package elements has a first pad located on an active surface, and all of the first pads are connected to the substrate. The backing surface and the substrate facing surface of all second electrode structures are on the same plane;
The redistribution layer is located on a side of the package device that faces away from the substrate, a plurality of second pads are formed on a first side of the redistribution layer, and a plurality of second pads are formed on a second side of the redistribution layer facing the first side. A third pad is formed, the first pad is in electrical contact with some of the second pads in a one-to-one correspondence, the second electrode structure is in electrical contact with the remaining second pads in a one-to-one correspondence, and the redistribution layer is It further includes a trace electrically connecting the second pad and the third pad, and a trace electrically connecting the second pad and the second electrode structure, and the conductors in the redistribution layer are separated by a polymer or molding compound. , the first surface of the redistribution layer is a surface facing away from the substrate of all the first pads of the at least one first package element and a surface facing away from the substrate of all the second electrode structures of the at least one second package element. has an area covering;
the passivation layer is located on a side of the redistribution layer that faces away from the substrate;
Here, the substrate is formed of a semiconductor material or an insulating material, and the thermal expansion coefficient of the substrate and the semiconductor material in the package element is the same or close to the semiconductor package structure. According to clause 23,
A semiconductor package structure, characterized in that the semiconductor material in the substrate and the semiconductor material in the package element are the same. According to clause 23,
A semiconductor package structure, wherein the semiconductor material in the package element is silicon or gallium arsenide, and the material of the substrate is engineering heat-resistant glass. According to clause 23,
A semiconductor package structure, wherein the number of first package elements is plural, the thickness is the same, and the depth of each first recess is the same. According to clause 23,
The quantity of the first package elements is plural, and the thickness of the at least two first package elements is different, wherein the upper surface of the first pad of each of the first package elements is on the same plane. A semiconductor package structure, characterized in that the depth of the first recess is different. According to clause 23,
It further includes a first electrode structure located on a side of the passivation layer facing away from the substrate, wherein a through via is opened in an area facing the third pad on the passivation layer, and the first electrode structure is connected to the third pad. A semiconductor package structure having a one-to-one correspondence with a semiconductor package structure, wherein the first electrode structure is electrically connected to the corresponding third pad through the through via. According to clause 23,
Characterized in that the first package element and the groove bottom of the first recess are separated by an insulating adhesive layer, and the second package element and the groove bottom of the second recess are separated by an insulating adhesive layer. Semiconductor package structure. According to clause 23,
Between the first package element and the side of the first recess is separated by a cured resin material or an inorganic insulating material, and between the second package element and the side of the second recess is separated by a cured resin material or an inorganic insulating material. A semiconductor package structure characterized by being separated by material. delete According to clause 23,
A semiconductor package structure, wherein the second package element is a surface-mounted package or a ceramic package. In the semiconductor packaging method,
forming at least one first recess and at least one second recess in the substrate;
Fixing at least one first package element in a one-to-one correspondence within the first recess, and fixing at least one second package element in a one-to-one correspondence within the second recess, wherein the first package element is a bare chip. state, the second package element has a second electrode structure exposed to the outside while in a package state, the active surface of the first package element faces away from the substrate, and the first package element and the first package element The first recess in which is located is separated by an insulating material, and the second package element and the second recess in which the second package element is located are separated by an insulating material, and each of the first package elements all have first pads located on the active surface, and the surfaces facing away from the substrate of all of the first pads and of all of the second electrode structures are coplanar;
forming a flat surface exposing the first pad and the second electrode structure;
A redistribution layer is formed, wherein a plurality of second pads are formed on a first side of the redistribution layer, a plurality of third pads are formed on a second side of the redistribution layer facing the first side, and the first The pad is in electrical contact with some of the second pads in a one-to-one correspondence, the second electrode structure is in electrical contact with the remaining second pads in a one-to-one correspondence, and the redistribution layer electrically connects the second pad and the third pad. further comprising a trace and a trace electrically connecting the second pad and the second electrode structure, wherein the conductor in the redistribution layer is separated from the conductor by a polymer or molding compound, and the first surface of the redistribution layer is at least having an area covering a substrate-facing surface of all first pads of one first package element and a substrate-facing surface of all second electrode structures of the at least one second package element;
It includes forming a passivation layer,
Here, the substrate is formed of a semiconductor material or an insulating material, and the thermal expansion coefficient of the substrate and the semiconductor material in the package element is the same or close to the semiconductor packaging method. According to clause 33,
A semiconductor packaging method, characterized in that the semiconductor material in the substrate and the semiconductor material in the package element are the same. According to clause 33,
A semiconductor packaging method, wherein the semiconductor material in the package element is silicon or gallium arsenide, and the material of the substrate is engineering heat-resistant glass. According to clause 33,
The number of the first package elements is plural, the depth of the first recess in which each of the first package elements is located is the same, and the method includes performing thinning on at least some of the first package elements, A semiconductor packaging method, characterized in that it further comprises the step of ensuring that the thickness of the first package element is the same. According to clause 33,
At least two of the first package element and the second package element have different thicknesses, and when the first recess and the second recess are formed on the substrate, the first recess of each of the first package element A method of packaging a semiconductor, wherein the depths of the at least two recesses are different, such that the top surface of the pad and the top surface of each second electrode structure are on the same plane. According to clause 33,
The step of fixing at least one first package element in one-to-one correspondence within the first recess,
forming an insulating adhesive layer on the bottom of the groove of the first recess;
attaching the first package element to the insulating adhesive layer; Here, an air gap is provided between the first package element and a side surface of the first recess;
A semiconductor packaging method comprising: filling an insulating material between the first package element and a side of the corresponding first recess. According to clause 38,
The step of filling an insulating material between the first package element and the side of the corresponding first recess,
Filling and curing a resin material between the side of the first recess corresponding to the first package element, or depositing an inorganic oxide insulating material into the gap between the side of the first recess corresponding to the first package element. A semiconductor packaging method, comprising the steps: According to clause 33,
The step of fixing at least one second package element in one-to-one correspondence within the second recess,
forming an insulating adhesive layer on the bottom of the groove of the second recess;
attaching the second package element to the insulating adhesive layer; Here, an air gap is provided between the second package element and a side surface of the second recess;
A semiconductor packaging method comprising: filling an insulating material between the second package element and a side of the corresponding second recess. According to clause 40,
The step of filling an insulating material between the second package element and the side of the corresponding second recess,
Filling and curing a resin material between the side of the second recess corresponding to the second package element, or depositing an inorganic oxide insulating material into the gap between the side of the second recess corresponding to the second package element. A semiconductor packaging method, comprising the steps: According to clause 33,
Forming a flat surface exposing the first pad and the second electrode structure includes:
A semiconductor packaging method comprising removing an insulating material and a substrate material higher than the first pad and the second electrode structure through a grinding process, and then performing surface treatment. According to clause 33,
forming a plurality of through vias in the passivation layer one-to-one corresponding to the third pad, and exposing the corresponding third pad to the through via;
A semiconductor packaging method further comprising forming a first electrode structure in electrical contact with the third pad. According to claim 33 or 43,
Further comprising obtaining a plurality of semiconductor package structures through a cutting process, wherein each semiconductor package structure includes at least one first package element, at least one second package element, and the first package element. Includes a first recess in which is located, a second recess in which the second package element is located, a redistribution layer electrically connected to the first package element and the second package element, and a passivation layer on top of the redistribution layer. A semiconductor packaging method, characterized in that. delete According to clause 33,
A semiconductor packaging method, wherein the second package element is a surface-mounted package or a ceramic package. In semiconductor devices,
A semiconductor comprising the semiconductor package structure according to any one of claims 1 to 9, or comprising the semiconductor package structure according to any one of claims 23 to 30 and 32. device. In electronic products,
An electronic product comprising a semiconductor device according to claim 47.