KR102615995B1 - Display device - Google Patents

Abstract

The object of the present invention is to provide a display device that can prevent deterioration of the gate driver by applying a gradually increasing compensation voltage to the QB node. A display device according to the present invention includes a display panel, a gate driver mounted on the display panel and outputting a gate voltage, a power control section that outputs a compensation voltage to the gate driver, and a feedback line connecting the gate driver and the power control section. Includes, and feeds back the QB voltage through the feedback line to adjust the compensation voltage.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device, and particularly to a display device that can prevent deterioration of a gate driver and a method of driving the same.

A typical liquid crystal display device displays images by adjusting the light transmittance of liquid crystals with dielectric anisotropy using an electric field. For this purpose, the liquid crystal display device includes a liquid crystal display panel in which pixel areas are arranged in a matrix form and a driving unit for driving the liquid crystal display panel.

In the liquid crystal display panel, a plurality of gate lines and a plurality of data lines are arranged to intersect, and the pixel area is located in an area defined by the vertical intersection of the gate lines and data lines. Then, pixel electrodes and a common electrode are formed to apply an electric field to each of the pixel areas. Each of the pixel electrodes is connected to a thin film transistor (TFT), which is a switching element. The thin film transistor is turned on by the gate voltage of the gate line, allowing the data signal of the data line to charge the pixel electrode.

The gate driver includes a shift register to sequentially output gate voltages. The shift register consists of multiple stages that are dependently connected to each other. Multiple stages sequentially output gate voltages to sequentially scan the gate lines of the liquid crystal display panel. The gate driver may be formed in the form of a GIP (Gate In Panel) embedded in a thin film transistor array substrate forming a liquid crystal display panel.

Figure 1 is a diagram showing the equivalent circuit of each stage of a conventional shift register.

As shown in Figure 1, each stage includes a seventh transistor (Tr7) that pulls up the gate voltage (Vg) and an eighth transistor (Tr8) that pulls down the gate voltage (Vg). and a plurality of transistors (Tr1 to Tr6) that control it.

That is, the first to third transistors (Tr1 to Tr3) control the voltage level of the Q node (Q), which is the gate of the seventh transistor (Tr7), and the fourth to sixth transistors (Tr4 to Tr6) control the voltage level of the Q node (Q), which is the gate of the seventh transistor (Tr7). 8 Controls the voltage level of the QB node (QB), which is the gate of the transistor (Tr8). Additionally, the stage receives two levels of voltage, a high potential voltage (VDD) and a low potential voltage (VSS), and outputs a gate voltage (Vg).

Here, the fourth transistor (Tr4) serves to pull up the QB node (QB). As a result, the third transistor (Tr3) whose gate is the QB node (QB) is deteriorated and the threshold voltage increases. Accordingly, the voltage applied to the QB node (QB) increases, which ultimately leads to a decrease in reliability of the third transistor (Tr3). Therefore, it becomes difficult to control the Q node (Q) corresponding to the drain of the third transistor (Tr3), which causes the gate voltage (Vg) to be output abnormally.

Moreover, recently, transistors applied to high-resolution product lines use oxide thin-film transistors (Oxide TFTs) to increase electron mobility. Oxide thin film transistors (Oxide TFT) have poorer degradation characteristics than amorphous silicon thin film transistors (a-si TFT). Accordingly, the above-described problems become more prominent and control of the gate voltage (Vg) becomes difficult.

The object of the present invention is to provide a display device that can prevent deterioration of the gate driver by applying a gradually increasing compensation voltage to the QB node.

The display device according to the present invention includes a display panel, a gate driver, a power control unit, and a feedback line.

The gate driver is mounted on the display panel and outputs a gate voltage.

The power control unit outputs a compensation voltage to the gate driver.

The feedback line connects the gate driver and the power control unit, and feeds back the QB voltage through the feedback line to adjust the compensation voltage.

As the amount of increase in the QB voltage decreases and the QB voltage gradually increases, the stress on the transistor whose gate is the QB node to which the QB voltage is applied is reduced, thereby reducing the degree of deterioration. Accordingly, the reliability of the transistor increases, ultimately improving the reliability of the gate driver in the form of a GIP (Gate In Panel).

Figure 1 is a diagram showing the equivalent circuit of each stage of a conventional shift register.
Figure 2 is a diagram showing a display device according to an embodiment of the present invention.
FIG. 3 is a diagram showing a power control unit of a display device according to an embodiment of the present invention, and FIG. 4 is a diagram showing the power compensation unit shown in FIG. 3.
Figure 5 is a diagram showing a shift register of a display device according to an embodiment of the present invention.
Figure 6 is a diagram showing an equivalent circuit of a dummy stage according to an embodiment of the present invention.
FIG. 7A is a graph showing the high potential voltage and QB voltage of a conventional display device, and FIGS. 7B and 7C are graphs and tables showing the compensation voltage and QB voltage of a display device according to an embodiment of the present invention.

Hereinafter, a display device according to an embodiment of the present invention will be described in detail with reference to the attached drawings.

Figure 2 is a diagram showing a display device according to an embodiment of the present invention.

As shown in FIG. 2, the display device 100 according to an embodiment of the present invention includes a display panel 110, gate/data drivers 123 and 125 that drive the display panel 110, and gate/data drivers 123 and 125. It includes a timing control unit 131 that controls and a power control unit 133 that supplies each driving power.

The display panel 110 has a plurality of gate lines (GL) and a plurality of data lines (DL) intersecting each other in a matrix form on a substrate (not shown) made of glass or plastic. And a number of pixels (not shown) are defined at the intersection of the gate line (GL) and the data line (DL). Additionally, a common electrode (not shown) may be disposed opposite to the pixel electrode (not shown) of the pixel.

Each of the plurality of pixels may include a thin film transistor (not shown) and a liquid crystal capacitor (not shown). The thin film transistor has a gate electrode connected to the gate line (GL), a source electrode connected to the data line (DL), and a drain electrode connected to the pixel electrode. The thin film transistor is turned on by the gate voltage (Vg) provided through the gate line (GL), and transmits the data voltage provided through the data line (DL) to the pixel electrode. In a liquid crystal capacitor, the data voltage provided to the pixel electrode through a thin film transistor and the common voltage applied to the common electrode form an electric field, which changes the arrangement of the liquid crystals and adjusts the light transmittance to display an image.

The display device 100 according to an embodiment of the present invention will be described focusing on the liquid crystal display device, but the display device 100 is not limited thereto and may include an organic light emitting display device (OLED display), an electrophoretic display device (EPD), and a plasma display device. It can be implemented based on a flat display panel such as a display panel (PDP).

The timing control unit 131 receives a timing signal (not shown) transmitted from an external system (not shown) and generates a gate control signal (GCS) and a data control signal (DCS). The gate control signal (GCS) is output to the gate driver 123, and the data control signal (DCS) is output to the data driver 125 through the EPI wire pair. Here, the timing signal may be a data enable signal (DE), a horizontal synchronization signal (Hsync), a vertical synchronization signal (Vsync), and a clock signal (CLK). Additionally, the timing control unit 131 generates image data (RGB) in digital form from an image signal (not shown) transmitted from an external system and outputs it to the data driver 125 through an EPI wire pair.

FIG. 3 is a diagram showing a power control unit of a display device according to an embodiment of the present invention, and FIG. 4 is a diagram showing the power compensation unit shown in FIG. 3.

The power control unit 133 includes a power conversion unit 133a that outputs a high potential voltage (VDD) and a low potential voltage (VSS), and a power compensation unit 133b that outputs a compensation voltage (VFB).

The power conversion unit 133a converts the external voltage (VCC) input from the outside into high potential voltage (VDD) and low potential voltage (VSS), which are standard power sources used inside the display device 100, and outputs them. The power conversion unit 133a includes a voltage amplifier (not shown) and outputs external power (VCC) as a high potential voltage (VDD) and a low potential voltage (VSS).

As will be described later, the power compensation unit 133b outputs a compensated compensation voltage (VFB) to the gate driver 123 using the QB voltage (VQB) applied from the gate driver 123 through the feedback line (FL). Here, the QB voltage (VQB) increases over time. Accordingly, the compensation voltage (VFB) compensated using the increasing QB voltage (VQB) also increases over time. Eventually, the compensation voltage (VFB) increases to the level of the high potential voltage (VFB). That is, the compensation voltage (VFB) is less than or equal to the high potential voltage (VDD).

More specifically, as shown in FIG. 4, the power compensation unit 133b may be composed of a differential amplifier (OP-AMP). A high potential voltage (VDD) is applied to the inverting terminal of the differential amplifier (OP-AMP) through the first resistor (R1), and the QB voltage (VQB) is applied to the non-inverting terminal of the differential amplifier (OP-AMP). The voltage is distributed and applied to the third resistor (R3) and the fourth resistor (R4). The compensation voltage (VFP) output from the differential amplifier (OP-AMP) is as shown in Equation 1.

[Equation 1]

As can be seen in Equation 1, the compensation voltage (VFB) is proportional to the QB voltage (VQB). Therefore, the compensation voltage (VFB) is not fixed to the high potential voltage (VDD) as in the prior art, but is gradually increased according to the QB voltage (VQB), thereby reducing the increase rate of the QB voltage (VQB). Accordingly, deterioration due to stress of the third transistor Tr3 to which the QB voltage VQB is applied can be reduced. Accordingly, the reliability of the gate driver 123 in the form of a GIP (Gate In Panel) can be improved.

The data driver 125 converts digital image data (RGB) provided from the timing control unit 131 through the EPI wire pair into an analog data voltage according to the data control signal (DCS). Then, the data driver 125 applies the analog data voltage to the pixel electrode of each pixel through the data line DL.

Additionally, the data control signal (DCS) includes a source start pulse (SSP), a source shift clock (SSC), and a source output enable signal (SOE). The source start pulse (SSP) determines the sampling start timing of the image data (RGB) of the data driver 125. The source shift clock (SSC) is a clock signal that controls the data sampling operation in the data driver 125. The source output enable signal (SOE) controls the output of the data driver 125.

The gate driver 123 may sequentially output the gate voltage Vg by one horizontal period through the gate line GL in response to the gate control signal GCS provided from the timing control unit 131. Accordingly, the thin film transistor connected to each gate line GL is turned on for one horizontal period. Here, the gate driver 123 may be composed of a plurality of shift registers (not shown) connected to a plurality of gate lines GL, and may be configured in the form of a GIP (Gate In Panel) mounted inside the display panel 110. there is.

Here, the gate control signal (GCS) includes a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable signal (GOE). The gate start pulse (GSP) is a signal that determines when to output the gate voltage (Vg) to the first gate line (GL1) and is applied to the shift register of the gate driver 123. The gate shift clock (CLK) is commonly applied to each shift register and is a clock signal that enables the next shift register (not shown). The gate output enable signal (GOE) controls the output of the shift register.

Figure 5 is a diagram showing a shift register of a display device according to an embodiment of the present invention.

The shift register is a first to nth stage (S1 to Sn) that sequentially outputs gate voltages (Vg1 to Vgn) in response to the gate shift clock (CLK) and gate start pulse (GSP) provided from the timing control unit 131. and a dummy stage (Sd) that does not output the gate voltage (Vg). At this time, each stage (S1 ~ Sn) outputs the gate voltage (Vg1 ~ Vgn) once every frame, and sequentially outputs the gate voltage (Vg1 ~ Vgn) from the first stage (S1) to the nth stage (Sn). do.

Each of the first to nth stages (S1 to Sn) receives the gate voltage (Vg) of the previous stage and uses it to output high-level gate voltages (Vg1 to Vgn), and uses the gate voltage (Vg1 to Vgn) of the next stage. Vgn) is supplied and used to output low-level gate voltage (Vg1 ~ Vgn). However, since the first stage (S1) does not have a previous stage, it receives a gate start pulse (GSP) from the timing control unit 131. Additionally, the nth stage (Sn) outputs low-level gate voltages (Vg1 to Vgn) in response to the dummy voltage (Vd) provided from the dummy stage (Sd).

Here, the dummy stage (Sd) receives the gate voltage (Vg) of the n-th stage (Sn), but does not output the gate voltage (Vg) like the first to n-th stages (S1 to Sn). As will be described later, the feedback line (FL) is connected to the QB node (QB) of the dummy stage (Sd), and the QB voltage (VQB) is input to the power control unit 133 through this. By connecting the feedback line (FL) to the dummy stage (Sd) in this way, the QB voltage (VQB) can be used to compensate for the compensation voltage (VFB) without any effect on the output of the gate voltage (Vg).

Figure 6 is a diagram showing an equivalent circuit of a dummy stage according to an embodiment of the present invention.

The transistors to be described later will be explained based on NMOS, but are not limited to this and may be composed of various types of transistors such as PMOS and COMS.

As shown in FIG. 4, the dummy stage (Sd) includes an output unit (P3) that outputs a dummy voltage (Vd) to the n-th stage (Sn), and a first control unit (P1) that controls the output unit (P3). and a second control unit (P2).

The output unit (P3) includes a seventh transistor (Tr7), which is a transistor that pulls up the dummy voltage (Vd), and an eighth transistor (Tr8), which is a transistor that pulls down the dummy voltage (Vd). Includes.

Here, the seventh transistor (Tr7) is a pull-up transistor in which the Q node (Q) is connected to the gate, the gate shift clock (CLK) as an input is applied to the drain, and the dummy voltage (Vd) is output from the source. am. The seventh transistor (Tr7) is turned on or turned off according to the logic state of the Q node (Q), and when turned on, the gate shift clock (CLK) is turned on to the dummy voltage ( It outputs as Vd).

And, the eighth transistor (Tr8) has a QB node (QB) connected to the gate, a low potential voltage (VSS) as an input is applied to the drain, and a dummy voltage (Vd) is output from the source. It's a transistor. The eighth transistor Tr8 is turned on or turned off depending on the logic state of the QB node (QB), and when turned on, the low potential voltage (VSS) is changed to the dummy voltage ( It outputs as Vd).

The first control unit (P1) controls the voltage applied to the Q node (Q) and includes a first transistor (Tr1), a second transistor (Tr2), and a third transistor (Tr3).

Here, the nth gate voltage (Vgn) is applied to the gate of the first transistor (Tr1), the high potential voltage (VDD), which is an input, is applied to the drain, and the Q node (Q) is connected to the source. The first transistor (Tr1) is turned on or turned off according to the logic state of the n-th gate voltage (Vgn), and when turned on, the high potential voltage (VDD) is converted to Q. It is output as the voltage applied to the node (Q).

The gate start pulse (NEXT) of the next frame is applied to the gate of the second transistor (Tr2), the input low potential voltage (VSS) is applied to the drain, and the Q node (Q) is connected to the source. The second transistor (Tr2) is turned on or turned off according to the logic state of the gate start pulse (NEXT) of the next frame, and when turned on, the low potential voltage (VSS) is output as the voltage applied to the Q node (Q).

The third transistor Tr3 has a QB node (QB) connected to its gate, an input low potential voltage (VSS) applied to its drain, and a Q node (Q) connected to its source. The third transistor (Tr3) is turned on or turned off according to the logic state of the QB voltage (VQB) applied to the QB node (QB), and has a low potential when turned on. The voltage (VSS) is output as the voltage applied to the Q node (Q).

The second control unit (P2) controls the QB voltage (VQB) applied to the QB node (QB) and includes a fourth transistor (Tr4), a fifth transistor (Tr5), and a sixth transistor (Tr6).

Here, the gate and drain of the fourth transistor (Tr4) are connected to receive a compensation voltage (VFB), and the QB node (QB) is connected to the source. The fourth transistor (Tr4) outputs the compensation voltage (VFB) as the QB voltage (VQB) applied to the QB node (QB).

The nth gate voltage (Vgn) is applied to the gate of the fifth transistor (Tr5), the input low potential voltage (VSS) is applied to the drain, and the QB node (QB) is connected to the source. The fifth transistor (Tr5) is turned on or turned off according to the logic state of the n-th gate voltage (Vgn), and when turned on, the low potential voltage (VSS) is connected to QB. It is output as the QB voltage (VQB) applied to the node (QB).

The sixth transistor Tr6 has a Q node (Q) connected to the gate, an input low potential voltage (VSS) applied to the drain, and a QB node (QB) connected to the source. The sixth transistor (Tr6) is turned on or turned off according to the logic state of the voltage applied to the Q node (Q), and when turned on, the low potential voltage (VSS) is output as the QB voltage (VQB) applied to the QB node (QB).

Then, a feedback line (FL) is connected to the QB node (QB), and the QB voltage (QB) applied to the QB node (QB) through the feedback line (FL) is output to the power control unit 133. As described above, the compensation voltage (VFB) can be compensated using the QB voltage (QB). Hereinafter, the effects of the display device according to an embodiment of the present invention will be described in detail.

FIG. 7A is a graph showing the high potential voltage and QB voltage of a conventional display device, and FIGS. 7B and 7C are graphs and tables showing the compensation voltage and QB voltage of a display device according to an embodiment of the present invention.

As shown in FIG. 7A, the conventional display device typically applies a high potential voltage (VDD) corresponding to 25V to the fourth transistor (Tr4), and as described above, the stress of the third transistor (Tr3) causes Due to deterioration, the QB voltage (VQB) also increases. As the QB voltage (VQB) increases, the reliability of the third transistor (Tr3) decreases, which leads to a decrease in the reliability of the gate driver 123 in the form of a GIP (Gate In Panel).

On the other hand, in the display device according to the embodiment of the present invention, as shown in FIGS. 7B and 7C, the compensation voltage (VFB) applied to the fourth transistor (Tr4) gradually increases from 9.8V over time. and finally rises to 25V, which is the high potential voltage (VDD). That is, the compensation voltage (VFB) is less than or equal to the high potential voltage (VDD). The QB voltage (VQB) applied to the QB node (QB) also gradually increases over time from -11.5V to -9.8V. The reason why the compensation voltage (VFB) and the QB voltage (VQB) gradually increase in this way is because the compensation voltage (VFB) is compensated using the QB voltage (VQB) through the feedback line (FL).

In this way, the amount of increase in the QB voltage (VQB) decreases and gradually increases, thereby reducing the stress of the third transistor (Tr3) whose gate is the QB node (QB) to which the QB voltage (VQB) is applied, thereby reducing the degree of degradation. Accordingly, the reliability of the third transistor (Tr3) increases, ultimately improving the reliability of the gate driver 123 in the form of a GIP (Gate In Panel).

Although many details are described in detail in the foregoing description, this should be interpreted as an example of a preferred embodiment rather than limiting the scope of the invention. Therefore, the invention should not be determined by the described embodiments, but by the scope of the patent claims and their equivalents.

100: display device 110: display panel
123: Gate driving unit 131: Timing control unit
133: Power control unit 133a: Power conversion unit
133b: Power compensation unit Sd: Dummy stage
Q: Q node QB: QB node
FL: Feedback Line

Claims (9)

display panel;
a gate driver mounted on the display panel to output a gate voltage;
a power control unit that outputs a compensation voltage to the gate driver; and
It includes a feedback line connecting the gate driver and the power control unit,
The compensation voltage is adjusted by feeding back the QB voltage through the feedback line,
The power control unit includes a power compensation unit that receives the QB voltage and outputs the compensation voltage,
The power compensation unit,
a differential amplifier having an inverting terminal, a non-inverting terminal, and an output terminal for outputting the compensation voltage;
a first resistor connected between the inverting terminal and a high potential voltage;
a second resistor connected between the inverting terminal and the output terminal;
a third resistor connected between the non-inverting terminal and the QB voltage;
A display device including a fourth resistor connected between the non-inverting terminal and a ground voltage. According to paragraph 1,
The gate driver includes a shift register in which a plurality of stages are cascaded,
The plurality of stages include dummy stages,
The feedback line is a display device connecting the dummy stage and the power control unit. According to paragraph 2,
The dummy stage is,
According to the Q node, a seventh transistor that pulls up the gate voltage and
Depending on the QB node, it includes an eighth transistor that pulls down the gate voltage,
The feedback line is a display device connected to the QB node. According to paragraph 3,
The plurality of stages are,
It includes a fourth transistor that pulls up the QB voltage applied to the QB node,
A display device in which the compensation voltage is applied to a fourth transistor. According to paragraph 1,
The power control unit,
A display device further comprising a power conversion unit that receives external power and outputs the high potential voltage and the low potential voltage. delete According to paragraph 1,
The display device wherein the level of the compensation voltage is lower than the level of the high potential voltage. According to paragraph 1,
A display device in which the level of the compensation voltage gradually increases and converges to the level of the high potential voltage. According to paragraph 1,
A display device in which the compensation voltage is determined by Equation 1 below.
[Equation 1]

(VFB is compensation voltage, VQB is QB voltage, VDD is high potential voltage, R1 to R4 are first to fourth resistors)