KR101713218B1 - Gate driver - Google Patents

Abstract

A gate driver is started. The gate driver includes a shift register, a level shifter, and a buffer. The buffer further includes a first transistor and a second transistor of the opposite polarity, to which the same signal input terminal is commonly connected to the gate and the drain is connected to each other, And a third transistor having a gate connected to a first intermediate voltage supply end for supplying a first intermediate voltage between a maximum value and a minimum value of the buffer driving voltage and having the same polarity as the polarity of the first transistor. This configuration eliminates the need for a separate control circuit for controlling the gate pulse modulation or the separate current route or gate pulse modulation circuit, so that the feedthrough voltage (DELTA Vp) can be effectively .

Description

Gate driver {GATE DRIVER}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for driving a display device, and more particularly, to a circuit for driving a display device by removing a feed through voltage (DELTA Vp) by adjusting a slope of rising and falling of a gate driver scanning signal .

1 is a diagram showing a pixel structure of a liquid crystal flat panel display device. 1, the voltage charged in the liquid crystal cell in the active matrix type liquid crystal display device is influenced by the feedthrough voltage? Vp generated due to the parasitic capacitance of the TFT (Thin Film Transistor). The feedthrough voltage (Vp) can be expressed by the following equation.

Here, Cgd is the parasitic capacitance formed between the gate terminal of the TFT connected to the gate line and the drain terminal of the TFT connected to the pixel electrode of the liquid crystal cell, and (VGH-VGL) is the gate- And a difference voltage between the voltage and the gate low voltage.

However, such a feedthrough voltage (? Vp) causes fluctuations in the voltage applied to the pixel electrode of the liquid crystal cell, resulting in flicker, afterimage, color deviation, and the like in the display image. A gate pulse modulation method of modulating the gate high voltage VGH at the polling edge of the gate pulse in order to reduce this feedthrough voltage DELTA Vp is widely used.

Fig. 2 is a diagram showing an example of a conventional gate pulse modulation circuit, and Fig. 3 is a diagram showing a gate scan waveform. The gate high voltage VGH is lowered at the poling edge of the gate pulse as shown in the waveform diagram of FIG. 3 where the gate pulse is not modulated and the gate pulse is modulated.

However, in order to lower the gate high voltage (VGH) by a desired voltage, there arises a problem that the current consumption increases and a circuit area increases in order to implement a gate modulation circuit.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a gate driver capable of effectively reducing a feed-through voltage even with low power consumption and a small circuit area.

In order to achieve the above object, a gate driver according to the present invention includes a shift register, a level shifter, and a buffer, and the buffer further includes a first transistor of the opposite polarity to which the same signal input is commonly connected to the gate, A drain connected to the source of the first transistor, a second transistor and a source of the first transistor, and a first intermediate voltage supply end connected to the gate for supplying a first intermediate voltage between a maximum value and a minimum value of the buffer driving voltage, Polarity third transistor.

This configuration effectively eliminates the feedthrough voltage (DELTA Vp) with low power consumption and low circuit area because no separate control circuit is needed to perform the gate pulse modulation or separate current route or gate pulse modulation. .

In this case, a drain is connected to the source of the second transistor, a second intermediate voltage supply terminal for supplying a second intermediate voltage between the maximum value and the lowest value of the buffer driving voltage is connected to the gate, And a fourth transistor of the second transistor. According to this configuration, it is possible to drive the gate regardless of the polarity of the panel element driven by the gate driver.

The liquid crystal display may further include a fifth transistor having a drain connected to the drains of the first transistor and the second transistor, and a source connected to the source of the third transistor. According to this configuration, the modulation period of the gate drive pulse can be adjusted more precisely.

The organic electroluminescent device may further include a sixth transistor having a drain connected to the drains of the first transistor and the second transistor, and a source connected to the source of the fourth transistor. According to this configuration, the modulation period of the gate drive pulse can be adjusted more precisely regardless of the polarity of the panel element driven by the gate driver.

A third intermediate voltage supply terminal is connected to the source of the third transistor and supplies a third intermediate voltage between the maximum value and the minimum value of the buffer drive voltage to the gate. And a seventh transistor of the second transistor. With this configuration, the modulation size of the gate drive pulse can be adjusted more precisely.

A drain of the fourth transistor is connected to the drain of the fourth transistor, and a fourth intermediate voltage supply terminal for supplying a fourth intermediate voltage between a maximum value and a minimum value of the buffer driving voltage is connected to the gate. 8 < / RTI > transistors. According to this configuration, the modulation magnitude of the gate drive pulse can be adjusted more precisely regardless of the polarity of the panel element driven by the gate driver.

According to the present invention, a separate current route for gate pulse modulation and a separate control circuit for controlling the gate pulse modulation circuit are unnecessary, so that the feedthrough voltage (DELTA Vp) can be effectively supplied even with low power consumption and small circuit area .

Further, the gate can be driven regardless of the polarity of the panel element driven by the gate driver.

In addition, the modulation period of the gate drive pulse can be adjusted more precisely.

In addition, the modulation period of the gate drive pulse can be adjusted more precisely regardless of the polarity of the panel element driven by the gate driver.

Further, the modulation size of the gate drive pulse can be adjusted more precisely.

1 is a diagram showing a pixel structure of a liquid crystal flat display device;
2 is a diagram showing an example of a conventional gate pulse modulation circuit;
3 shows a gate scan waveform;
4 is a schematic circuit diagram of a gate driver according to the first embodiment of the present invention.
5 is a schematic circuit diagram of a gate driver according to a second embodiment of the present invention;
6 is a schematic circuit diagram of a gate driver according to a third embodiment of the present invention;
7 is a schematic circuit diagram of a gate driver according to a fourth embodiment of the present invention;
8 is a schematic circuit diagram of a gate driver according to a fifth embodiment of the present invention.
9 is a schematic circuit diagram of a gate driver according to a sixth embodiment of the present invention.
10 is a view showing voltage-current characteristics of an NMOS transistor;
11 is a drive waveform diagram of an n-type TFT scan line.
12 is a diagram showing voltage-current characteristics of a PMOS transistor;
Fig. 13 is a driving waveform diagram of a p-type TFT scan line; Fig.
Fig. 14 is a driving waveform diagram of a p-type TFT scan line in the case where VGM1 in Fig. 13 is a waveform other than direct current; Fig.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

4 is a schematic circuit diagram of a gate driver according to the first embodiment of the present invention. The gate driver includes a shift register, a level shifter, and a buffer, but a shift register is not shown in Fig.

The buffer further includes a first transistor (N1) and a second transistor (P2) of opposite polarity connected with the same signal input terminal to the gate and having drains connected to each other, and a drain connected to the source of the first transistor (N1) A first intermediate voltage supply terminal VGM for supplying a first intermediate voltage between the maximum value VGH and the minimum value VGL of the buffer driving voltage is connected and the third transistor N3 having the same polarity as the polarity of the first transistor N1 is connected, (N2).

This configuration eliminates the need for a separate control circuit for controlling the gate pulse modulation or the separate current route or gate pulse modulation circuit, so that the feedthrough voltage (DELTA Vp) can be effectively .

5 is a schematic circuit diagram of a gate driver according to a second embodiment of the present invention. 5, a drain is connected to the source of the second transistor P2 and a second intermediate voltage supply terminal (not shown) is connected to the gate to supply a second intermediate voltage between the maximum value VGH and the minimum value VGL of the buffer driving voltage And a fourth transistor P1 having the same polarity as the polarity of the second transistor P2. According to this configuration, it is possible to drive the gate regardless of the polarity of the panel element driven by the gate driver.

6 is a schematic circuit diagram of a gate driver according to a third embodiment of the present invention. 6 further includes a fifth transistor N3 having a drain connected to the drains of the first transistor N1 and the second transistor P2 and a source connected to the source of the third transistor N2. According to this configuration, the modulation period of the gate drive pulse can be adjusted more precisely.

7 is a schematic circuit diagram of a gate driver according to a fourth embodiment of the present invention. 7, the buffer includes all of the first to fifth transistors, and the drain of the first transistor N1 and the drain of the second transistor P2 is further connected to the source of the fourth transistor P1. And a sixth transistor P3 to which a source is connected. According to this configuration, the modulation period of the gate drive pulse can be adjusted more precisely regardless of the polarity of the panel element driven by the gate driver.

8 is a schematic circuit diagram of a gate driver according to a fifth embodiment of the present invention. 8, a drain is connected to the source of the third transistor N2, and a third intermediate voltage supply terminal (not shown) for supplying a third intermediate voltage between the maximum value VGH and the minimum value VGL of the buffer driving voltage And a seventh transistor N4 having the same polarity as the polarity of the first transistor N1. With this configuration, the modulation size of the gate drive pulse can be adjusted more precisely.

9 is a schematic circuit diagram of a gate driver according to a sixth embodiment of the present invention. 9, a drain is connected to the source of the fourth transistor P2, and a fourth intermediate voltage supply terminal (not shown) for supplying a fourth intermediate voltage between the maximum value (VGH) and the minimum value (VGL) And an eighth transistor N4 having the same polarity as the polarity of the second transistor N1. According to this configuration, the polarity of the polarity is opposite to that of the embodiment of FIG. 8, so that the modulation magnitude of the gate drive pulse can be adjusted more precisely.

7, the gate driver includes a shift register, a potential shifter (level shifter), and a buffer. The shift register transfers and generates a signal for driving the scan line, and the potential converter converts the shift register signal of low potential into a signal of high potential for driving the TFT of the scan line. And generates a waveform for driving.

The buffer consists of three PMOSs (P1 and P2 and P3 in series) and three NMOSs (N1 and N2 and N3 in series). P2 and N1 receive the output of the level shifter as input and P1 receives the voltage VGM1 between the gate high voltage VGH and the gate low voltage VGL as inputs and N2 is the gate high voltage VGH, And a voltage VGM2 between the voltage VGL.

The buffer can be composed of several PMOSs connected in series, and can also be composed of several NMOSs connected in series. At this time, one or more PMOS and NMOS receive the output of the level shifter, and the other PMOS and NMOS receive an arbitrary voltage between VGH and VGL as an input.

The gate driver can be applied to any display device that sequentially supplies gate pulses (scan pulses) to gate lines to write video data to pixels by line sequential scanning. For example, a liquid crystal display (LCD), an organic light emitting diode (OLED) display, and an electrophoresis display (EPD).

When the voltage VGM2 input to the gate of the NMOS transistor N2 is lower than the gate high voltage VGH, the current driving capability of the NMOS N2 is reduced. As a result, the slope of the falling edge of the scan line signal GOUT becomes gentle. Referring to FIG. 10, the lower the voltage of VGM2, the gentler the slope of the polling edge of GOUT becomes. 10 is a diagram showing voltage-current characteristics of an NMOS transistor.

The slope of the polling edge of the scan line signal GOUT becomes gentle, so that the feedthrough voltage (? Vp) caused by the parasitic capacitance of the n-type TFT also becomes smaller or disappears, and flicker, afterimage, color deviation, etc. are also reduced or eliminated. FIG. 11 illustrates a waveform diagram for driving a scan line by supplying a voltage lower than the gate high voltage VGH to VGM2. 11 is a driving waveform diagram of an n-type TFT scan line.

When the voltage VGM1 input to the gate of the PMOS transistor P1 is higher than the gate-low voltage VGL, the current driving capability of the PMOS P1 is reduced. As a result, the slope of the rising edge of the scan line signal GOUT becomes gentle. Referring to FIG. 12, the higher the voltage of VGM1 is, the gentler the slope of the rising edge of GOUT becomes. 12 is a graph showing voltage-current characteristics of a PMOS transistor.

The slope of the rising edge of the scan line signal GOUT becomes gentle, so that the feedthrough voltage (DELTA Vp) caused by the parasitic capacitance of the p-type TFT also becomes small, and the flicker, afterimage, color deviation, and the like also decrease or disappear. FIG. 13 illustrates a waveform diagram for driving a scan line by supplying a voltage higher than the gate-low voltage VGL to VGM1. 13 is a driving waveform chart of a p-type TFT scan line. At this time, VGM1 and VGM2 have a potential between VGH and VGL, and may be generated in the gate driver, supplied from the outside, or may have a DC voltage as well as a DC voltage.

Fig. 14 is a driving waveform diagram of a p-type TFT scan line in the case where VGM1 in Fig. 13 is a waveform other than direct current. In Fig. 14, it can be seen that in Fig. 13, VGM1, which is a direct current, is implemented as a non-DC waveform in Fig.

To summarize again, the gate driver consists of a shift register, a level shifter, and a buffer. In the buffer, two PMOSs and two NMOSs are connected in series. One of the PMOS and NMOS uses a given intermediate voltage (VGM1 and VGM2) between VGH and VGL as an input to generate a rising edge, And the slope of the falling edge.

As a concrete example of realizing this, in order to implement the function of controlling the slope at the time of falling, two or more NMOS transistors Tr. Is connected as a series, and when a certain voltage (VGM) between VGH and VGL generated internally or externally is input to the gates of the two or more NMOS Tr. When at least one of the two or more PMOS transistors is connected to a series in order to realize a function of adjusting the slope at the time of rising when receiving the output of the level shifter or the output of the Amp having the output as its input, When an arbitrary voltage (VGM) between VGH and VGL generated internally or externally is input to the gates of two or more PMOS Tr. The output of the Levlel shifter or the output of Amp with its output as input.

With this configuration, it is possible to realize an image free from flicker, afterimage, and color deviation by reducing or eliminating the feedthrough voltage (DELTA Vp) caused by the parasitic capacitance of the TFT. Particularly, by using the voltage-current characteristics of the MOS transistor compared with the conventional technique of modulating the gate high voltage (VGH), the consumption current can be drastically reduced and the increase of the circuit area can be minimized.

Although the present invention has been described in terms of some preferred embodiments, the scope of the present invention should not be limited thereby but should be modified and improved in accordance with the above-described embodiments.

N1: first transistor
P2: second transistor
N2: third transistor
P1: fourth transistor
N3: fifth transistor
P3: sixth transistor
N4: seventh transistor
P4: the eighth transistor

Claims (6)

A gate driver comprising a shift register, a level shifter, and a buffer,
The buffer includes:
A first transistor and a second transistor of opposite polarity, to which the same signal input terminal is commonly connected to the gate and the drains are connected to each other; And
A drain connected to a source of the first transistor, a gate connected to a first intermediate voltage supply terminal for supplying a first intermediate voltage between a maximum value and a minimum value of the buffer driving voltage, And a third transistor of the second conductivity type. The method according to claim 1,
A drain connected to the source of the second transistor, a second intermediate voltage supply terminal connected to the gate for supplying a second intermediate voltage between a maximum value and a minimum value of the buffer driving voltage, And a fourth transistor of a second polarity. The method according to claim 1,
And a fifth transistor having a drain connected to a drain of the first transistor and a second transistor, a source connected to a source of the third transistor, and a fifth transistor having the same polarity as the first transistor. The method of claim 3,
A drain connected to the source of the second transistor, a second intermediate voltage supply terminal connected to the gate for supplying a second intermediate voltage between a maximum value and a minimum value of the buffer driving voltage, A fourth transistor of a polarity; And
And a sixth transistor having a drain connected to a drain of the first transistor and a second transistor and a source connected to a source of the fourth transistor and having the same polarity as that of the second transistor, . The method according to claim 1,
A third intermediate voltage supply terminal connected to the source of the third transistor and supplying a third intermediate voltage between a maximum value and a minimum value of the buffer driving voltage to the gate, Further comprising a seventh transistor. 6. The method of claim 5,
A drain connected to the source of the second transistor, a second intermediate voltage supply terminal connected to the gate for supplying a second intermediate voltage between a maximum value and a minimum value of the buffer driving voltage, A fourth transistor of a polarity; And
A drain connected to a source of the fourth transistor, and a fourth intermediate voltage supply terminal connected to the gate for supplying a fourth intermediate voltage between a maximum value and a minimum value of the buffer driving voltage, Further comprising an eighth transistor.

Images