KR20060135385A - Scan dirver and liquid crystal display device using the same - Google Patents

Abstract

A gate driver and a liquid crystal display device using the same are provided to increase the freedom in a design of the gate driver by stably displaying desired images by determining the output direction of a sampling pulse according to the supply direction of a gate start pulse. A gate driver includes a shift register, a level shifter(102), and an output buffer(104). The output direction of a sampling pulse of the shift register is controlled by first and second gate start pulses, which are input from different directions. The level shifter changes the voltage level of the sampling pulse to generate a scan signal. The output buffer supplies the scan signal from the level shifter to gate lines. The shift register includes a direction determining unit, at least one demultiplexer, and at least one D flip-flop.

Description

Gate Driver and Liquid Crystal Display Using the Same {SCAN DIRVER AND LIQUID CRYSTAL DISPLAY DEVICE USING THE SAME}

1 is a diagram illustrating a conventional bidirectional shift register unit.

FIG. 2 is a diagram illustrating the shift register unit illustrated in FIG. 1 in detail.

3A and 3B are diagrams illustrating a connection state of a demultiplexer in response to a direction setting signal.

4A and 4B are waveform diagrams illustrating an operation process of the shift register unit illustrated in FIG. 1.

5 is a view showing a gate driver according to an embodiment of the present invention.

6 is a diagram illustrating in detail a shift register illustrated in FIG. 5.

<Description of Symbols for Main Parts of Drawings>

2,102: demultiplexer section 4,104: deflipper section

2a, 2b, 2c, 2d, 102a, 102b, 102c, 102d: Demultiplexer

4a, 4b, 4c, 4d, 104a, 104b, 104c, 104d

100: shift register section 102: level shifter section

104: output buffer section 106: direction setting section

The present invention relates to a gate driver and a liquid crystal display using the same, and more particularly, to a gate driver whose output direction is controlled by a start pulse and a liquid crystal display using the same.

The liquid crystal display device displays an image by adjusting light transmittance of liquid crystal cells according to data signals. Such a liquid crystal display includes a liquid crystal panel having liquid crystal cells positioned at intersections of gate lines and data lines.

The liquid crystal panel is provided with pixel electrodes and a common electrode for applying an electric field to each of the liquid crystal cells. Each of the pixel electrodes is connected to one of the data lines via a source and a drain electrode of a thin film transistor, which is a switching element. The gate terminal of the thin film transistor is connected to any one of the gate lines.

The driving circuit includes a gate driver for driving the gate lines and a data driver for driving the data lines. The gate driver sequentially supplies scan signals to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel. The data driver supplies a video signal to each of the data lines whenever a scan signal is supplied to any one of the gate lines. Accordingly, the liquid crystal display displays an image by adjusting light transmittance by an electric field applied between the pixel electrode and the common electrode according to the video signal for each liquid crystal cell.

In such a driving circuit, the gate driver supplies a scan signal in both directions by the need for driving. To this end, the gate driver has a bidirectional shift register capable of generating sampling pulses in both directions.

1 is a diagram illustrating a conventional bidirectional shift register unit.

Referring to FIG. 1, the conventional bidirectional shift register receives a direction setting signal DIR, a first gate start pulse GSP1, a second gate start pulse GSP2, and a gate shift clock GSC.

The shift register part supplied with the first gate start pulse GSP1 and / or the second gate start pulse GSP2 is the first gate start pulse GSP1 or the second gate start pulse GSP2 for each period of the gate shift clock GSC. 1) Sequentially shift) to generate sampling pulses.

Here, the output direction of the sampling pulse is determined by the direction setting signal DIR. For example, when the direction setting signal DIR is set to a low state, the shift register unit sequentially shifts the first gate start pulse GSP1 for each period of the gate shift clock GSC, and thus the first output line O1. Sampling pulses are generated in the order of the nth output line On. When the direction setting signal DIR is set to a high state, the shift register unit sequentially shifts the second gate start pulse GSP2 for each period of the gate shift clock GSC, and the nth output line On Sampling pulses are generated in the order of the first output line O1.

FIG. 2 is a diagram illustrating a circuit diagram of the shift register unit illustrated in FIG. 1. In FIG. 2, n is set to 4 for convenience of description.

Referring to FIG. 2, the conventional shift register unit includes a demultiplexer unit 2 and a flip-flop unit 4.

The flip-flop portion 4 has n (i.e., four) de-flipped flops 4a to 4d provided for each of the output lines O1 to O4. The de flip-flops 4a to 4d output a signal supplied from the demultiplexer 2 as a sampling pulse in response to the gate shift clock GSC.

The demultiplexer portion 2 includes n (i.e., 4) demultiplexers 2a to 2d provided for each output line O1 to O4. The demultiplexer 2 is controlled by the direction setting signal DIR. For example, when the direction setting signal DIR is set to low, the first terminal L of each of the demultiplexers 2a to 2d is connected to any one of the flip-flops 4a to 4d. In addition, when the direction setting signal DIR is set to high, the second terminal H of each of the demultiplexers 2a to 2d is connected to any one of the flip-flops 4a to 4d.

An operation process when the direction setting signal DIR is set to Low will be described in detail with reference to FIGS. 3A and 4A.

First, when the direction setting signal DIR is set to low, the first terminal L of the demultiplexers 2a to 2d is connected to the deflip-flops 4a to 4d. Thereafter, when the first gate start pulse GSP1 and the gate shift clock GSC are supplied, the first sampling pulse SP1 is output to the first output terminal O1 of the first flip-flop 4a. The first sampling pulse SP1 is supplied to the second demultiplexer 2b as a carry signal.

Subsequently, when the gate shift clock GSC is supplied, the second sampling pulse SP2 is output to the second output terminal of the second flip-flop 4b. The second sampling pulse SP2 is supplied to the third demultiplexer 2c as a carry signal. In practice, the conventional shift register unit generates and supplies the sampling pulses SP1 to SP4 sequentially from the first output line O1 to the fourth output line O4 while repeating the above process. Then, the gate driver sequentially supplies a scan signal from the first gate line to the fourth gate line in response to the sampling pulses SP1 to SP4.

The operation process when the direction setting signal DIR is set to High will be described in detail with reference to FIGS. 3B and 4B. The second terminal H of 2d) is connected to the def flip-flops 4a to 4d. Subsequently, when the second gate start pulse GSP2 and the gate shift clock GSC are supplied, the first sampling pulse SP1 is output to the fourth output terminal O4 of the fourth flip-flop 4d. The first sampling pulse SP1 is supplied to the third demultiplexer 2c as a carry signal.

Thereafter, when the gate shift clock GSC is supplied, the second sampling pulse SP2 is output to the third output terminal O3 of the third flip-flop 4c. The second sampling pulse SP2 is supplied to the second demultiplexer 2b as a carry signal. In practice, the conventional shift register unit generates and supplies sampling pulses SP1 to SP4 sequentially from the fourth output line O4 to the first output line O1 while repeating the above process. Then, the gate driver sequentially supplies a scan signal from the fourth gate line to the first gate line in response to the sampling pulses SP1 to SP4.

The shift register of the conventional gate driver includes a direction setting pin Pin for generating a direction setting signal. That is, the conventional shift register generates a high or low direction setting signal DIR by controlling the position of the direction setting pin. However, if the direction pin is additionally included in the shift register, a problem arises in that the design becomes complicated. In addition, a problem arises in that the position of the direction setting pin must be controlled whenever the output direction of the scan signal is changed. In addition, a problem occurs in that the desired image cannot be displayed if the position of the direction sulfing pin is not controlled in the desired direction.

Accordingly, an object of the present invention is to provide a gate driver whose output direction is controlled by a start pulse and a liquid crystal display using the same.

In order to achieve the above object, the gate driver according to an embodiment of the present invention is a shift register unit for controlling the output direction of the sampling pulse by the first gate start pulse or the second gate start pulse supplied from different directions, And a level shifter unit for generating a scan signal by changing a voltage level of the sampling pulse, and an output buffer unit for supplying scan signals supplied from the level shifter unit to gate lines.

Preferably, the shift register unit includes a direction setting unit for generating a first control signal when the first gate start pulse is supplied and generating a second control signal when the second gate start pulse is supplied; At least one demultiplexer whose output is controlled in response to a first control signal or a second control signal supplied from the direction setting unit, and a signal supplied from the demultiplexer and supplied from the demultiplexer to the level shifter unit as the sampling pulse. At least one deflip-flop for feeding. The direction setting unit is an SR latch receiving the first gate start pulse through a first terminal and the second gate start pulse through a second terminal. When the first control signal is input, the demultiplexer is controlled to output the scan signal from the first gate line in the order of the nth (n is a natural number) gate line. When the second control signal is input, the demultiplexer is controlled to output the scan signal in the order from the nth gate line to the first gate line.

A liquid crystal display according to an embodiment of the present invention includes a data driver for supplying a data signal to data lines; A gate driver for sequentially supplying scan signals to the gate lines; A plurality of liquid crystal cells formed at an intersection of the gate lines and the data lines, and configured to display an image corresponding to the data lines; The gate driver generates a scan signal by changing a voltage level of the sampling pulse and a shift register unit in which an output direction of a sampling pulse is controlled by a first gate start pulse or a second gate start pulse supplied from different directions. And a level shifter unit for supplying a scan signal supplied from the level shifter unit to gate lines.

Preferably, the shift register unit includes a direction setting unit for generating a first control signal when the first gate start pulse is supplied and generating a second control signal when the second gate start pulse is supplied; At least one demultiplexer whose output is controlled in response to a first control signal or a second control signal supplied from the direction setting unit, and a signal supplied from the demultiplexer and supplied from the demultiplexer to the level shifter unit as the sampling pulse. At least one deflip-flop for feeding. The direction setting unit is an SR latch receiving the first gate start pulse through a first terminal and the second gate start pulse through a second terminal. When the first control signal is input, the demultiplexer is controlled to output the scan signal from the first gate line in the order of the nth (n is a natural number) gate line. When the second control signal is input, the demultiplexer is controlled to output the scan signal in the order from the nth gate line to the first gate line.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 to 6.

5 is a view showing a gate driver according to an embodiment of the present invention.

Referring to FIG. 5, the gate driver of the present invention includes a shift register unit 100, a level shifter unit 102, and an output buffer unit 104.

The shift register unit 100 receives the first gate start pulse GSP1 or the second gate pulse GSP2 and receives the first gate start pulse GSP1 or the second gate pulse every cycle of the gate shift clock GSC. The sampling pulse is supplied to the output lines O1 to On while shifting the GSP2. Here, the shift register unit 100 sequentially supplies an output signal from the first output line O1 to the nth output line On when the first gate start pulse GSP1 is supplied. The shift register unit 100 sequentially supplies an output signal from the nth output line On to the first output line O1 when the second gate start pulse GSP2 is supplied. That is, in the present invention, the shift register unit 100 controls the output direction of the sampling pulse in response to the input of the gate start pulses GSP1 and GSP2.

The level shifter 102 receives a gate output signal GOE. The level shifter 102 supplied with the gate output signal GOE generates a scan signal by changing a voltage value of the sampling pulse, and supplies the generated scan signal to the output buffer unit 104. In practice, the level shifter 102 generates a scan signal during the low section (or the high section) of the gate output signal GOE and supplies the scan signal to the output buffer section 104.

The output buffer unit 104 sequentially drives the gate lines G1 to Gn by supplying the scan signals supplied from the level shifter unit 102 to the gate lines G1 to Gn. Here, the direction of the scan signal output from the output buffer section 104 is set corresponding to the sampling pulse.

6 is a diagram illustrating in detail a shift register illustrated in FIG. 5. In FIG. 6, n is assumed to be 4 for convenience of description.

Referring to FIG. 6, the shift register unit 100 of the present invention includes a direction setting unit 106, a demultiplexer unit 102, and a flip-flop unit 104.

The flip-flop portion 104 includes n (i.e., four) de-flipped flops 104a to 104d provided for each output line O1 to O4. The de-flip flops 104a to 104d output a signal supplied from the demultiplexer 2 as a sampling pulse in response to the gate shift clock GSC.

The demultiplexer section 102 includes n (ie 4) demultiplexers 102a to 102d provided for each output line O1 to O4. The demultiplexer 102 is controlled by the control signal supplied from the direction setting unit 106. For example, when a low control signal is input from the direction setting unit 106, the first terminal L of each of the demultiplexers 102a to 102d is connected to the deflip-flops 104a to 104d. When the high control signal is input from the direction setting unit 106, the second terminal H of each of the demultiplexers 102a to 102d is connected to the deflip-flops 104a to 104d.

The direction setting unit 106 is composed of an SR latch. When the first gate start pulse GSP1 is input to the first input terminal S of the direction setting unit 106, a low control signal is generated and supplied to the demultiplexers 104a to 104d. When the second gate start pulse GSP2 is input to the second input terminal R, the direction setting unit 106 generates a high control signal and supplies the high control signal to the demultiplexers 104a to 104d.

In detail, when the first gate start pulse GSP1 is input to the first input terminal S, a low control signal is output to the output terminal / Q of the direction setting unit 106. = high, R = Low, and even if the supply of the first gate start pulse GSP1 is stopped, the direction setting unit 106 maintains the previous logic value, that is, the control signal of the row (i.e., S = Low, R = Low)

When the second gate start pulse GSP2 is input to the second input terminal S, a high control signal is output to the output terminal / Q of the direction setting unit 106 (that is, S = Low and R = High). In addition, even if the supply of the second gate start pulse GSP2 is stopped, the direction setting unit 106 maintains the previous logic value, that is, the control signal of high (that is, S = Low and R = Low).

The operation process when the first gate start pulse GSP1 is input will be described in detail. First, the direction setting unit 106 supplied with the first gate start pulse GSP1 and the gate shift clock GSC is low. Is supplied to the demultiplexers 102a to 102d. Then, the first terminal L of each of the demultiplexers 102a to 102d is connected to the de flip-flops 104a to 104d.

Thereafter, the first demultiplexer 102a supplies the first start pulse GSP1 to the first deflect flop 104a, and the first deflect flop 104a corresponds to the gate shift clock GSC. Likewise, the first sampling pulse SP1 is output to the first output terminal O1. The first sampling pulse SP1 is supplied to the second demultiplexer 102b as a carry signal.

Thereafter, when the gate shift clock GSC is supplied, the second sampling pulse SP2 is output to the second output terminal O2 of the second flip-flop 104b. The second sampling pulse SP2 is supplied to the third demultiplexer 102c as a carry signal. In practice, the shift register unit of the present invention sequentially generates and supplies sampling pulses SP1 to SP4 from the first output line O1 to the fourth output line O4. Then, the gate driver sequentially supplies a scan signal from the first gate line G1 to the fourth gate line G4.

The operation process when the second gate start pulse GSP2 is input will be described in detail. First, the direction setting unit 106 supplied with the second gate start pulse GSP2 and the gate shift clock GSC is high. Is supplied to the demultiplexers 102a to 102d. Then, the second terminal H of each of the demultiplexers 102a to 102d is connected to the deflip flops 104a to 104d.

Thereafter, the fourth demultiplexer 102d supplies the second start pulse GSP2 to the fourth deflected flop 104d, and the fourth deflected flop 104d corresponds to the gate shift clock GSC with FIG. 4B. Likewise, the first sampling pulse SP1 is output to the fourth output terminal Or. The first sampling pulse SP1 is supplied to the third demultiplexer 102c as a carry signal.

Thereafter, when the gate shift clock GSC is supplied, the second sampling pulse SP2 is output to the third output terminal O3 of the third flip-flop 104c. The second sampling pulse SP2 is supplied to the second demultiplexer 102b as a carry signal. In fact, the shift register unit of the present invention sequentially generates and supplies sampling pulses SP1 to SP4 from the fourth output line O4 to the first output line O1. Then, the gate driver sequentially supplies a scan signal from the fourth gate line G4 to the first gate line G1.

As described above, according to the gate driver and the liquid crystal display using the same according to the present invention, the output direction of the sampling pulse of the shift register part included in the gate driver is determined by the supply direction of the gate start pulse. As such, when the output direction of the sampling pulse is determined by the supply direction of the gate start pulse, a desired image can be stably displayed. In addition, since the direction setting pin is not additionally installed, design freedom can be secured.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (10)

A shift register section in which an output direction of a sampling pulse is controlled by a first gate start pulse or a second gate start pulse supplied from different directions; A level shifter unit for generating a scan signal by changing a voltage level of the sampling pulse; And an output buffer for supplying scan signals supplied from the level shifter to gate lines. The method of claim 1, The shift register part A direction setting unit for generating a first control signal when the first gate start pulse is supplied and generating a second control signal when the second gate start pulse is supplied; At least one demultiplexer whose output is controlled in response to a first control signal or a second control signal supplied from the direction setting unit; And at least one deflip-flop connected to each of said demultiplexers and for supplying a signal supplied from said demultiplexer to said level shifter section as said sampling pulse. The method of claim 2, And the direction setting unit is an SR latch receiving the first gate start pulse through a first terminal and the second gate start pulse through a second terminal. The method of claim 2, And the output of the demultiplexer is controlled so that the scan signal is supplied from the first gate line to the nth (n is a natural number) gate line when the first control signal is input. The method of claim 4, wherein And the output of the demultiplexer is controlled such that the scan signal is supplied in the order from the nth gate line to the first gate line when the second control signal is input. A data driver for supplying a data signal to the data lines; A gate driver for sequentially supplying scan signals to the gate lines; A plurality of liquid crystal cells formed at intersections of the gate lines and the data lines, and configured to display an image corresponding to the data lines; The gate driver A shift register section in which an output direction of a sampling pulse is controlled by a first gate start pulse or a second gate start pulse supplied from different directions; A level shifter unit for generating the scan signal by changing the voltage level of the sampling pulse; And an output buffer unit for supplying scan signals supplied from the level shifter unit to gate lines. The method of claim 6, The shift register part A direction setting unit for generating a first control signal when the first gate start pulse is supplied and generating a second control signal when the second gate start pulse is supplied; At least one demultiplexer whose output is controlled in response to a first control signal or a second control signal supplied from the direction setting unit; And at least one deflip-flop connected to each of the demultiplexers and for supplying a signal supplied from the demultiplexer to the level shifter unit as the sampling pulse. The method of claim 7, wherein And the direction setting part is an SR latch receiving the first gate start pulse through a first terminal and the second gate start pulse through a second terminal. The method of claim 7, wherein And the output is controlled such that the scan signal is supplied from the first gate line to the nth (n is a natural number) gate line when the first control signal is input. The method of claim 9, And outputting the demultiplexer so that the scan signal is supplied in the order from the nth gate line to the first gate line when the second control signal is input.

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