KR102610626B1 - Light emitting diode having solder bump - Google Patents

Abstract

A light emitting diode according to an embodiment includes a first conductive semiconductor layer; an active layer disposed on the first conductive semiconductor layer; a second conductive semiconductor layer disposed on the active layer; a first bump pad electrically connected to the first conductive semiconductor layer; a second bump pad electrically connected to the second conductive semiconductor layer; a first solder bump disposed on the first bump pad; and a second solder bump disposed on the second bump pad, wherein the first and second solder bumps each have a thickness in the range of 10 to 80 times the thickness of the first bump pad and the second bump pad. have

Description

Light emitting diode with solder bumps {LIGHT EMITTING DIODE HAVING SOLDER BUMP}

The present invention relates to a light emitting diode, and more particularly to a light emitting diode having a solder bump.

In general, nitrides of group III elements such as gallium nitride (GaN) and aluminum nitride (AlN) have excellent thermal stability and have a direct transition energy band structure, so they have recently been used as light source materials in the visible and ultraviolet regions. is receiving a lot of attention. In particular, blue and green light-emitting diodes using indium gallium nitride (InGaN) are used in various application fields such as large-scale color flat panel displays, traffic lights, indoor lighting, high-density light sources, high-resolution output systems, and optical communications.

Generally, light emitting diodes are provided in various chip forms, and the light emitting diode chips are mounted on a mounting surface such as a package, submount, or printed circuit board. For example, a flip-chip type light emitting diode includes bump pads, and the bump pads are mounted on connection pads such as a printed circuit board through solder paste.

The mounting process according to the prior art is generally performed by applying solder paste on the connection pads, placing the bump pads of the light emitting diode chip on the solder paste, and then performing a reflow process, whereby the bumps are formed by solder. The pads are bonded to the connecting pads.

However, in order to bond a light emitting diode chip, it is necessary to apply a significant amount of solder paste on the connection pads. For this purpose, it may be necessary to apply solder paste multiple times on one connection pad. Therefore, as the amount of solder paste applied on the connection pads increases, the mounting process of the light emitting diode chip becomes more complicated, and the possibility of process defects increases.

Meanwhile, since the bump pads formed on the light emitting diode chip generally have a relatively thin thickness, they do not help in handling the light emitting diode chip. Accordingly, it is difficult to form a white wall to improve the brightness of the light emitting diode chip. Additionally, relatively small-sized light emitting diode chips are difficult to handle, making the mounting process using solder paste difficult.

The problem to be solved by the present invention is to provide a light emitting diode chip that can easily perform a bonding process using solder.

Another problem to be solved by the present invention is to provide a light emitting diode chip that is easy to handle.

A light emitting diode according to an embodiment of the present invention includes a first conductivity type semiconductor layer; an active layer disposed on the first conductive semiconductor layer; a second conductive semiconductor layer disposed on the active layer; a first bump pad electrically connected to the first conductive semiconductor layer; a second bump pad electrically connected to the second conductive semiconductor layer; a first solder bump disposed on the first bump pad; and a second solder bump disposed on the second bump pad, wherein the first and second solder bumps each have a thickness in the range of 10 to 80 times the thickness of the first bump pad and the second bump pad. have

A light emitting diode according to another embodiment of the present invention includes a substrate; a first conductive semiconductor layer disposed on the substrate; an active layer disposed on the first conductive semiconductor layer; a second conductive semiconductor layer disposed on the active layer; an upper insulating layer disposed on the second conductive semiconductor layer and having openings to allow electrical connection; and a first solder bump and a second solder bump disposed on the upper insulating layer and electrically connected to the first and second conductive semiconductor layers, respectively, through openings in the upper insulating layer, The first and second solder bumps each have a thickness in the range of 10um to 100um.

A light emitting device according to another embodiment of the present invention includes a mounting surface having connection pads; and a light emitting diode mounted on the mounting surface through solders, wherein the light emitting diode includes: a first conductive semiconductor layer; an active layer disposed on the first conductive semiconductor layer; a second conductive semiconductor layer disposed on the active layer; a first bump pad electrically connected to the first conductive semiconductor layer; and a second bump pad electrically connected to the second conductive semiconductor layer, wherein the solder bonds the connection pads and the first and second bump pads, and the solder includes the first bump pad and the second bump pad. It has a thickness in the range of 10 to 80 times the thickness of the second bump pad.

A light emitting diode according to another embodiment of the present invention includes a substrate; At least four light emitting cells disposed on the substrate, each including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer; and at least two solder bumps disposed on the light emitting cells, wherein the at least four light emitting cells are disposed close to one edge of the substrate and at least two light emitting cells are disposed close to the other edge of the substrate. It includes at least two light emitting cells, and solder bump(s) are provided on two or more of the at least two light emitting cells disposed close to one edge of the substrate, and disposed close to the other edge of the substrate. Solder bump(s) are provided on two or more of the at least two light emitting cells.

According to embodiments of the present invention, by providing a relatively thick solder bump on the light emitting diode, the bonding process can be easily performed and the handling of the light emitting diode chip can be facilitated.

Other advantages and effects of the present invention will become clearer through the detailed description.

1 is a schematic plan view for explaining a light emitting diode according to an embodiment of the present invention.
Figure 2 is a cross-sectional view taken along line AA in Figure 1.
Figure 3 is a schematic cross-sectional view illustrating a solder bump of a light emitting diode according to an embodiment of the present invention.
Figure 4 is a schematic plan view for explaining a light emitting diode according to an embodiment of the present invention.
Figures 5A to 5F are schematic cross-sectional views for explaining a light-emitting device manufacturing process according to an embodiment of the present invention.
Figure 6 is a schematic plan view for explaining a light emitting diode according to another embodiment of the present invention.
FIG. 7 is a schematic circuit diagram for explaining the light emitting diode of FIG. 6.
Figure 8 is a schematic cross-sectional view taken along line BB in Figure 6.
Figure 9 is a schematic cross-sectional view taken along line CC of Figure 6;
Figure 10 is a schematic cross-sectional view for explaining a light emitting diode according to another embodiment of the present invention.
Figure 11 is a schematic plan view for explaining a light emitting diode according to another embodiment of the present invention.
Figure 12 is an exploded perspective view to explain a lighting device using a light emitting diode according to an embodiment of the present invention.
Figure 13 is a cross-sectional view for explaining a display device using a light emitting diode according to another embodiment of the present invention.
Figure 14 is a cross-sectional view for explaining a display device using a light emitting diode according to another embodiment of the present invention.
Figure 15 is a cross-sectional view for explaining an example of applying a light emitting diode to a headlamp according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. The embodiments introduced below are provided as examples so that the idea of the present invention can be sufficiently conveyed to those skilled in the art. Accordingly, the present invention is not limited to the embodiments described below and may be embodied in other forms. And in the drawings, the width, length, thickness, etc. of components may be exaggerated for convenience. Additionally, when one component is described as being "on top of" or "on" another component, it means that each component is "directly on" or "directly on" the other component, as well as when each component is described as being "directly on" or "directly on" the other component. This also includes cases where another component is interposed. Like reference numerals refer to like elements throughout the specification.

A light emitting diode according to an embodiment of the present invention includes a first conductivity type semiconductor layer; an active layer disposed on the first conductive semiconductor layer; a second conductive semiconductor layer disposed on the active layer; a first bump pad electrically connected to the first conductive semiconductor layer; a second bump pad electrically connected to the second conductive semiconductor layer; a first solder bump disposed on the first bump pad; and a second solder bump disposed on the second bump pad, wherein the first and second solder bumps each have a thickness in the range of 10 to 80 times the thickness of the first bump pad and the second bump pad. You can have it.

Furthermore, the first solder bump and the second solder bump have inclined sides, and the inclination angle of the inclined sides may be in the range of 65 degrees to 75 degrees with respect to the bottom surface.

Meanwhile, the gap between the first solder bump and the second solder bump may be 2 times or more and 10 times or less the thickness of the first solder bump or the second solder bump.

Furthermore, the light emitting diode may further include a substrate disposed under the first conductive semiconductor layer, and the shortest horizontal distance between the first solder bump or the second solder bump and the substrate is the first solder bump. and may be equal to or greater than the thickness of the second solder bump.

The light emitting diode may further include an upper insulating layer disposed on the second conductive semiconductor layer, wherein the upper insulating layer has openings to allow electrical connection, and the first and second bump pads are It is disposed on the upper insulating layer and can be electrically connected to the first and second conductive semiconductor layers through the openings.

In one embodiment, the first and second solder bumps may cover the entire upper surfaces of the first and second bump pads, respectively.

The gap between the first bump pad and the second bump pad may be 2 to 10 times the thickness of the first or second solder bump.

The light emitting diode may further include a substrate disposed under the first conductive semiconductor layer, and the shortest horizontal distance between the first bump pad or the second bump pad and an edge of the substrate is the first solder. It may be equal to or greater than the thickness of the bump and the second solder bump.

The light emitting diode includes a transparent conductive oxide layer electrically connected to the second conductive semiconductor layer; a dielectric layer covering the conductive oxide layer and having a plurality of openings exposing the conductive oxide layer; a metal reflective layer disposed on the dielectric layer and connected to the conductive oxide layer through openings in the dielectric layer; a lower insulating layer disposed on the metal reflective layer and including a first opening exposing the first conductive semiconductor layer and a second opening exposing the metal reflective layer; a first pad metal layer disposed on the lower insulating layer and electrically connected to the first conductive semiconductor layer through a first opening in the lower insulating layer; and a second pad metal layer disposed on the lower insulating layer and electrically connected to the second conductive semiconductor layer through second openings in the lower insulating layer, wherein the openings in the upper insulating layer are The first pad metal layer and the second pad metal layer may be exposed.

In some embodiments, the light emitting diode includes: a substrate; and may further include a plurality of light emitting cells disposed on the substrate, wherein each of the light emitting cells includes the first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer, and the first bump pad is It is electrically connected to a first conductivity type semiconductor layer of one light emitting cell among the plurality of light emitting cells, and the second bump pad is connected to a second conductivity type semiconductor layer of another light emitting cell among the plurality of light emitting cells. Can be electrically connected.

In one embodiment, the light emitting diode may further include a dummy bump pad disposed on another light emitting cell among the plurality of light emitting cells, and the dummy bump pad may be electrically spaced from the light emitting cells. there is.

In another embodiment, the first bump pad and the second bump pad may each be disposed across at least two light emitting cells.

Furthermore, the first and second bump pads may include narrow areas in the area between the light emitting cells.

A light emitting diode according to another embodiment of the present invention includes a substrate; a first conductive semiconductor layer disposed on the substrate; an active layer disposed on the first conductive semiconductor layer; a second conductive semiconductor layer disposed on the active layer; an upper insulating layer disposed on the second conductive semiconductor layer and having openings to allow electrical connection; and a first solder bump and a second solder bump disposed on the upper insulating layer and electrically connected to the first and second conductive semiconductor layers, respectively, through openings in the upper insulating layer, The first and second solder bumps may each have a thickness in the range of 10um to 100um.

Additionally, the first solder bump and the second solder bump have inclined sides, and an inclination angle of the inclined sides may be in the range of 65 degrees to 75 degrees with respect to the bottom surface.

Furthermore, the gap between the first solder bump and the second solder bump may be 2 to 10 times the thickness of the first or second solder bump.

The shortest horizontal distance between the first solder bump or the second solder bump and the substrate may be more than 1/2 of the distance between the first solder bump and the second solder bump.

A light emitting device according to another embodiment of the present invention includes a mounting surface having connection pads; and a light emitting diode mounted on the mounting surface through solders, wherein the light emitting diode includes: a first conductive semiconductor layer; an active layer disposed on the first conductive semiconductor layer; a second conductive semiconductor layer disposed on the active layer; a first bump pad electrically connected to the first conductive semiconductor layer; and a second bump pad electrically connected to the second conductive semiconductor layer, wherein the solder bonds the connection pads and the first and second bump pads, and the solder includes the first bump pad and the second bump pad. It has a thickness in the range of 10 to 80 times the thickness of the second bump pad.

Additionally, the light emitting diode may further include an upper insulating layer positioned between the second conductive semiconductor layer and the first and second bump pads and having openings to allow electrical connection.

Furthermore, the light emitting diode includes: a transparent conductive oxide layer electrically connected to the second conductive semiconductor layer; a dielectric layer covering the conductive oxide layer and having a plurality of openings exposing the conductive oxide layer; a metal reflective layer disposed on the dielectric layer and connected to the conductive oxide layer through openings in the dielectric layer; a lower insulating layer disposed on the metal reflective layer and including a first opening exposing the first conductive semiconductor layer and a second opening exposing the metal reflective layer; and a first pad metal layer disposed on the lower insulating layer and electrically connected to the first conductive semiconductor layer through a first opening in the lower insulating layer. and a second pad metal layer disposed on the lower insulating layer and electrically connected to the second conductive semiconductor layer through a second opening in the lower insulating layer, wherein the openings in the upper insulating layer are connected to the second conductive semiconductor layer. The first pad metal layer and the second pad metal layer may be exposed.

A light emitting diode according to another embodiment of the present invention includes a substrate; At least four light emitting cells disposed on the substrate, each including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer; and at least two solder bumps disposed on the light emitting cells, wherein the at least four light emitting cells are disposed close to one edge of the substrate and at least two light emitting cells are disposed close to the other edge of the substrate. It includes at least two light emitting cells, and solder bump(s) are provided on two or more of the at least two light emitting cells disposed close to one edge of the substrate, and disposed close to the other edge of the substrate. Solder bump(s) are provided on two or more of the at least two light emitting cells.

Solder bumps can be arranged in a symmetrical structure to enable stable mounting of light emitting diodes.

Meanwhile, the at least two solder bumps include: a first solder bump electrically connected to one light emitting cell; and a second solder bump electrically connected to another light emitting cell.

Furthermore, the light emitting diode includes a first bump pad located between the first solder bump and the light emitting cell; And it may further include a second bump pad located between the second solder bump and the light emitting cell, wherein the first and second solder bumps have a thickness of 10 to 10 times the thickness of the first bump pad and the second bump pad, respectively. It can have a thickness within the range of 80 times.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a schematic plan view for explaining the light emitting diode 100 according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the cutting line A-A of FIG. 1.

1 and 2, the light emitting diode includes a substrate 21, a first conductive semiconductor layer 23, an active layer 25, a second conductive semiconductor layer 27, a conductive oxide layer 28, Dielectric layer 29, metal reflection layer 31, lower insulating layer 33, first pad metal layer 35a, second pad metal layer 35b), upper insulating layer 37, first bump pad 39a, It may include a second bump pad 39b, a first solder bump 41a, and a second solder bump 41b.

The substrate 21 is not particularly limited as long as it is a substrate capable of growing a gallium nitride-based semiconductor layer. Examples of the substrate 21 may be various, such as a sapphire substrate, a gallium nitride substrate, or a SiC substrate, and may be a patterned sapphire substrate. The substrate 21 may have a rectangular or square outer shape as shown in plan view (a), but is not necessarily limited thereto. The size of the substrate 21 is not particularly limited and can be selected in various ways.

The first conductive semiconductor layer 23 is disposed on the substrate 21. The first conductive semiconductor layer 23 is a layer grown on the substrate 21 and may be a gallium nitride-based semiconductor layer. The first conductive semiconductor layer 23 may be a gallium nitride-based semiconductor layer doped with an impurity, for example, Si.

In this embodiment, the edge of the first conductivity type semiconductor layer 23 is located inside the area surrounded by the edge of the substrate 21. Accordingly, a portion of the upper surface of the substrate 21 may be exposed along the perimeter of the first conductivity type semiconductor layer 23. However, the present invention is not limited to this, and the edge of the first conductive semiconductor layer 23 may be parallel to the edge of the substrate 21.

A mesa (M) may be disposed on the first conductive semiconductor layer 23. The mesa (M) may be located limited to the inside of the area surrounded by the first conductivity type semiconductor layer 23, and therefore, areas near the edge of the first conductivity type semiconductor layer 23 are not covered by the mesa (M). may be exposed to the outside without

The mesa (M) includes a second conductive semiconductor layer 27 and an active layer 25. Although not shown, the mesa M may include a portion of the thickness of the first conductivity type semiconductor layer 23. The active layer 25 is interposed between the first conductive semiconductor layer 23 and the second conductive semiconductor layer 27. The active layer 25 may have a single quantum well structure or a multiple quantum well structure. The composition and thickness of the well layer within the active layer 25 determines the wavelength of the light generated. In particular, by adjusting the composition of the well layer, an active layer that generates ultraviolet rays, blue light, or green light can be provided.

Meanwhile, the second conductive semiconductor layer 27 may be a gallium nitride-based semiconductor layer doped with a p-type impurity, for example, Mg. The p-type impurity concentration in the second conductive semiconductor layer 27 may have a concentration profile that varies along the thickness within the above range.

Meanwhile, the first conductivity type semiconductor layer 23 and the second conductivity type semiconductor layer 27 may each be a single layer, but are not limited thereto, and may be a multilayer, or may include a superlattice layer. The first conductive semiconductor layer 23, the active layer 25, and the second conductive semiconductor layer 27 are formed in a chamber using a known method such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). It can be formed by growing on the substrate 21 within.

Meanwhile, as shown in FIG. 1, the mesa M may have a via hole 27a exposing the first conductivity type semiconductor layer 23. The via hole 27a may be surrounded by the second conductive semiconductor layer 27 and the active layer 25. The via hole 27a may have an elongated shape passing through the center of the light emitting diode, as shown in FIG. 1 . As shown, the via hole 27a passes through the center of the mesa (M) and may be disposed to be biased toward one edge. The length of the via hole 27a is not particularly limited and may be 1/2 the length of the mesa (M) or longer.

Meanwhile, as shown, both ends of the via hole 27a are relatively wide and may have a round shape. By shaping the ends of the via hole 27a like this, the dielectric layer 29 and the lower insulating layer 33 can be patterned into similar shapes. In particular, when the lower insulating layer 33 includes a distributed Bragg reflector, if the width is not widened at the ends of the via hole 27a as shown in Figure 1, a severe double step is formed on the side wall of the distributed Bragg reflector, and the side wall Because the inclination angle of increases, cracks are likely to occur in the first pad metal layer 35a. Therefore, by keeping the shape of the end of the via hole 27a and the shape of the end of the first opening 33a2 of the lower insulating layer 33 as in the present embodiment, the edge of the lower insulating layer 33 has a gentle inclination angle. This can improve the yield of light emitting diodes.

Although the mesa (M) is shown and described as having a single via hole (27a), the present invention is not limited thereto. For example, a plurality of via holes may be arranged inside the mesa (M). As the number of via holes 27a increases, the current dispersion performance of the light emitting diode can be improved. Additionally, instead of the via hole 27a, an indentation penetrating into the interior of the mesa M may be formed around the mesa M. The indentation may be formed long inside the mesa (M) from one edge of the mesa (M) toward the other edge opposite to it.

Meanwhile, the conductive oxide layer 28 is disposed on the mesa (M) and contacts the second conductive semiconductor layer 27. The conductive oxide layer 28 may be disposed over almost the entire area of the mesa (M) in the upper area of the mesa (M). For example, the conductive oxide layer 28 may cover more than 80%, and even more than 90%, of the upper area of the mesa (M).

The conductive oxide layer 28 is formed of an oxide layer that transmits light generated in the active layer 25. The conductive oxide layer 28 may be formed of, for example, ITO (indium tin oxide) or ZnO. The conductive oxide layer 28 is formed to a thickness sufficient to make ohmic contact with the second conductive semiconductor layer 27, for example, within a thickness range of 3 nm to 50 nm, specifically, within a thickness range of 6 nm to 30 nm. can be formed. If the thickness of the conductive oxide layer 28 is too thin, it does not provide sufficient ohmic properties and the forward voltage increases. Additionally, if the thickness of the conductive oxide layer 28 is too thick, loss due to light absorption occurs, reducing luminous efficiency.

Meanwhile, the dielectric layer 29 covers the conductive oxide layer 28. Furthermore, the dielectric layer 29 may cover the side surfaces of the second conductive semiconductor layer 27 and the active layer 25. The edge of the dielectric layer 29 may be covered with the lower insulating layer 33. Accordingly, the edge of the dielectric layer 29 is located farther from the edge of the substrate 21 than the edge of the lower insulating layer 33. Accordingly, as will be described later, a portion of the lower insulating layer 33 may be in contact with the first conductivity type semiconductor layer 23 around the mesa (M). Moreover, the dielectric layer 29 may be defined within the upper region of the second conductive semiconductor layer 27, and the lower insulating layer 33 may be in contact with the sides of the second conductive semiconductor layer 27 and the active layer 25. It may be possible.

The dielectric layer 29 has openings 29a exposing the conductive oxide layer 28. A plurality of openings 29a may be disposed on the conductive oxide layer 28. The openings 29a are used as connection passages so that the metal reflection layer 31 can be connected to the conductive oxide layer 28. The dielectric layer 29 also has an opening 29b exposing the first conductivity type semiconductor layer 23 around the mesa M and exposing the first conductivity type semiconductor layer 23 within the via hole 27a. You can.

The dielectric layer 29 is formed of an insulating material having a lower refractive index than the second conductive semiconductor layer 27 and the conductive oxide layer 28. The dielectric layer 29 may be formed of, for example, SiO ₂ .

The thickness of the dielectric layer 29 may range from 200 nm to 1000 nm, and specifically may range from 300 nm to 800 nm. If the thickness of the dielectric layer 29 is less than 200 nm, the forward voltage is high and the light output is low, which is not good. Meanwhile, when the thickness of the dielectric layer 29 exceeds 400 nm, the light output is saturated and the forward voltage tends to increase again. Therefore, it is advantageous that the thickness of the dielectric layer 29 does not exceed 1000 nm, and in particular may be 800 nm or less.

Meanwhile, the metal reflective layer 31 is disposed on the dielectric layer 29 and connected to the ohmic contact layer 28 through the openings 29a. The metal reflective layer 31 includes a reflective metal, for example, Ag or Ni/Ag. Furthermore, the metal reflective layer 32 may include a barrier layer, such as Ni, to protect the reflective metal material layer, and may also include an Au layer to prevent oxidation of the metal layer. Furthermore, in order to improve the adhesion of the Au layer, a Ti layer may be included under the Au layer. The metal reflective layer 31 is in contact with the upper surface of the dielectric layer 29, and therefore, the thickness of the dielectric layer 29 is equal to the separation distance between the conductive oxide layer 28 and the metal reflective layer 31.

By forming an ohmic contact with the conductive oxide layer 28 and disposing the metal reflection layer 31 on the dielectric layer 29, it is possible to prevent the ohmic resistance from increasing due to solder, etc. Furthermore, by disposing the conductive oxide layer 28, the dielectric layer 29, and the metal reflection layer 31 on the second conductive semiconductor layer 27, the reflectance of light can be improved, thereby improving luminous efficiency.

The lower insulating layer 33 covers the mesa (M) and the metal reflection layer 31. The lower insulating layer 33 may also cover the first conductivity type semiconductor layer 23 along the perimeter of the mesa (M), and the first conductivity type semiconductor layer (23) within the via hole (27a) inside the mesa (M). ) can be covered. The lower insulating layer 33 covers in particular the sides of the mesa (M). Bottom insulating layer 33 may also cover dielectric layer 29.

Meanwhile, the lower insulating layer 33 has first openings 33a1 and 33a2 exposing the first conductive semiconductor layer and a second opening 33b exposing the metal reflection layer 31. The first opening 33a1 exposes the first conductive semiconductor layer 23 along the perimeter of the mesa (M), and the first opening 33a2 exposes the first conductive semiconductor layer 23 within the via hole 27a. ) is exposed.

As shown in FIG. 1, a plurality of first openings 33a1 may be arranged along the perimeter of the mesa M, but the present invention is not limited thereto. For example, a single first opening 33a1 may be formed along the perimeter of the mesa M.

In this embodiment, the first openings 33a1 of the lower insulating layer 33 are shown and described as being disposed along the perimeter of the mesa (M), but the lower insulating layer 33 is formed by the first conductive semiconductor layer 23. ) may be formed to expose the entire surrounding area, including the edges. That is, in this embodiment, the edge of the lower insulating layer 33 is shown as being parallel to the edge of the substrate 21, but the edge of the lower insulating layer 33 may be located on the first conductivity type semiconductor layer 23. It may be possible.

The second opening 33b exposes the metal reflective layer 31. A plurality of second openings 33b may be formed, and these second openings 33b may be disposed near the central area of the mesa M.

Meanwhile, the lower insulating layer 33 may be formed as a single layer of SiO2 or Si3N4, but is not limited thereto and may be formed as a multiple layer. Furthermore, the lower insulating layer 33 may include a distributed Bragg reflector. A distributed Bragg reflector may be formed by stacking insulating layers with different refractive indices. For example, a distributed Bragg reflector may be formed by alternately stacking silicon oxide films and titanium oxide films. The lower insulating layer 33 may also include a capping layer. The capping layer may function as a protective layer that covers the upper surface of the distributed Bragg reflector and protects the distributed Bragg reflector. Additionally, the capping layer improves the adhesion of the pad metal layers 35a and 35b disposed on the distributed Bragg reflector. The capping layer may be formed of SiO2, but is not limited thereto, and may be formed of a SiO2-TiO2 mixed layer or an MgF2 layer. The SiO2-TiO2 mixed layer or MgF2 layer has waterproof properties, improving the reliability of the light emitting diode in a high temperature and high humidity environment.

Meanwhile, the first pad metal layer 35a is disposed on the lower insulating layer 33 and is insulated from the mesa (M) and the metal reflection layer 31 by the lower insulating layer 33. The first pad metal layer 35a contacts the first conductive semiconductor layer 23 through the first openings 33a1 and 33a2 of the lower insulating layer 33. The first pad metal layer 35a may contact the first conductive semiconductor layer 23 through first openings 33a1 along the perimeter of the mesa (M), and may also contact the via through the second opening 33a2. It may be in contact with the first conductivity type semiconductor layer 23 within the hole 27a.

Meanwhile, the second pad metal layer 35b is disposed in the upper area of the mesa (M) on the lower insulating layer 33, and is electrically connected to the metal reflection layer 31 through the second opening 33b of the lower insulating layer 33. Connected. The second pad metal layer 35b may be surrounded by the first pad metal layer 35a, and a boundary area may be formed between them. As shown in FIG. 1, the boundary area may be formed in a ring shape. The lower insulating layer 33 is exposed in the boundary area, and this boundary area is covered with the upper insulating layer 37, which will be described later.

The first pad metal layer 35a and the second pad metal layer 35b may be formed together with the same material in the same process. The first and second pad metal layers 35a and 35b may include an ohmic reflective layer such as an Al layer, and the ohmic reflective layer may be formed on an adhesive layer such as Ti, Cr, or Ni. Additionally, a protective layer having a single or multiple layer structure of Ni, Cr, Au, etc. may be formed on the ohmic reflection layer. The first and second pad metal layers 35a and 35b may have a multilayer structure of, for example, Cr/Al/Ni/Ti/Ni/Ti/Au/Ti.

The upper insulating layer 37 covers the first and second pad metal layers 35a and 35b. Additionally, the upper insulating layer 37 may cover the first conductive semiconductor layer 23 along the perimeter of the mesa (M). In this embodiment, the top insulating layer 37 is parallel to the edge of the substrate 21. However, the present invention is not limited to this, and the edge of the upper insulating layer 37 may be located inside the area surrounded by the edge of the substrate 21 so that the upper insulating layer 37 exposes the edge area of the substrate 21. It may be possible.

Meanwhile, the upper insulating layer 37 has a first opening 37a exposing the first pad metal layer 35a and a second opening 37b exposing the second pad metal layer 35b. The first opening 37a and the second opening 37b may be disposed in the upper area of the mesa (M) and may be disposed to face each other. In particular, the first opening 37a and the second opening 37b may be disposed close to both edges of the mesa M. Additionally, as shown, the second openings 37a and 37b of the upper insulating layer 37 may be laterally spaced from the second openings 33b of the lower insulating layer 33. By separating the second opening 33b of the lower insulating layer 33 from the second opening 37b of the upper insulating layer 37 in the horizontal direction, the metal reflection layer 31 and the conductive oxide layer 28 are damaged by solder. You can prevent it from happening.

The upper insulating layer 37 may be formed of a single layer of SiO ₂ or Si ₃ N ₄ , but is not limited thereto, and may include a SiO 2 -TiO 2 mixed layer or an MgF 2 layer. The SiO2-TiO2 mixed layer or MgF2 layer has excellent waterproof properties and can improve the reliability of light emitting diodes in high temperature and high humidity environments. Additionally, the upper insulating layer 37 may have a multilayer structure including a silicon nitride film and a silicon oxide film, and may include a distributed Bragg reflector in which silicon oxide films and titanium oxide films are alternately stacked.

Meanwhile, the first bump pad 39a is in electrical contact with the first pad metal layer 35a exposed through the first opening 37a of the upper insulating layer 37, and the second bump pad 39b is in electrical contact with the second pad metal layer 35a. It electrically contacts the second pad metal layer 35b exposed through the opening 37b. As shown in FIG. 1, the first bump pad 39a and the second bump pad 39b cover and seal both the first opening 37a and the second opening 37b of the upper insulating layer 37, respectively. You can. However, the present invention is not limited to this, and the first bump pad 39a is disposed in the first opening 37a of the upper insulating layer 37, and the second bump pad 39b is disposed in the upper insulating layer 37. It may be disposed within the second opening 37b.

Additionally, as shown in FIG. 1, the second bump pad 39b may be located limited to the upper region of the second pad metal layer 35a. However, the present invention is not limited to this, and a portion of the second bump pad 39b may overlap the first pad metal layer 35a. However, the upper insulating layer 37 may be disposed between the first pad metal layer 35a and the second bump pad 39b to insulate them.

The first and second bump pads 39a and 39b may be formed of a metal layer and may include a plurality of layers. In particular, the first and second bump pads 39a and 39b may include Au or Pt.

The first solder bump 41a is disposed on the first bump pad 39a, and the second solder bump 41b is disposed on the second bump pad 39b. The first and second solder bumps 41a and 41b may include AgCuSn, for example.

The first and second solder bumps 41a and 41b are formed by placing solder paste containing solder powder and flux on the first and second bump pads 39a and 39b, respectively, and then applying flux using a reflow process. It can be formed by removing . Accordingly, the first and second solder bumps 41a and 41b may have a bottom area that is the same as the area of the first bump pads 39a and 39b, respectively.

Meanwhile, the first and second solder bumps 41a and 41b are relatively thicker than the first and second bump pads 39a and 39b. For example, the thickness T2 of the first or second solder bump 41a or 41b may be 10 to 80 times the thickness T1 of the first or second bump pad 39a or 39b. Specifically, the first and second bump pads 39a and 39b may have a thickness of approximately 1 um, while the first and second solder bumps 41a and 41b may have a thickness of 10 um to 100 um. .

Additionally, the first and second solder bumps 41a and 41b may have inclined side surfaces and a generally trapezoidal cross-sectional shape. As shown in FIG. 3, the inclination angle θ of the side surface of the first and second solder bumps 41a and 41b with respect to the bottom surface may be in the range of about 65 degrees to 75 degrees. When the inclination angle θ is within the above range, the solder bumps 41a and 41b can be easily formed, and further, the light emitting diode 100 can be easily transferred.

Meanwhile, as shown in FIG. 4, the gap s1 between the first solder bump 41a and the second solder bump 41b, the first and second solder bumps 41a and 41b and the substrate 21 The gaps s2 and S3 between the edges need to be controlled. For example, the gap s1 is more than twice the thickness of the first and second solder bumps 41a and 41b. The upper limit of the gap s1 is not particularly limited, but may not exceed 10 times in order to secure a sufficient area of the solder bumps 41a and 41b.

Meanwhile, the intervals s2 and s3 may be 1/2 or more of the interval s1. Furthermore, the gaps s2 and s3 may be equal to or greater than the thickness T2 of the first and second solder bumps 41a and 41b. By controlling the gaps s1, s2, and s3, the first and second solder bumps 41a, 41b can be easily formed using screen printing technology, and electrical short circuits between the solder bumps can be prevented. .

According to an embodiment of the present invention, a reflective structure of a conductive oxide layer 28, a dielectric layer 29, and a metal reflective layer 31 is used instead of the conventional ohmic reflective layer. Accordingly, penetration of bonding materials such as solder into the contact area can be prevented, and stable ohmic contact resistance can be secured to improve the reliability of the light emitting diode. Moreover, by setting the thickness of the dielectric layer 29 to 300 nm or more, high light output and low forward voltage can be achieved.

Furthermore, by forming the first and second solder bumps 41a and 41b on the first and second bump pads 39a and 39b, the amount of solder paste used in the mounting process of the light emitting diode can be reduced. , the light emitting diode mounting process can be simplified.

In addition, the light emitting diode can be easily handled by disposing the solder bumps 41a and 41b with a thickness of more than 10 times that of the first and second bump pads 39a and 39b.

Figures 5A to 5F are schematic cross-sectional views for explaining a light-emitting device manufacturing process according to an embodiment of the present invention. Here, a process of forming solder bumps 41a and 41b using screen printing technology and mounting them on a mounting surface using the solder bumps 41a and 41b is described.

First, referring to FIG. 5A, a substrate 21 on which bump pads 39a and 39b are formed is prepared. Although not shown, on the substrate 21, a first conductive semiconductor layer 23, an active layer 25, a second conductive semiconductor layer 27, and a conductive oxide layer 28 as described with reference to FIGS. 1 and 2 are formed. ), a dielectric layer 29, a metal reflection layer 31, a lower insulating layer 33, a first pad metal layer 35a, a second pad metal layer 35b), and an upper insulating layer 37 may be formed. The first and second bump pads 39a and 39b may be disposed on the upper insulating layer 37.

A plurality of light emitting diode regions are disposed on the substrate 21, and first and second bump pads 39a and 39b may be formed in each region.

Referring to FIG. 5B, a mask 110 is disposed on the substrate 21. The mask 110 has openings that expose the bump pads 39a and 39b, and the mask 110 is disposed so that the openings are aligned with the bump pads 39a and 39b. The height of the openings may be about 20um or more, and may be about 300um or less.

Next, solder paste 40 fills the openings of mask 110. Solder paste 40 may be applied using, for example, a squeeze printing technique. Accordingly, solder paste 40 having a thickness approximately corresponding to the height of the opening is disposed on the bump pads.

Referring to FIG. 5C, the mask 110 is removed and the solder face is reflowed through a reflow process. Accordingly, the solder paste is aggregated to form a solder bump 40a having an inclined side and a convex upper surface. During the reflow process, most of the flux in the solder paste can be removed.

In order to remove the mask 110, the gap between the solder pastes 40 needs to be greater than or equal to the thickness of the solder paste 40. If the gap between the solder pastes 40 is too narrow, the solder pastes 40 may be connected to each other, making it difficult to remove the mask 110.

Meanwhile, during the reflow process, the first and second bump pads 39a and 39b and the solder may diffuse and mix with each other. Accordingly, the boundary between the first and second bump pads 39a and 39b and the solder bump 40a may not be clear. However, when the first and second bump pads 39a and 39b are formed of multiple metal layers, some may be mixed with the solder and some may remain.

Referring to FIG. 5D, first and second solder bumps 41a and 41b are formed by removing part of the thickness of the solder bumps 40a. Solder bumps 40a may be cut using a cutting process such as flying cut technology, for example.

In particular, the solder bumps 40a can be cut by more than 50%. Accordingly, the first and second solder bumps 41a and 41b may be formed to have a thickness of less than 1/2 the height of the opening of the mask 110. If the cutting of the solder bumps 40a is less than 50%, process defects are likely to occur due to poor adhesion of the solder bumps 41a and 41b when transferring the light emitting diodes.

Referring to FIG. 5E, individual light emitting diodes 100 are completed by dividing the substrate 21. Before dividing the substrate 21, a process of reducing the thickness by grinding the bottom surface of the substrate 21 may be added. The process of reducing the thickness of the substrate 21 may be performed before printing the solder paste.

Meanwhile, although the drawing shows two light emitting diodes 100 being formed, hundreds or thousands of light emitting diodes 100 may be formed on one substrate 21.

Referring to FIG. 5F, the light emitting diode 100 is bonded on the sub-mount substrate 51 having connection pads 51a and 51b. The solder bumps 41a and 41b of the light emitting diode 100 are aligned on the connection pads 51a and 51b, and the light emitting diode 100 is attached to the sub-mount substrate 51 by bonding technology using a reflow process. It can be bonded.'

In this case, solder paste may be applied in advance on the connection pads 51a and 51b. However, as the solder bumps 41a and 41b are disposed on the light emitting diode 100, the amount of solder paste applied on the connection pads 51a and 51b can be significantly reduced compared to the prior art.

Accordingly, a light emitting device is provided in which the connection pads 51a and 51b and the first and second bump pads 41a and 41b are bonded to each other by solder 141a and 141b.

Here, it is described that the light emitting diode 100 is mounted on the sub-mount board 51, but a printed circuit board may be used instead of the sub-mount board 51, or a package having leads may be used.

Accordingly, various types of light-emitting devices, such as a light-emitting diode package or a light-emitting module in which the light-emitting diode 100 is mounted, can be provided.

FIG. 6 is a schematic plan view for explaining a light emitting diode 200 according to another embodiment of the present invention, FIG. 7 is a schematic circuit diagram for explaining the light emitting diode of FIG. 6, and FIG. 8 is a perforated line of FIG. 6. It is a schematic cross-sectional view taken along line B-B, and Figure 9 is a schematic cross-sectional view taken along line C-C of Figure 6.

Referring to FIGS. 6 to 9, the light emitting diode according to this embodiment is generally similar to the embodiment previously described with reference to FIG. 1, but has a plurality of light emitting cells C1, C2, C3, and C4 on the substrate 21. ) There is a difference in how they are arranged. These light emitting cells (C1, C2, C3, C4) may be connected in series between the first bump pad (39a) and the second bump pad (39b) as shown in FIG. 7.

The first to fourth light emitting cells C1, C2, C3, and C4 are disposed on the substrate 21. The first to fourth light emitting cells C1, C2, C3, and C4 are spaced apart from each other by a separation area exposing the substrate 21. The upper surface of the substrate 21 may be exposed in the area between the light emitting cells.

In this embodiment, the first and second light emitting cells C1 and C2 are shown as being disposed below and the third and fourth light emitting cells C3 and C4 are shown as being placed above. The four light emitting cells (C1, C2, C3, C4) can be arranged in various ways. Additionally, in this embodiment, four light emitting cells are shown and described arranged on the substrate 21, but the number of light emitting cells is not particularly limited. For example, two light-emitting cells or seven light-emitting cells may be arranged on the substrate 21.

Each light emitting cell includes a first conductive semiconductor layer 23 and a mesa (M). Since the first conductive semiconductor layer 23 and the mesa (M) are the same as previously described with reference to FIGS. 1 and 2, detailed descriptions of the same items will be omitted to avoid duplication.

The mesa (M) may be located limited to the inside of the area surrounded by the first conductive semiconductor layer 23, and therefore, the areas near the edge adjacent to the outer surfaces of the first conductive semiconductor layer 23 are the mesa (M). ) and is exposed to the outside.

In this embodiment, each mesa M may include via holes 27a, and the first conductivity type semiconductor layer 23 is exposed within each via hole 27a.

Meanwhile, a conductive oxide layer 28 is disposed on each mesa (M), and the dielectric layers 29 form the conductive oxide layer 28 and the mesa (M) on the light emitting cells (C1, C2, C3, C4), respectively. Cover. The conductive oxide layer 28 makes ohmic contact with the second conductive semiconductor layer 27. The conductive oxide layer 28 may be disposed over almost the entire area of the mesa (M) in the upper area of the mesa (M). However, the conductive oxide layer 28 may be spaced apart from the edge of the mesa (M).

The dielectric layer 29 covers the upper area and side surfaces of the mesa (M), and may cover the first conductive semiconductor layer exposed around the mesa (M). Dielectric layer 29 also has openings 29a exposing conductive oxide layer 28. The dielectric layer 29 is located in the upper region of the first conductivity type semiconductor layer 23, and therefore, the dielectric layers 29 on different light emitting cells can be spaced apart from each other. However, the present invention is not necessarily limited to this, and dielectric layers on adjacent light-emitting cells may be connected to each other.

The metal reflective layer 31 is disposed on the dielectric layer 29 and connects to the conductive oxide layer 28 through the openings 29a of the dielectric layer 29. The metal reflective layer 31 is disposed in the upper area of the mesa (M) of each light emitting cell (C1, C2, C3, C4).

The lower insulating layer 33 covers the mesas M and covers the metal reflective layer 31 and the dielectric layer 29. The lower insulating layer 33 also covers the first conductive semiconductor layer 23 and the substrate 21 exposed to the outside of the dielectric layer 29. When the substrate 21 is a patterned sapphire substrate, the lower insulating layer 33 may be formed along the shape of the protrusions on the substrate 21.

As shown, the edge of the lower insulating layer 33 may be located on the first conductive semiconductor layer 23 of each light-emitting cell, but is not limited to this, and the first conductive semiconductor layer 23 It may cover the side of and be located on the substrate 21.

The lower insulating layer 33 has first openings 33a exposing the first conductivity type semiconductor layer 23 within the via holes 27a of each mesa (M), and also has first openings 33a exposing the first light emitting cell C1. ) and second openings 33b1 exposing the metal reflection layer 31 on the second to third light emitting cells C2, C3, and C4. .

In this embodiment, the lower insulating layer 33 does not include an opening exposing the first conductivity type semiconductor layer 23 around the mesa (M). However, the present invention is not limited to this, and the lower insulating layer 33 may include an opening that exposes the first conductive semi-couple layer 23 around the mesa.

The second opening 33b1 is disposed on the first light emitting cell C1, and the second openings 33b2 expose the metal reflective layer 31 of each light emitting cell near the separation area of the light emitting cells. The second openings 33b2 may generally have an elongated shape along the separation area, but are not limited thereto and may have various shapes.

Meanwhile, the second opening 33b1 is located on the first light emitting cell C1 and may be located in a lower area of the second bump pad 39b. However, in another embodiment, the second opening 33b1 may be arranged to be spaced apart in the horizontal direction from the second bump pad 39b on the first light emitting cell C1.

The lower insulating layer 33 may be formed of a single layer or multiple layers, as described with reference to FIGS. 1 and 2, or may include a distributed Bragg reflector. Additionally, the lower insulating layer 33 may further include a capping layer covering the distributed Bragg reflector.

Meanwhile, the first pad metal layer 35a, the second pad metal layer 35b, and the connection metal layer 35c are disposed on the lower insulating layer 33.

The first pad metal layer 35a is disposed on the fourth light emitting cell C4 and makes ohmic contact with the first conductive semiconductor layer 23 exposed in the via holes 27a of the mesa (M). In this embodiment, the first pad metal layer 35a is shown contacting the first conductivity type semiconductor layer 23 within the via holes 27a, but the first conductivity type semiconductor layer 23 is around the mesa (M). ) may come into contact with. However, by disposing the first pad metal layer 35a in the upper area of the mesa (M), it can be spaced far away from the edge of the substrate 21, and accordingly, the first pad metal layer 35a is positioned on the side of the substrate 21. It can prevent damage from moisture entering from the side.

The second pad metal layer 35b is disposed on the first light emitting cell C1 and can be electrically connected to the metal reflection layer 31 through the second opening 33b1. Accordingly, the second pad metal layer 35b is electrically connected to the second conductive semiconductor layer 27 of the first light emitting cell C1.

The second pad metal layer 35b is located on the mesa (M) and is insulated from the first conductive semiconductor layer 23. Furthermore, the second pad metal layer 35b may be spaced apart from the sides of the mesa M on the first light emitting cell C1. Accordingly, the second pad metal layer 35b can be prevented from being damaged by moisture entering from the side of the substrate 21.

Meanwhile, the connecting metal layers 35c connect neighboring light emitting cells to each other in series. The connecting metal layers 35c connect the first conductive semiconductor layer 23 and the second conductive semiconductor layer of neighboring light emitting cells through the first opening 33a and the second opening 33b2 of the lower insulating layer 33. It can be electrically connected to (27). For example, one connection metal layer 35c is electrically connected to the first conductive semiconductor layer 23 in the first light emitting cell C1, and the metal reflection layer 31 on the second light emitting cell C2 can be electrically connected to. Accordingly, the first light emitting cell (C1) and the second light emitting cell (C2) are connected in series to each other through the connecting metal layer (33c). In this way, the second light emitting cell (C2) and the third light emitting cell (C3) can be connected in series through the connecting metal layer (35c), and the third light emitting cell (C3) and the fourth light emitting cell (C4) can be connected in series through the connecting metal layer (35c). ) can be connected in series.

The connecting metal layers 35c are spaced apart from the first pad metal layer 35a and the second pad metal layer 35b. Furthermore, the connecting metal layers 35c may be formed to have a width narrower than the mesa M, and thus may be spaced farther from the edge of the substrate 21 than the mesa M.

The first and second pad metal layers 35a and 35b and the connecting metal layers 35c may be formed together with the same material through the same process. For example, the first and second pad metal layers 35a, 35b and the connecting metal layers 35c may include an ohmic reflective layer such as an Al layer, and the ohmic reflective layer is formed on an adhesive layer such as Ti, Cr, or Ni. It can be. Additionally, a protective layer having a single or multiple layer structure of Ni, Cr, Au, etc. may be formed on the ohmic reflection layer. The first and second pad metal layers 35a and 35b and the connecting metal layers 35c may have a multilayer structure of, for example, Cr/Al/Ni/Ti/Ni/Ti/Au/Ti.

The upper insulating layer 37 is disposed on the first pad metal layer 35a, the second pad metal layer 35b, and the connecting metal layers 35c, and has a first opening 37a exposing the first pad metal layer 35a. and a second opening 37b exposing the second pad metal layer 35b. The upper insulating layer 37 may cover the upper surface of the substrate 21 exposed around the light emitting cells 21. The upper insulating layer 37 may cover the edge of the substrate 21 as shown, but is not limited to this, and the edge of the upper insulating layer 37 may be located inside the edge of the substrate 21.

Meanwhile, the first opening 37a is disposed in the upper region of the first pad metal layer 35a, and is thus spaced apart from the connecting metal layer 35c and the second opening 33b2 of the lower insulating layer 33. Additionally, the second opening 37b is also located limited on the second pad metal layer 35b and is spaced apart from the connection metal layer 35c.

In this embodiment, the first and second pad metal layers 35a, 35b exposed through the first and second openings 37a, 37b of the upper insulating layer 37 have solder bumps 41a, 41b) can be used as formed bump pads. In contrast, as described with reference to FIGS. 1 and 2, the first and second bump pads 39a and 39b are exposed through the first and second openings 37a and 37b of the upper insulating layer 37. may cover the first and second pad metal layers 35a and 35b, respectively. The first and second bump pads 39a and 39b may be disposed across a plurality of light emitting cells, respectively, and may cover and seal the first and second openings 37a and 37b.

The first solder bump 41a and the second solder bump 41b are disposed on the first bump pad 39a and the second bump pad 39b, respectively. The first and second solder bumps 41a and 41b may have bottom surfaces of the same shape as the first bump pad 39a and the second bump pad 39b. Meanwhile, the thickness of the first solder bump 41a and the second solder bump 41b, the gap between them, and the gap between them and the edge of the substrate 21 are as described with reference to FIGS. 3 and 4. To avoid duplication, detailed descriptions are omitted.

10 and 11 are schematic plan views for explaining light emitting diodes 200a and 200b according to still other embodiments of the present invention.

Referring to FIG. 10, the light emitting diode 200a according to this embodiment is generally similar to the light emitting diode described with reference to FIGS. 6 to 9, but there is a difference in the shapes of the first and second bump pads 39a and 39b. There is a difference in the shapes of the first and second solder bumps 41a and 41b.

That is, in the light emitting diode 200, the first and second bump pads 39a and 39b have a generally elongated rectangular shape and are each arranged across a plurality of light emitting cells. In contrast, in the light emitting diode 200a, the first and second bump pads 39a and 39b are each disposed across a plurality of light emitting cells, but include a narrow region in the area between the light emitting cells.

The first and second solder bumps 41a and 41b cover the first and second bump pads 39a and 39a and may be formed in the same shape as the first and second bump pads 39a and 39b. You can.

Referring to FIG. 11, the light emitting diode 200b according to this embodiment is generally similar to the light emitting diode 200 described with reference to FIGS. 6 to 9, but the first and second bump pads 39a and 39b are The difference is that dummy bump pads 39c are disposed on single light emitting cells C4 and C1, respectively, and dummy bump pads 39c are disposed on other light emitting cells C2 and C3.

The dummy bump pads 39c are formed on the upper insulating layer 37 together with the first and second bump pads 39a and 39b in the same process. However, the dummy bump pads 39c are electrically separated from the first to fourth light emitting cells C1, C2, C3, and C4 by the upper insulating layer 37.

Meanwhile, the first and second solder bumps 41a and 41b are disposed on the first and second bump pads 39a and 39b, respectively, and a dummy solder bump 41c is disposed on the dummy bump pad 39c. can be placed. The dummy solder bump 41c may be omitted, thus reducing the amount of solder paste for forming the solder bump.

In this embodiment, a light emitting diode including four light emitting cells is taken as an example, but the light emitting diode may include more light emitting cells than four. In this case, the solder bumps can be arranged to stabilize the mounting process of the light emitting diode. For example, a first solder bump may be disposed across at least two light emitting cells arranged close to one edge of the substrate, and a second solder bump may be disposed across at least two light emitting cells arranged close to the other edge of the substrate. there is. Alternatively, a dummy solder bump may be disposed on at least one of at least two light emitting cells disposed close to one edge of the substrate, and a first solder bump may be disposed on at least one of the other light emitting cells. Additionally, a dummy solder bump may be disposed on at least one of at least two light emitting cells disposed close to the other edge of the substrate, and a second solder bump may be disposed on at least one of the other light emitting cells.

Figure 12 is an exploded perspective view to explain a lighting device using a light emitting diode according to an embodiment of the present invention.

Referring to FIG. 12, the lighting device according to this embodiment includes a diffusion cover 1010, a light emitting device module 1020, and a body portion 1030. The body portion 1030 may accommodate the light emitting device module 1020, and the diffusion cover 1010 may be disposed on the body portion 1030 to cover the top of the light emitting device module 1020.

The body portion 1030 is not limited as long as it can accommodate and support the light emitting device module 1020 and supply electrical power to the light emitting device module 1020. For example, as shown, the body portion 1030 may include a body case 1031, a power supply device 1033, a power case 1035, and a power connection unit 1037.

The power supply device 1033 is accommodated in the power case 1035 and is electrically connected to the light emitting device module 1020, and may include at least one IC chip. The IC chip can adjust, convert, or control the characteristics of the power supplied to the light emitting device module 1020. The power case 1035 may accommodate and support the power supply device 1033, and the power case 1035 with the power supply device 1033 fixed therein may be located inside the body case 1031. . The power connection unit 115 may be disposed at the bottom of the power case 1035 and coupled to the power case 1035. Accordingly, the power connection unit 1037 is electrically connected to the power supply device 1033 inside the power case 1035 and can serve as a passage through which external power can be supplied to the power supply device 1033.

The light emitting device module 1020 includes a substrate 1023 and a light emitting device 1021 disposed on the substrate 1023. The light emitting device module 1020 may be provided on the upper part of the body case 1031 and electrically connected to the power supply device 1033.

The substrate 1023 is not limited as long as it can support the light emitting device 1021, and may be, for example, a printed circuit board including wiring. The substrate 1023 may have a shape corresponding to the fixing portion on the upper part of the body case 1031 so that it can be stably fixed to the body case 1031. The light emitting device 1021 may include at least one of the light emitting diodes according to the embodiments of the present invention described above.

The diffusion cover 1010 may be placed on the light emitting device 1021 and may be fixed to the body case 1031 to cover the light emitting device 1021. The diffusion cover 1010 may be made of a light-transmitting material, and the directivity characteristics of the lighting device may be adjusted by adjusting the shape and light transmittance of the diffusion cover 1010. Accordingly, the diffusion cover 1010 may be transformed into various forms depending on the purpose of use and application of the lighting device.

Figure 13 is a cross-sectional view for explaining a display device using a light emitting diode according to another embodiment of the present invention.

The display device of this embodiment includes a display panel 2110, a backlight unit that provides light to the display panel 2110, and a panel guide that supports a lower edge of the display panel 2110.

The display panel 2110 is not particularly limited and may be, for example, a liquid crystal display panel including a liquid crystal layer. A gate driving PCB that supplies a driving signal to the gate line may be further positioned at the edge of the display panel 2110. Here, the gate driving PCB may not be formed on a separate PCB but may be formed on a thin film transistor substrate.

The backlight unit includes a light source module including at least one substrate and a plurality of light emitting devices 2160. Furthermore, the backlight unit may further include a bottom cover 2180, a reflective sheet 2170, a diffusion plate 2131, and optical sheets 2130.

The bottom cover 2180 is opened upward and can accommodate a substrate, a light emitting element 2160, a reflective sheet 2170, a diffusion plate 2131, and optical sheets 2130. Additionally, the bottom cover 2180 may be combined with a panel guide. The substrate may be positioned below the reflective sheet 2170 and surrounded by the reflective sheet 2170. However, it is not limited to this, and if a reflective material is coated on the surface, it may be located on the reflective sheet 2170. In addition, the substrate may be formed in plural, and the plurality of substrates may be arranged side by side, but the present invention is not limited to this and may be formed as a single substrate.

The light emitting device 2160 may include a light emitting diode according to the embodiments of the present invention described above. The light emitting elements 2160 may be regularly arranged in a certain pattern on the substrate. Additionally, a lens 2210 is disposed on each light-emitting device 2160 to improve the uniformity of light emitted from the plurality of light-emitting devices 2160.

The diffusion plate 2131 and the optical sheets 2130 are located on the light emitting device 2160. Light emitted from the light emitting device 2160 may be supplied to the display panel 2110 in the form of a planar light source through the diffusion plate 2131 and the optical sheets 2130.

As such, the light emitting device according to the embodiments of the present invention can be applied to a direct display device such as the present embodiment.

Figure 14 is a cross-sectional view for explaining a display device using a light emitting diode according to another embodiment of the present invention.

A display device equipped with a backlight unit according to this embodiment includes a display panel 3210 on which an image is displayed, and a backlight unit disposed on the back of the display panel 3210 to irradiate light. Furthermore, the display device includes a frame 240 that supports the display panel 3210 and houses a backlight unit, and covers 3240 and 3280 that surround the display panel 3210.

The display panel 3210 is not particularly limited and may be, for example, a liquid crystal display panel including a liquid crystal layer. A gate driving PCB that supplies a driving signal to the gate line may be further positioned at the edge of the display panel 3210. Here, the gate driving PCB may not be formed on a separate PCB but may be formed on a thin film transistor substrate. The display panel 3210 is fixed by covers 3240 and 3280 located at the top and bottom, and the cover 3280 located at the bottom can be coupled to the backlight unit.

The backlight unit that provides light to the display panel 3210 includes a lower cover 3270 with a portion of the upper surface opened, a light source module disposed on one inner side of the lower cover 3270, and a light source module positioned in parallel with the light source module to emit point light. It includes a light guide plate 3250 that converts to surface light. In addition, the backlight unit of this embodiment includes optical sheets 3230 located on the light guide plate 3250 to diffuse and converge light, and disposed below the light guide plate 3250 to transmit light traveling in the lower direction of the light guide plate 3250. It may further include a reflective sheet 3260 that reflects in the direction of the display panel 3210.

The light source module includes a substrate 3220 and a plurality of light emitting elements 3110 arranged on one surface of the substrate 3220 at regular intervals. The substrate 3220 is not limited as long as it supports the light emitting device 3110 and is electrically connected to the light emitting device 3110. For example, it may be a printed circuit board. The light emitting device 3110 may include at least one light emitting diode according to the embodiments of the present invention described above. Light emitted from the light source module is incident on the light guide plate 3250 and supplied to the display panel 3210 through the optical sheets 3230. Through the light guide plate 3250 and the optical sheets 3230, a point light source emitted from the light emitting elements 3110 may be transformed into a planar light source.

In this way, the light emitting device according to the embodiments of the present invention can be applied to an edge-type display device such as this embodiment.

Figure 15 is a cross-sectional view illustrating an example of applying a light emitting diode to a headlamp according to another embodiment of the present invention.

Referring to FIG. 15, the headlamp includes a lamp body 4070, a substrate 4020, a light emitting element 4010, and a cover lens 4050. Furthermore, the headlamp may further include a heat dissipation unit 4030, a support rack 4060, and a connection member 4040.

The substrate 4020 is fixed by a support rack 4060 and spaced apart from the lamp body 4070. The substrate 4020 is not limited as long as it can support the light emitting device 4010, and may be, for example, a substrate with a conductive pattern such as a printed circuit board. The light emitting device 4010 is located on the substrate 4020 and can be supported and fixed by the substrate 4020. Additionally, the light emitting device 4010 can be electrically connected to an external power source through the conductive pattern of the substrate 4020. Additionally, the light emitting device 4010 may include at least one light emitting diode according to the embodiments of the present invention described above.

The cover lens 4050 is located on the path along which light emitted from the light emitting device 4010 travels. For example, as shown, the cover lens 4050 may be arranged to be spaced apart from the light-emitting device 4010 by the connecting member 4040, and may be placed in a direction to provide light emitted from the light-emitting device 4010. You can. The beam angle and/or color of light emitted from the headlamp to the outside may be adjusted by the cover lens 4050. Meanwhile, the connecting member 4040 fixes the cover lens 4050 to the substrate 4020 and may also serve as a light guide that is arranged to surround the light emitting element 4010 and provides a light emission path 4045. At this time, the connecting member 4040 may be formed of a light-reflective material or coated with a light-reflective material. Meanwhile, the heat dissipation unit 4030 may include a heat dissipation fin 4031 and/or a heat dissipation fan 4033, and radiates heat generated when the light emitting device 4010 is driven to the outside.

As such, the light-emitting device according to the embodiments of the present invention can be applied to a headlamp like this embodiment, especially a headlamp for a vehicle.

In the above, various embodiments of the present invention have been described, but the present invention is not limited to these embodiments. Additionally, matters or components described in one embodiment may be applied to other embodiments as long as they do not depart from the technical spirit of the present invention.

Claims (23)

Mounting surface with connection pads; and
It includes a light emitting diode mounted on the mounting surface through a first solder and a second solder,
The light emitting diode is
A first conductive semiconductor layer;
an active layer disposed on the first conductive semiconductor layer;
a second conductive semiconductor layer disposed on the active layer;
a transparent conductive oxide layer electrically connected to the second conductive semiconductor layer;
a dielectric layer covering the conductive oxide layer and having a plurality of openings exposing the conductive oxide layer;
a metal reflective layer disposed on the dielectric layer and connected to the conductive oxide layer through openings in the dielectric layer;
a lower insulating layer disposed on the metal reflective layer and including a first opening exposing the first conductive semiconductor layer and a second opening exposing the metal reflective layer;
a first pad metal layer disposed on the lower insulating layer and electrically connected to the first conductive semiconductor layer through a first opening in the lower insulating layer;
a second pad metal layer disposed on the lower insulating layer and electrically connected to the second conductive semiconductor layer through a second opening in the lower insulating layer;
an upper insulating layer disposed on the first pad metal layer and the second pad metal layer and having openings exposing the first pad metal layer and the second pad metal layer;
a first bump pad electrically connected to the first pad metal layer and the first conductive semiconductor layer through an opening in the upper insulating layer; and
a second bump pad electrically connected to the second pad metal layer and the second conductive semiconductor layer through an opening in the upper insulating layer;
The first and second solders bond the connection pads and the first and second bump pads,
The first solder and the second solder have a thickness in the range of 10 to 80 times the thickness of the first bump pad and the second bump pad. In claim 1,
The first solder and the second solder have inclined sides, and the inclination angle of the inclined sides is in the range of 65 degrees to 75 degrees with respect to the bottom surface. In claim 1,
A light emitting device wherein the gap between the first solder and the second solder is 2 to 10 times the thickness of the first solder or the second solder. In claim 1,
Further comprising a substrate disposed under the first conductive semiconductor layer,
A light emitting device wherein the shortest distance in the horizontal direction between the first solder or the second solder and an edge of the substrate is equal to or greater than the thickness of the first solder and the second solder. delete In claim 1,
The first and second solders cover the entire upper surfaces of the first and second bump pads, respectively. In claim 1,
A light emitting device wherein a gap between the first bump pad and the second bump pad is 2 to 10 times the thickness of the first solder or the second solder. In claim 1,
Further comprising a substrate disposed under the first conductive semiconductor layer,
A light emitting device wherein the shortest horizontal distance between the first bump pad or the second bump pad and an edge of the substrate is equal to or greater than the thickness of the first solder and the second solder. delete In claim 1,
Board; and
Further comprising a plurality of light emitting cells arranged on the substrate,
Each of the light emitting cells includes the first conductivity type semiconductor layer, the active layer, and the second conductivity type semiconductor layer,
The first bump pad is electrically connected to a first conductivity type semiconductor layer of one light emitting cell among the plurality of light emitting cells,
The second bump pad is a light emitting device electrically connected to a second conductive semiconductor layer of another light emitting cell among the plurality of light emitting cells. In claim 10,
Further comprising a dummy bump pad disposed on another light emitting cell among the plurality of light emitting cells,
The dummy bump pad is a light emitting device that is electrically spaced apart from the light emitting cells. In claim 10,
The first bump pad and the second bump pad are each disposed across at least two light emitting cells. In claim 12,
The first and second bump pads are a light emitting device including narrow areas in areas between light emitting cells. delete delete delete In claim 1,
Further comprising a substrate disposed under the first conductive semiconductor layer,
A light emitting device wherein the shortest distance in the horizontal direction between the first solder or the second solder and the substrate is more than 1/2 of the gap between the first solder and the second solder.
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