KR102601421B1 - Chip scale packaged light emitting diode - Google Patents

Abstract

A chip scale packaged light emitting diode is provided. A light emitting diode according to an embodiment includes a first conductive semiconductor layer; a mesa located on the first conductivity type semiconductor layer and including an active layer and a second conductivity type semiconductor layer; A conductive oxide layer disposed on the mesa; a dielectric layer having a plurality of openings exposing the conductive oxide layer and having a lower refractive index than the second conductive semiconductor layer and the conductive oxide layer; a metallic reflective layer connected to the conductive oxide layer through openings in the dielectric layer; a lower insulating layer including a first opening exposing the first conductive semiconductor layer and a second opening exposing the metal reflective layer; a first pad metal layer electrically connected to the first conductive semiconductor layer through the first opening; a second pad metal layer electrically connected to the metal reflection layer through a second opening; and an upper insulating layer that covers the first pad metal layer and the second pad metal layer and includes a first opening exposing the first pad metal layer and a second opening exposing the second pad metal layer, wherein the openings of the dielectric layer are and a narrow, elongated bar-shaped opening adjacent to at least one of the first openings of the lower insulating layer.

Description

Chip scale package light emitting diode {CHIP SCALE PACKAGED LIGHT EMITTING DIODE}

The present invention relates to light emitting diodes, and more specifically to light emitting diodes in chip scale package form.

In general, nitrides of group III elements such as gallium nitride (GaN) and aluminum nitride (AlN) have excellent thermal stability and have a direct transition energy band structure, so they have recently been used as light source materials in the visible and ultraviolet regions. is receiving a lot of attention. In particular, blue and green light-emitting diodes using indium gallium nitride (InGaN) are used in various application fields such as large-scale color flat panel displays, traffic lights, indoor lighting, high-density light sources, high-resolution output systems, and optical communications.

Recently, research on light emitting diodes in the form of chip-scale packages in which the packaging process is performed at the chip level is in progress. Since these light emitting diodes are smaller than regular packages and do not require a separate packaging process, the process can be further simplified, saving time and cost.

Light emitting diodes in the form of chip-scale packages generally have a flip-chip-shaped electrode structure and use an ohmic reflection layer to emit light toward the substrate. By adopting a flip chip-shaped electrode structure, a light emitting diode with excellent luminous efficiency and heat dissipation characteristics can be provided. However, the ohmic reflection layer of these light emitting diodes may be contaminated due to diffusion of solder used during flip bonding, which may result in light emitting diode defects.

Therefore, efforts are being made to simplify the structure of the light emitting diode and provide a reliable light emitting diode.

In addition, light emitting diodes in the form of chip-scale packages cannot incorporate separate protection elements for electrical overload or electrostatic discharge, so strong resistance to these is required.

The problem to be solved by the present invention is to provide a light emitting diode that can improve reliability by efficiently preventing the diffusion of bonding materials such as solder.

Another problem to be solved by the present invention is to provide a chip-scale packaged light emitting diode having a reflective structure with high reflectivity.

Another problem to be solved by the present invention is to provide a chip-scale packaged light emitting diode that is resistant to electrical overstress or electrostatic discharge.

A light emitting diode according to an embodiment of the present invention includes a first conductivity type semiconductor layer; a mesa located on the first conductivity type semiconductor layer and including an active layer and a second conductivity type semiconductor layer; a transparent conductive oxide layer disposed on the mesa and electrically connected to the second conductive semiconductor layer; a dielectric layer covering the conductive oxide layer and having a plurality of openings exposing the conductive oxide layer; a metal reflective layer disposed on the dielectric layer and connected to the conductive oxide layer through openings in the dielectric layer; a lower insulating layer that covers the mesa and the metal reflective layer and includes at least one first opening exposing the first conductive semiconductor layer and a second opening exposing the metal reflective layer; a first pad metal layer disposed on the lower insulating layer and electrically connected to the first conductive semiconductor layer through the at least one first opening; a second pad metal layer disposed on the lower insulating layer and electrically connected to the metal reflection layer through the second opening; and an upper insulating layer covering the first pad metal layer and the second pad metal layer, the dielectric layer including a first opening exposing the first pad metal layer and a second opening exposing the second pad metal layer. The openings include a narrow, elongated bar-shaped opening adjacent to at least one of the first openings of the lower insulating layer.

A light emitting diode according to another embodiment of the present invention includes a first conductivity type semiconductor layer; a mesa located on the first conductivity type semiconductor layer and including an active layer and a second conductivity type semiconductor layer; a transparent conductive oxide layer disposed on the mesa and electrically connected to the second conductive semiconductor layer; a dielectric layer covering the conductive oxide layer and having a plurality of openings exposing the conductive oxide layer; a metal reflective layer disposed on the dielectric layer and connected to the conductive oxide layer through openings in the dielectric layer; a lower insulating layer that covers the mesa and the metal reflective layer and includes at least one first opening exposing the first conductive semiconductor layer and a second opening exposing the metal reflective layer; a first pad metal layer disposed on the lower insulating layer and electrically connected to the first conductive semiconductor layer through the at least one first opening; a second pad metal layer disposed on the lower insulating layer and electrically connected to the metal reflection layer through the second opening; and an upper insulating layer covering the first pad metal layer and the second pad metal layer, the dielectric layer including a first opening exposing the first pad metal layer and a second opening exposing the second pad metal layer. The openings include openings having different sizes, wherein at least one of the openings in the dielectric layer adjacent to the first opening in the upper insulating layer is at least one of the openings in the dielectric layer disposed farther from the first opening in the upper insulating layer. It has a width or length greater than one opening.

A light emitting diode according to another embodiment of the present invention includes a first conductivity type semiconductor layer; a mesa located on the first conductivity type semiconductor layer and including an active layer and a second conductivity type semiconductor layer; a transparent conductive oxide layer disposed on the mesa and electrically connected to the second conductive semiconductor layer; a dielectric layer covering the conductive oxide layer and having a plurality of openings exposing the conductive oxide layer; a metal reflective layer disposed on the dielectric layer and connected to the conductive oxide layer through openings in the dielectric layer; a lower insulating layer that covers the mesa and the metal reflective layer and includes at least one first opening exposing the first conductive semiconductor layer and a second opening exposing the metal reflective layer; a first pad metal layer disposed on the lower insulating layer and electrically connected to the first conductive semiconductor layer through the at least one first opening; a second pad metal layer disposed on the lower insulating layer and electrically connected to the metal reflection layer through the second opening; and an upper insulating layer covering the first pad metal layer and the second pad metal layer, the dielectric layer including a first opening exposing the first pad metal layer and a second opening exposing the second pad metal layer. The openings include openings located below the first opening of the upper insulating layer, and from the first opening among the openings located below the first opening of the upper insulating layer and adjacent to the first opening of the lower insulating layer. The separation distance of the openings spaced apart in the vertical direction is longer than the separation distance of the openings of the dielectric layer closest to the first opening.

According to embodiments of the present invention, a reflective structure of a conductive oxide layer, a dielectric layer, and a metal reflective layer is used instead of a conventional ohmic reflective layer. Accordingly, penetration of bonding materials such as solder into the contact area can be prevented, and stable ohmic contact resistance can be secured to improve the reliability of the light emitting diode. Moreover, high light output and low forward voltage can be achieved by adjusting the thickness of the dielectric layer.

Additionally, according to embodiments of the present invention, a light emitting diode that is resistant to electrical overload or electrostatic discharge can be provided by controlling the position, size, or shape of openings formed in the dielectric layer.

Other advantages and effects of the present invention will become clearer through the detailed description.

1 is a schematic plan view for explaining a light emitting diode according to an embodiment of the present invention.
Figure 2 is a cross-sectional view taken along line AA in Figure 1.
Figure 3 is a graph schematically showing the doping profile of p-type impurities in the second conductivity type semiconductor layer.
FIGS. 4A and 4B are graphs showing forward voltage and light output according to the thickness of the dielectric layer, respectively.
Figure 5 is a schematic plan view for explaining a light emitting diode according to another embodiment of the present invention.
Figure 6 is a cross-sectional view taken along line BB in Figure 5.
Figure 7 is a schematic plan view for explaining a light emitting diode according to another embodiment of the present invention.
Figure 8 is a schematic plan view for explaining a light emitting diode according to another embodiment of the present invention.
Figure 9 is a schematic plan view for explaining a light emitting diode according to another embodiment of the present invention.
Figure 10 is a schematic plan view for explaining a light emitting diode according to another embodiment of the present invention.
Figure 11 is a schematic plan view for explaining a light emitting diode according to another embodiment of the present invention.
Figure 12 is a schematic plan view for explaining a light emitting diode according to another embodiment of the present invention.
Figure 13 is a schematic plan view for explaining a light emitting diode according to another embodiment of the present invention.
Figure 14 is a schematic cross-sectional view taken along line CC of Figure 13.
Figure 15 is a schematic plan view for explaining a light emitting diode according to another embodiment of the present invention.
Figure 16 is a schematic plan view for explaining a light emitting diode according to another embodiment of the present invention.
Figure 17 is an exploded perspective view to explain a lighting device using a light emitting diode according to an embodiment of the present invention.
Figure 18 is a cross-sectional view illustrating a display device using a light emitting diode according to another embodiment of the present invention.
Figure 19 is a cross-sectional view for explaining a display device using a light emitting diode according to another embodiment of the present invention.
Figure 20 is a cross-sectional view illustrating an example of applying a light emitting diode to a headlamp according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. The embodiments introduced below are provided as examples so that the idea of the present invention can be sufficiently conveyed to those skilled in the art. Accordingly, the present invention is not limited to the embodiments described below and may be embodied in other forms. And in the drawings, the width, length, thickness, etc. of components may be exaggerated for convenience. Additionally, when one component is described as being "on top of" or "on" another component, it means that each component is "directly on" or "directly on" the other component, as well as when each component is described as being "directly on" or "directly on" the other component. This also includes cases where another component is interposed. Like reference numerals refer to like elements throughout the specification.

A light emitting diode according to an embodiment of the present invention includes a first conductivity type semiconductor layer; a mesa located on the first conductivity type semiconductor layer and including an active layer and a second conductivity type semiconductor layer; a transparent conductive oxide layer disposed on the mesa and electrically connected to the second conductive semiconductor layer; a dielectric layer that covers the conductive oxide layer, has a plurality of openings exposing the conductive oxide layer, and has a lower refractive index than the second conductive semiconductor layer and the conductive oxide layer; a metal reflective layer disposed on the dielectric layer and connected to the conductive oxide layer through openings in the dielectric layer; a lower insulating layer that covers the mesa and the metal reflective layer and includes a first opening exposing the first conductive semiconductor layer and a second opening exposing the metal reflective layer; a first pad metal layer disposed on the lower insulating layer and electrically connected to the first conductive semiconductor layer through the first opening; a second pad metal layer disposed on the lower insulating layer and electrically connected to the metal reflection layer through the second opening; and an upper insulating layer covering the first pad metal layer and the second pad metal layer, the dielectric layer including a first opening exposing the first pad metal layer and a second opening exposing the second pad metal layer. has a thickness ranging from 4 to 13 times the thickness of the second conductive semiconductor layer.

The dielectric layer may have a thickness ranging from 200 nm to 1000 nm, and specifically, may have a thickness ranging from 300 nm to 800 nm. High optical output and low forward voltage can be achieved in this thickness range.

Meanwhile, the conductive oxide layer may have a thickness within the range of 3 nm to 50 nm, and specifically, may have a thickness within the range of 6 nm to 30 nm. Within this thickness range, good ohmic contact resistance can be secured and loss due to light absorption can be reduced.

Additionally, the dielectric layer may cover a side of the mesa and partially cover a first conductivity type semiconductor layer around the mesa.

Furthermore, the lower insulating layer may cover an edge of the dielectric layer.

Meanwhile, the first opening of the lower insulating layer exposes the first conductive semiconductor layer along the perimeter of the mesa, and the first pad metal layer is an external contact portion contacting the first conductive semiconductor layer along the perimeter of the mesa. You can have Since the first pad metal layer contacts the first conductive semiconductor layer along the mesa perimeter, the current dispersion performance of the light emitting diode can be improved.

Additionally, the mesa may include a recessed portion exposing the first conductive semiconductor layer, and the first opening of the lower insulating layer may further expose the first conductive semiconductor layer within the recessed portion. Furthermore, the first pad metal layer may further include an internal contact part that contacts the first conductive semiconductor layer within the indented part. Since the first pad metal layer contacts the first conductive semiconductor layer around and inside the mesa, the current dispersion performance of the light emitting diode is further enhanced.

Furthermore, the internal contact part may be connected to the external contact part, but the present invention is not limited thereto, and the internal contact part and the external contact part may be spaced apart from each other.

In some embodiments, the mesa has a via hole that penetrates the second conductivity type semiconductor layer and the active layer to expose the first conductivity type semiconductor layer, and the first opening of the lower insulating layer is exposed to the via hole. A first conductive semiconductor layer is exposed, and the first pad metal layer may have an internal contact portion that contacts the first conductive semiconductor layer exposed to the via hole.

Furthermore, the first pad metal layer includes external contact parts that contact the first conductive semiconductor layer outside the mesa, and the external contact parts may be spaced apart from each other.

Meanwhile, the light emitting diode includes: a first bump pad connected to the first pad metal layer through a first opening of the upper insulating layer; and a second bump pad connected to the second pad metal layer through a second opening in the upper insulating layer. The first and second bump pads may be used as bonding pads when manufacturing a light emitting module by mounting a light emitting diode on a circuit board, etc.

Furthermore, the lower insulating layer may include a plurality of second openings, and the second bump pad may cover an upper portion of at least one second opening of the lower insulating layer.

The position and shape of the first bump pad may be variously modified as long as it is insulated from the second pad metal layer, and the location and shape of the second bump pad may be variously modified as long as it is insulated from the first pad metal layer. there is.

Meanwhile, the second pad metal layer may be surrounded by the first pad metal layer. Accordingly, a boundary area where the lower insulating layer is exposed may be formed between the first pad metal layer and the second pad metal layer. This border area may be covered by a top insulating layer.

In some embodiments, the second bump pad may be located limited to an upper region of the second pad metal layer, but this is not limited, and the second bump pad may partially overlap the first pad metal layer. It may be possible.

Meanwhile, the light emitting diode may further include a substrate located on the side of the first conductive semiconductor layer. The substrate transmits light generated in the active layer.

A light emitting diode according to another embodiment of the present invention includes a first conductivity type semiconductor layer; a mesa located on the first conductivity type semiconductor layer and including an active layer and a second conductivity type semiconductor layer; a transparent conductive oxide layer disposed on the mesa and electrically connected to the second conductive semiconductor layer; a dielectric layer that covers the conductive oxide layer, has a plurality of openings exposing the conductive oxide layer, and has a lower refractive index than the second conductive semiconductor layer and the conductive oxide layer; and a metal reflective layer disposed on the dielectric layer and connected to the conductive oxide layer through openings in the dielectric layer, wherein the dielectric layer has a lower refractive index than the conductive oxide layer and the second conductive semiconductor layer, and is 300 nm to 800 nm. It has a thickness within the range.

Additionally, the thickness of the dielectric layer may be in the range of 4 to 13 times the thickness of the second conductive semiconductor layer.

Meanwhile, the conductive oxide layer may be an indium tin oxide (ITO) layer, and the ITO layer may have a thickness in the range of 6 nm to 30 nm.

The light emitting diode includes: a substrate located on the side of the first conductive semiconductor layer; a first bump pad located on the metal reflective layer and electrically connected to the first conductive semiconductor layer; and a second bump pad located on top of the metal reflective layer and electrically connected to the metal reflective layer.

A light emitting diode according to another embodiment of the present invention includes a first conductivity type semiconductor layer; a mesa located on the first conductivity type semiconductor layer and including an active layer and a second conductivity type semiconductor layer; a transparent conductive oxide layer disposed on the mesa and electrically connected to the second conductive semiconductor layer; a dielectric layer covering the conductive oxide layer and having a plurality of openings exposing the conductive oxide layer; a metal reflective layer disposed on the dielectric layer and connected to the conductive oxide layer through openings in the dielectric layer; a lower insulating layer that covers the mesa and the metal reflective layer and includes at least one first opening exposing the first conductive semiconductor layer and a second opening exposing the metal reflective layer; a first pad metal layer disposed on the lower insulating layer and electrically connected to the first conductive semiconductor layer through the at least one first opening; a second pad metal layer disposed on the lower insulating layer and electrically connected to the metal reflection layer through the second opening; and an upper insulating layer covering the first pad metal layer and the second pad metal layer, the dielectric layer including a first opening exposing the first pad metal layer and a second opening exposing the second pad metal layer. The openings include a narrow, elongated bar-shaped opening adjacent to at least one of the first openings of the lower insulating layer.

By arranging the bar-shaped opening adjacent to the first opening of the lower insulating layer, the light emitting diode can be prevented from being damaged by electrical overload or electrostatic discharge.

The dielectric layer may include openings of other shapes in addition to the bar-shaped opening, and the bar-shaped opening may be disposed between the corresponding first opening of the lower insulating layer and the openings of other shapes of the dielectric layer. .

Furthermore, the first opening of the corresponding lower insulating layer may have an elongated shape in one direction, and the bar-shaped opening of the dielectric layer may be arranged parallel to the first opening of the corresponding lower insulating layer.

Meanwhile, the bar-shaped opening of the dielectric layer may be longer than the first opening of the corresponding lower insulating layer. Accordingly, it is possible to provide a light emitting diode that is more resistant to electrical overload or static discharge.

Meanwhile, the lower insulating layer may have a plurality of first openings exposing the first conductivity type semiconductor layer around the mesa, and the first pad metal layer may have a plurality of first conductivity type semiconductor layers in the plurality of first openings. It may have external contacts that contact the semiconductor layer.

In some embodiments, the dielectric layer may have a plurality of bar-shaped openings each adjacent to the plurality of first openings.

In other embodiments, the bar-shaped opening of the dielectric layer may be disposed long across the external contact portions.

The light emitting diode includes a first bump pad; and a second bump pad, wherein the first bump pad and the second bump pad are connected to the first pad metal layer and the second pad metal layer through the first opening and the second opening of the upper insulating layer, respectively. Electrically connected, at least a portion of the bar-shaped opening may be disposed below the first bump pad.

Additionally, a portion of the bar-shaped opening may be disposed below the second bump pad.

Meanwhile, the light emitting diode may further include a substrate located on a side of the first conductive semiconductor layer, and the substrate transmits light generated in the active layer.

Meanwhile, the first pad metal layer may have protrusions along one edge of the mesa M, and the first pad metal layer may have external contact portions that contact the first conductive semiconductor layer near the edge of the mesa. , the external contact portions are formed by the protrusions, and an area between the protrusions among the edges of the first pad metal layer may be located on the conductive oxide layer.

A light emitting diode according to another embodiment of the present invention includes a first conductivity type semiconductor layer; a mesa located on the first conductivity type semiconductor layer and including an active layer and a second conductivity type semiconductor layer; a transparent conductive oxide layer disposed on the mesa and electrically connected to the second conductive semiconductor layer; a dielectric layer covering the conductive oxide layer and having a plurality of openings exposing the conductive oxide layer; a metal reflective layer disposed on the dielectric layer and connected to the conductive oxide layer through openings in the dielectric layer; a lower insulating layer that covers the mesa and the metal reflective layer and includes at least one first opening exposing the first conductive semiconductor layer and a second opening exposing the metal reflective layer; a first pad metal layer disposed on the lower insulating layer and electrically connected to the first conductive semiconductor layer through the at least one first opening; a second pad metal layer disposed on the lower insulating layer and electrically connected to the metal reflection layer through the second opening; and an upper insulating layer covering the first pad metal layer and the second pad metal layer, the dielectric layer including a first opening exposing the first pad metal layer and a second opening exposing the second pad metal layer. The openings include openings having different sizes, wherein at least one of the openings in the dielectric layer adjacent to the first opening in the upper insulating layer is at least one of the openings in the dielectric layer disposed farther from the first opening in the upper insulating layer. It has a width or length greater than one opening.

A light emitting diode that has strong resistance to electrical overload or electrostatic discharge by making the first opening of the upper insulating layer, that is, the opening of the dielectric layer adjacent to the area where the first pad metal layer contacts the first conductive semiconductor layer, larger than the opening of the other dielectric layers. can be provided.

In some embodiments, the opening of the dielectric layer having the greater width or length may have a bar shape. In other embodiments, the opening of the dielectric layer may have a circular or ring shape.

The light emitting diode includes a first bump pad; and a second bump pad, wherein the first bump pad and the second bump pad are connected to the first pad metal layer and the second pad metal layer through the first opening and the second opening of the upper insulating layer, respectively. At least a portion of the opening of the dielectric layer that is electrically connectable and has the greater width or length may be disposed below the first bump pad.

In one embodiment, at least one opening of the dielectric layer having the greater width or length may extend from a lower portion of the first bump pad to a lower portion of the second bump pad.

In some embodiments, the mesa may have a via hole exposing the first conductivity type semiconductor layer, and the first openings of the lower insulating layer expose the first conductivity type semiconductor layer within the via hole. The first pad metal layer includes an internal contact portion contacting the first conductive semiconductor layer within the via hole, and the opening of the dielectric layer having the greater width or length is adjacent to the via hole. can be placed.

Furthermore, the opening of the dielectric layer disposed adjacent to the via hole may surround the via hole.

Meanwhile, the first pad metal layer may include external contact parts contacting the first conductive semiconductor layer outside the mesa, the external contact parts are spaced apart from each other, and an opening of the dielectric layer having the larger width or length is formed. They may be disposed adjacent to each of the external contact parts.

Meanwhile, the dielectric layer has a lower refractive index than the second conductive semiconductor layer and the conductive oxide layer, and may have a thickness in the range of 300 nm to 800 nm. Additionally, the conductive oxide layer may have a thickness ranging from 3 nm to 50 nm.

In addition, the light emitting diode may further include a substrate located on a side of the first conductive semiconductor layer, and the substrate transmits light generated in the active layer.

A light emitting diode according to another embodiment of the present invention includes a first conductivity type semiconductor layer; a mesa located on the first conductivity type semiconductor layer and including an active layer and a second conductivity type semiconductor layer; a transparent conductive oxide layer disposed on the mesa and electrically connected to the second conductive semiconductor layer; a dielectric layer covering the conductive oxide layer and having a plurality of openings exposing the conductive oxide layer; a metal reflective layer disposed on the dielectric layer and connected to the conductive oxide layer through openings in the dielectric layer; a lower insulating layer that covers the mesa and the metal reflective layer and includes at least one first opening exposing the first conductive semiconductor layer and a second opening exposing the metal reflective layer; a first pad metal layer disposed on the lower insulating layer and electrically connected to the first conductive semiconductor layer through the at least one first opening; a second pad metal layer disposed on the lower insulating layer and electrically connected to the metal reflection layer through the second opening; and an upper insulating layer covering the first pad metal layer and the second pad metal layer, the dielectric layer including a first opening exposing the first pad metal layer and a second opening exposing the second pad metal layer. The openings include openings located below the first opening of the upper insulating layer, and from the first opening among the openings located below the first opening of the upper insulating layer and adjacent to the first opening of the lower insulating layer. The separation distance of the openings spaced apart in the vertical direction is longer than the separation distance of the openings of the dielectric layer closest to the first opening.

By adjusting the distance between the contact portion where the first pad metal layer contacts the first conductivity type semiconductor layer and the opening portion of the dielectric layer adjacent thereto, a light emitting diode with improved resistance to electrical overload or electrostatic discharge can be provided.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a schematic plan view for explaining a light emitting diode according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line A-A of FIG. 1.

1 and 2, the light emitting diode includes a substrate 21, a first conductive semiconductor layer 23, an active layer 25, a second conductive semiconductor layer 27, a conductive oxide layer 28, It includes a dielectric layer 29, a metal reflection layer 31, a lower insulating layer 33, a first pad metal layer 35a, a second pad metal layer 35b), and an upper insulating layer 37. Furthermore, the light emitting diode may further include a first bump pad 39a and a second bump pad 39b.

The substrate 21 is not particularly limited as long as it is a substrate capable of growing a gallium nitride-based semiconductor layer. Examples of the substrate 21 may be various, such as a sapphire substrate, a gallium nitride substrate, or a SiC substrate, and may be a patterned sapphire substrate. The substrate 21 may have a rectangular or square outer shape as shown in plan view (a), but is not necessarily limited thereto. The size of the substrate 21 is not particularly limited and can be selected in various ways.

The first conductive semiconductor layer 23 is disposed on the substrate 21. The first conductive semiconductor layer 23 is a layer grown on the substrate 21 and may be a gallium nitride-based semiconductor layer. The first conductive semiconductor layer 23 may be a gallium nitride-based semiconductor layer doped with an impurity, for example, Si.

In this embodiment, the edge of the first conductive semiconductor layer 23 is parallel to the edge of the substrate 21. However, the present invention is not limited to this, and the first conductive semiconductor layer 23 may be located inside the area surrounded by the edge of the substrate 21. In this case, a portion of the upper surface of the substrate 21 may be exposed along the perimeter of the first conductivity type semiconductor layer 23.

A mesa (M) is disposed on the first conductive semiconductor layer 23. The mesa (M) may be located limited to the inside of the area surrounded by the first conductivity type semiconductor layer 23, and therefore, areas near the edge of the first conductivity type semiconductor layer 23 are not covered by the mesa (M). exposed to the outside.

The mesa (M) includes a second conductive semiconductor layer 27 and an active layer 25. The active layer 25 is interposed between the first conductive semiconductor layer 23 and the second conductive semiconductor layer 27. The active layer 25 may have a single quantum well structure or a multiple quantum well structure. The composition and thickness of the well layer within the active layer 25 determines the wavelength of the light generated. In particular, by adjusting the composition of the well layer, an active layer that generates ultraviolet rays, blue light, or green light can be provided.

Meanwhile, the second conductive semiconductor layer 27 may be a gallium nitride-based semiconductor layer doped with a p-type impurity, for example, Mg. The concentration of p-type impurities in the second conductivity type semiconductor layer 27 affects the refractive index of the second conductivity type semiconductor layer 27. The concentration of p-type impurities in the second conductive semiconductor layer 27 may range from 8x10 ^-18 to 4x10 ^-21 /cm ³ . If the impurity concentration is lower than 8x10 ^-18 /cm ³ , the effect of increasing the refractive index cannot be obtained, and if it is higher than 4x10 ^-21 /cm ³ , it is difficult to form a stable ohmic.

In particular, the p-type impurity concentration in the second conductive semiconductor layer 27 does not have a constant value, but may have a concentration profile that varies along the thickness within the above range. In particular, the second conductive semiconductor layer 27 may have a higher impurity concentration on the side closer to the conductive oxide layer 28 so as to have a higher refractive index on the surface.

Accordingly, the refractive index of the second conductive semiconductor layer 27 can be increased to increase the gap with the refractive index of the conductive oxide layer 28, and the gap between the second conductive semiconductor layer 27 and the conductive oxide layer 28 can be increased. It is effective in light extraction by making the refractive index difference between and the refractive index difference between the conductive oxide layer 28 and the dielectric layer 29 more similar.

FIG. 3 illustrates a concentration profile within the second conductivity type semiconductor layer 27. As shown in FIG. 3, the concentration of p-type impurities, such as Mg, within the second conductivity type semiconductor layer 27 has sections with different slopes. It can be included. It may have a profile where the concentration decreases on the side close to the active layer 25 and then increases as it gets closer to the conductive oxide layer 28. In particular, the concentration increases rapidly as it gets closer to the conductive oxide layer 28, thereby increasing the concentration of the active layer 28. It may have a slope that is larger than the absolute value of the concentration decrease slope on the side close to . Accordingly, the portion where the refractive index rapidly increases comes into contact with the conductive oxide layer 28, thereby maximizing the light extraction effect.

Meanwhile, the first conductivity type semiconductor layer 23 and the second conductivity type semiconductor layer 27 may each be a single layer, but are not limited thereto, and may be a multilayer, or may include a superlattice layer. The first conductive semiconductor layer 23, the active layer 25, and the second conductive semiconductor layer 27 are formed in a chamber using a known method such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). It can be formed by growing on the substrate 21 within.

Meanwhile, as shown in FIG. 1, a recessed portion 30 penetrating inside may be formed in the mesa M, and the upper surface of the first conductivity type semiconductor layer 23 is formed by the indented portion 30. This may be exposed. The indentation 30 may be formed long inside the mesa (M) from one edge of the mesa (M) toward the other edge opposite to it. The length of the indented portion 30 is not particularly limited and may be 1/2 the length of the mesa (M) or longer. In addition, although two indentations 30 are shown in FIG. 1, the number of indentations 30 may be one or three or more. As the number of indented portions 30 increases, the number of internal contact portions 35a2 of the first pad metal layer 35a, which will be described later, increases, thereby improving current dispersion performance.

Meanwhile, the indented portion 30 has a round shape with a wider width at the end. By shaping the end of the indented portion 30 in this way, the lower insulating layer 33 can be patterned into a similar shape. In particular, when the lower insulating layer 33 includes a distributed Bragg reflector, if the width is not widened at the end as shown in Figure 1, a severe double step is formed on the side wall of the distributed Bragg reflector, and the inclination angle of the side wall increases, so that the first It is easy for cracks to occur in the pad metal layer 35a. Therefore, the shape of the end of the indentation 30 and the shape of the end of the first opening 33a2 of the lower insulating layer 33 are similar to those of the present embodiment so that the edge of the lower insulating layer 33 has a gentle inclination angle. It is possible to improve the yield of light emitting diodes.

In this embodiment, it is shown and explained that the indentation 30 is formed in the mesa (M), but the mesa (M) includes the second conductivity type semiconductor layer 27 and the active layer 25 instead of the indentation 30. It may have at least one via hole penetrating.

Meanwhile, the conductive oxide layer 28 is disposed on the mesa (M) and contacts the second conductive semiconductor layer 27. The conductive oxide layer 28 may be disposed over almost the entire area of the mesa (M) in the upper area of the mesa (M). For example, the conductive oxide layer 28 may cover more than 80%, and even more than 90%, of the upper area of the mesa (M).

The conductive oxide layer 28 is formed of an oxide layer that transmits light generated in the active layer 25. The conductive oxide layer 28 may be formed of, for example, ITO (indium tin oxide) or ZnO. The conductive oxide layer 28 is formed to a thickness sufficient to make ohmic contact with the second conductive semiconductor layer 27, for example, within a thickness range of 3 nm to 50 nm, specifically, within a thickness range of 6 nm to 30 nm. can be formed. If the thickness of the conductive oxide layer 28 is too thin, it does not provide sufficient ohmic properties and the forward voltage increases. Additionally, if the thickness of the conductive oxide layer 28 is too thick, loss due to light absorption occurs, reducing luminous efficiency.

Meanwhile, the dielectric layer 29 covers the conductive oxide layer 28 and may further cover the side surfaces of the second conductive semiconductor layer 27, the active layer 25, and the first conductive semiconductor layer 23. The edge of the dielectric layer 29 may be covered with the lower insulating layer 33. Accordingly, the edge of the dielectric layer 29 is located farther from the edge of the substrate 21 than the edge of the lower insulating layer 33. However, the present invention is not limited to this, and a portion of the dielectric layer 29 may be exposed to the outside of the lower insulating layer 33.

The dielectric layer 29 has openings 29a exposing the conductive oxide layer 28. A plurality of openings 29a may be disposed on the conductive oxide layer 28. The openings 29a are used as connection passages so that the metal reflection layer 31 can be connected to the conductive oxide layer 28. The dielectric layer 29 also exposes the first conductivity type semiconductor layer 23 around the mesa M and exposes the first conductivity type semiconductor layer 23 within the indentation 30 .

The dielectric layer 29 is formed of an insulating material having a lower refractive index than the second conductive semiconductor layer 27 and the conductive oxide layer 28. The dielectric layer 29 may be formed of, for example, SiO ₂ .

The thickness of dielectric layer 29 affects the forward voltage and light output of the light emitting diode. The thickness of the dielectric layer 29 may range from 200 nm to 1000 nm, and specifically may range from 300 nm to 800 nm. If the thickness of the dielectric layer 29 is less than 200 nm, the forward voltage is high and the light output is low, which is not good. Meanwhile, when the thickness of the dielectric layer 29 exceeds 400 nm, the light output is saturated and the forward voltage tends to increase again. Therefore, it is advantageous that the thickness of the dielectric layer 29 does not exceed 1000 nm, and in particular may be 800 nm or less. Moreover, the thickness of the dielectric layer 29 may be 4 times or more and 13 times or less the thickness of the second conductivity type semiconductor layer 27 on the active layer 25.

Meanwhile, the metal reflective layer 31 is disposed on the dielectric layer 29 and connected to the ohmic contact layer 28 through the openings 29a. The metal reflective layer 31 includes a reflective metal, for example, Ag or Ni/Ag. Furthermore, the metal reflective layer 32 may include a barrier layer, such as Ni, to protect the reflective metal material layer, and may also include an Au layer to prevent oxidation of the metal layer. Furthermore, in order to improve the adhesion of the Au layer, a Ti layer may be included below the Au layer. The metal reflective layer 31 is in contact with the upper surface of the dielectric layer 29, and therefore, the thickness of the dielectric layer 29 is equal to the separation distance between the conductive oxide layer 28 and the metal reflective layer 31.

By forming an ohmic contact with the conductive oxide layer 28 and disposing the metal reflection layer 31 on the dielectric layer 29, it is possible to prevent the ohmic resistance from increasing due to solder, etc. Furthermore, by disposing the conductive oxide layer 28, the dielectric layer 29, and the metal reflection layer 31 on the second conductive semiconductor layer 27, the reflectance of light can be improved, thereby improving luminous efficiency.

The lower insulating layer 33 covers the mesa (M) and the metal reflection layer 31. The lower insulating layer 33 may also cover the first conductivity type semiconductor layer 23 along the perimeter of the mesa (M), and the first conductivity type semiconductor layer (23) within the indentation 30 inside the mesa (M). ) can be covered. The lower insulating layer 33 covers in particular the sides of the mesa (M). Bottom insulating layer 33 may also cover dielectric layer 29.

Meanwhile, the lower insulating layer 33 has first openings 33a1 and 33a2 exposing the first conductive semiconductor layer and a second opening 33b exposing the metal reflection layer 31. The first opening 33a1 exposes the first conductive semiconductor layer 23 along the perimeter of the mesa (M), and the first opening 33a2 exposes the first conductive semiconductor layer 23 within the indentation 30. ) is exposed. When a via hole is formed instead of the indented portion 30, the first opening 33a2 exposes the first conductivity type semiconductor layer 23 within the via hole.

As shown in FIG. 1, the first opening 33a1 and the first opening 33a2 may be connected to each other. However, the present invention is not limited to this, and the first openings 33a1 and 33a2 may be spaced apart from each other.

In this embodiment, the first opening 33a1 of the lower insulating layer 33 is formed to expose the entire surrounding area, including the edge of the first conductivity type semiconductor layer 23. However, the present invention is not limited to this, and the first opening 33a1 of the lower insulating layer 33 may be formed in a strip shape along the perimeter of the mesa M. In this case, the edge of the first conductive semiconductor layer 23 may be covered with the lower insulating layer 33 or may be parallel to the edge of the lower insulating layer 33.

The second opening 33b exposes the metal reflective layer 31. A plurality of second openings 33b may be formed, and these second openings 33b may be disposed near one edge of the substrate 21 opposite the indentation 30 . The positions of the second openings 33b will be described again later.

Meanwhile, the lower insulating layer 33 may be formed as a single layer of SiO ₂ or Si ₃ N ₄ , but is not limited thereto. For example, the lower insulating layer 33 may have a multilayer structure including a silicon nitride film and a silicon oxide film, and may also include a distributed Bragg reflector in which silicon oxide films and titanium oxide films are alternately stacked.

Meanwhile, the first pad metal layer 35a is disposed on the lower insulating layer 33 and is insulated from the mesa (M) and the metal reflection layer 31 by the lower insulating layer 33. The first pad metal layer 35a contacts the first conductive semiconductor layer 23 through the first openings 33a1 and 33a2 of the lower insulating layer 33. The first pad metal layer 35a has an external contact portion 35a1 in contact with the first conductive semiconductor layer 23 along the circumference of the mesa (M) and a first conductive semiconductor layer ( 23) may include an internal contact portion 35a2 that contacts the surface. The external contact portion 35a1 contacts the first conductive semiconductor layer 23 near the edge of the substrate 21 along the circumference of the mesa M, and the internal contact portion 35a2 is inside the area surrounded by the external contact portion 35a1. Contacts the first conductive semiconductor layer 23. The external contact part 35a1 and the internal contact part 35a2 may be connected to each other, but are not limited to this and may be spaced apart from each other. In addition, the external contact portion 35a1 may continuously contact the first conductive semiconductor layer 23 along the circumference of the mesa M, but is not limited thereto, and the plurality of external contact portions 35a1 may be spaced apart from each other. It may be deployed.

Meanwhile, the second pad metal layer 35b is disposed in the upper area of the mesa (M) on the lower insulating layer 33, and is electrically connected to the metal reflection layer 31 through the second opening 33b of the lower insulating layer 33. Connected. The second pad metal layer 35b may be surrounded by the first pad metal layer 35a, and a boundary area 35ab may be formed between them. The lower insulating layer 33 is exposed in the boundary area 35ab, and this boundary area 35ab is covered with the upper insulating layer 37, which will be described later.

The first pad metal layer 35a and the second pad metal layer 35b may be formed together with the same material in the same process. The first and second pad metal layers 35a and 35b may include an ohmic reflective layer such as an Al layer, and the ohmic reflective layer may be formed on an adhesive layer such as Ti, Cr, or Ni. Additionally, a protective layer having a single or multiple layer structure of Ni, Cr, Au, etc. may be formed on the ohmic reflection layer. The first and second pad metal layers 35a and 35b may have a multilayer structure of, for example, Cr/Al/Ni/Ti/Ni/Ti/Au/Ti.

The upper insulating layer 37 covers the first and second pad metal layers 35a and 35b. Additionally, the upper insulating layer 37 may cover the first conductive semiconductor layer 23 along the perimeter of the mesa (M). In this embodiment, the upper insulating layer 37 may expose the first conductive semiconductor layer 23 along the edge of the substrate 21. However, the present invention is not limited to this, and the upper insulating layer 37 may cover the entire first conductive semiconductor layer 23 and may be parallel to the edge of the substrate 21.

Meanwhile, the upper insulating layer 37 has a first opening 37a exposing the first pad metal layer 35a and a second opening 37b exposing the second pad metal layer 35b. The first opening 37a and the second opening 37b may be disposed in the upper area of the mesa (M) and may be disposed to face each other. In particular, the first opening 37a and the second opening 37b may be disposed close to both edges of the mesa M.

The upper insulating layer 37 may be formed as a single layer of SiO ₂ or Si ₃ N ₄ , but is not limited thereto. For example, the upper insulating layer 37 may have a multilayer structure including a silicon nitride film and a silicon oxide film, and may also include a distributed Bragg reflector in which silicon oxide films and titanium oxide films are alternately stacked.

Meanwhile, the first bump pad 39a is in electrical contact with the first pad metal layer 35a exposed through the first opening 37a of the upper insulating layer 37, and the second bump pad 39b is in electrical contact with the second pad metal layer 35a. It electrically contacts the second pad metal layer 35b exposed through the opening 37b. As shown in FIG. 1, the first bump pad 39a is disposed within the first opening 37a of the upper insulating layer 37, and the second bump pad 39b is disposed within the second opening 37a of the upper insulating layer 37. It may be placed within the opening 37b. However, the present invention is not limited to this, and the first bump pad 39a and the second bump pad 39b may cover and seal the first opening 37a and the second opening 37b, respectively. Additionally, the second bump pad 39b may cover the upper area of the second opening 33b of the lower insulating layer 33. The second bump pad 39b may cover all of the second openings 33b of the lower insulating layer 33, but is not limited thereto, and some of the openings 33b may cover the outside of the second bump pad 39b. It may be located in .

Additionally, as shown in FIG. 1, the second bump pad 39b may be located limited to the upper region of the second pad metal layer 35a. However, the present invention is not limited to this, and a portion of the second bump pad 39b may overlap the first pad metal layer 35a. However, the upper insulating layer 37 may be disposed between the first pad metal layer 35a and the second bump pad 39b to insulate them.

According to an embodiment of the present invention, a reflective structure of a conductive oxide layer 28, a dielectric layer 29, and a metal reflective layer 31 is used instead of the conventional ohmic reflective layer. Accordingly, penetration of bonding materials such as solder into the contact area can be prevented, and stable ohmic contact resistance can be secured to improve the reliability of the light emitting diode. Moreover, by setting the thickness of the dielectric layer 29 to 300 nm or more, high light output and low forward voltage can be achieved.

FIGS. 4A and 4B are graphs showing the forward voltage (Vf) and light output (Po) according to the thickness of SiO ₂ when the conductive oxide layer 28 is made of ITO and the dielectric layer 29 is made of SiO ₂ .

The ITO thickness was set to 20 nm, and SiO2 was changed to 200 nm, 400 nm, 600 nm, and 800 nm. The thickness of the second conductive semiconductor layer 27 was about 65 nm.

As shown in FIG. 4A, when the thickness of the dielectric layer 29 was 200 nm, the forward voltage was relatively high, and the lowest value was at 400 nm. Additionally, the forward voltage tended to increase as the thickness increased beyond 400 nm.

Meanwhile, as shown in FIG. 4B, the lowest light output was shown when the thickness of the dielectric layer 29 was 200 nm, and generally similar light output was shown at 400 nm or more.

FIG. 5 is a schematic plan view for explaining a light emitting diode according to another embodiment of the present invention, and FIG. 6 is a schematic cross-sectional view taken along the cutting line B-B of FIG. 5.

Referring to FIGS. 5 and 6, the light emitting diode according to this embodiment is generally similar to the light emitting diode described with reference to FIGS. 1 and 2, so to avoid duplication of description, the following mainly describes the characteristic differences. .

First, in the previous embodiment, the edge of the first conductive semiconductor layer 23 is parallel to the edge of the substrate 21, but in this embodiment, the edge of the first conductive semiconductor layer 23 is parallel to the edge of the substrate 21. It is placed within the area surrounded by the edges of . Accordingly, the area near the edge of the substrate 21 is exposed to the outside of the first conductivity type semiconductor layer 23.

Additionally, in this embodiment, the positions of the openings 29a of the dielectric layer 29 are controlled, which will be described in detail later.

Meanwhile, in the previous embodiment, the edge of the lower insulating layer 33 is located on the first conductivity type semiconductor layer 23, but in this embodiment, the lower insulating layer 33 is located on the first conductivity type semiconductor layer ( It covers the edge of 23) and is parallel to the edge of the substrate 21. The first opening 33a1 of the lower insulating layer 33 is located limited on the first conductive semiconductor layer 23 and is arranged in a ring shape along the periphery of the mesa M.

Furthermore, the second opening 33b of the lower insulating layer 33 is formed outside the second bump pad 39b so as not to overlap the second bump pad 39b. By arranging the second opening 33b to be spaced apart from the second bump pad 39b in the horizontal direction, it is possible to prevent solder from spreading into the light emitting diode when soldering the second bump pad 39b.

The first pad metal layer 35a covers the first opening 33a1 of the lower insulating layer 33 and contacts the first conductive semiconductor layer 23, and accordingly, an external contact part ( 35a1) is formed. The external contact part 35a1 may be connected to the internal contact part 35a2 or may be spaced apart from the internal contact part 35a2, as described in the previous embodiment.

Meanwhile, in this embodiment, the shape of the second pad metal layer 35 is different compared to the embodiment of FIG. 1, and accordingly, there is a gap between the second pad metal layer 35b and the first pad metal layer 35a. The location of the border area 35ab is also different from the embodiment of FIG. 1. As shown in FIG. 5, the second pad metal layer 35b extends to the area between the inner contact portion 35a2 and the outer contact portion 35a1. When a plurality of internal contact portions 35a2 are disposed, the tip of the second pad metal layer 35b may have a convex-convex shape, as shown. The first pad metal layer 35a may be spaced apart from the second pad metal layer 35b at a regular interval, and therefore, the first pad metal layer 35a adjacent to the tip of the second pad metal layer 35b also has a concave-convex shape.

By extending the tip of the second pad metal layer 35b near the internal contact portions 35a2, the second openings 33b of the lower insulating layer 33 can be easily spaced apart from the second bump pad 39b in the horizontal direction. there is.

Meanwhile, the upper insulating layer 37 covers the lower insulating layer 33, and the edges of the upper insulating layer 37 may be formed parallel to the edges of the substrate 21 and the lower insulating layer 33. Furthermore, in the previous embodiment, the first and second bump pads 39a, 39b are shown and described as being arranged to be defined within the first and second openings 37a, 37b of the upper insulating layer 37. However, in this embodiment, the first and second bump pads 39a and 39b cover and seal the first and second openings 37a and 37b of the upper insulating layer 37. That is, the edges of the first and second bump pads 39a and 39b are located on the upper surface of the upper insulating layer 37. Accordingly, the first pad metal layer 35a and the second pad metal layer 35b can be prevented from being exposed between the upper insulating layer 37 and the bump pads 39a and 39b, and accordingly, the solder is Direct diffusion into the first and second pad metal layers 35a and 35b can be prevented.

In this embodiment, the edge positions of the first conductive semiconductor layer 23, the lower insulating layer 33, the upper insulating layer 37, and the bump pads 39a and 39b are explained as being different from the embodiment of FIG. 1. However, this is for explaining an embodiment that can be modified to the embodiment of FIG. 1, and the present embodiment is not limited to what is described here. That is, in this embodiment, the edge positions of the first conductive semiconductor layer 23, the lower insulating layer 33, and the upper insulating layer 37 may be the same as those in the embodiment of FIG. 1. The embodiment may be modified as in this embodiment.

Meanwhile, in this embodiment, the positions of the openings 29a of the dielectric layer 29 are adjusted to enhance resistance to electrical overload or electrostatic discharge. The reflective structure of the conductive oxide layer 28, the dielectric layer 29, and the metal reflective layer 31 improves reflectivity, but the conductive oxide layer 28 and the metal reflective layer 31 must be electrically connected. The openings 29a of the dielectric layer 29 provide a passage through which the metal reflective layer 31 is electrically connected to the conductive oxide layer 28. In addition, a plurality of openings 29a are widely distributed on the conductive oxide layer 28 in order to evenly distribute the current over a wide area of the conductive oxide layer 28. However, the distance between the openings 29a and the external contact part 35a1 and the internal contact part 35a2 that the first pad metal layer 35a is in contact with may affect the characteristics of the light emitting diode with respect to electrical overload or electrostatic discharge.

As a countermeasure to this, in this embodiment, as shown in FIG. 5, a dielectric layer located below the first opening 37a area of the upper insulating layer 37 (or below the first bump pad 39a) Among the openings 29a of 29), the openings 29a located closest to the external contact part 35a1 and the internal contact part 35a2 are relatively spaced apart.

That is, in FIG. 5, the shortest distance Dv1 between the external contact part 35a1 and the opening 29a located below the first opening 37a of the upper insulating layer 37 is the distance between the external contact part 35a1 and the upper insulating layer ( It is larger than the shortest distance Ds between the openings 29a located outside the first opening 37a of 37). Although the drawing shows the distance between the external contact part 35a1 and the opening 29a, the same applies to the distance between the internal contact part 35a2 and the opening 29a.

The distance between the opening 29a of the dielectric layer 29 located below the first bump pad 39a electrically connected to the first conductive semiconductor layer 23 and the contact portions 35a1 and 35a2 is determined by electrical overload or electrostatic discharge. It is greatly affected by discharge. Accordingly, the reliability of the light emitting diode can be improved by spacing the openings 29a of the dielectric layer 29 located below the first bump pad 39a away from the contact portions 35a1 and 35a2.

Meanwhile, not only the bottom of the first bump pad 39a, but also the bottom of the second bump pad 39b and other openings 29a can be spaced away from the contact portions 35a1 and 35a2, but do not disperse the current widely. Otherwise, luminous efficiency may decrease. Therefore, in this embodiment, only the openings 29a located below the first bump pad 39a are placed relatively farther away than the other openings, thereby improving electrostatic discharge characteristics without deteriorating current dispersion performance.

Figure 7 is a schematic plan view for explaining a light emitting diode according to another embodiment of the present invention.

Referring to FIG. 7, the light emitting diode according to this embodiment is generally similar to the light emitting diode described with reference to FIGS. 5 and 6, but the openings of the dielectric layer 29 have a plurality of openings 29a and an elongated opening. There is a difference in including (29b).

When the opening 29b is located between the outer contact portion 35a1 and the inner contact portion 35a2 and the openings 29a, it forms a closed loop along the outer contact portion 35a1 and the inner contact portion 35a2. Since the openings 29b adjacent to the external contact part 35a1 and the internal contact part 35a2 are long and adjacent to each other along the contact parts 35a1 and 35a2, it is possible to prevent a large voltage difference from occurring at a specific point, and thus, electric A light emitting diode with strong resistance to overload or electrostatic discharge can be provided.

In this embodiment, the openings 29b are shown and described as forming a closed loop, but the openings 29b having a length longer than the width may be arranged along the contact portions 35a1 and 35a2.

Meanwhile, in this embodiment, the opening 29b is not limited to the lower part of the first bump pad 39a and is described as extending to the outside of the first bump pad 39a, but is limited to the lower part of the first bump pad 39a. It may be arranged as much as possible.

Figure 8 is a schematic plan view for explaining a light emitting diode according to another embodiment of the present invention.

Referring to FIG. 8, the light emitting diode according to this embodiment is generally similar to the light emitting diode described with reference to FIG. 7, but the difference is that the openings of the dielectric layer 29 further include an opening 29c.

The opening 29c is disposed within the area surrounded by the opening 29b, and in particular, may be located outside the lower area of the second bump pad 39b. A portion of the opening 29c may also be located below the first bump pad 39b.

Figure 9 is a schematic plan view for explaining a light emitting diode according to another embodiment of the present invention.

Referring to FIG. 9, the light emitting diode according to this embodiment is generally similar to the light emitting diode described with reference to FIG. 5, but the mesa (M) has an elongated shape in the uniaxial direction and has no internal contacts 35a2 and external contacts. The difference is that (35a1) is formed near one edge of the mesa, and the first pad metal layer 35a is formed so as not to surround the second pad metal layer 35b.

The mesa (M) has an elongated shape in the uniaxial direction. For example, its length may be 4 times or more and 7 times or less the width. By forming the mesa M into an elongated shape in the uniaxial direction, the area where the first pad metal layer 35a contacts the first conductivity type semiconductor layer 23 can be relatively reduced, thereby securing the light emitting area.

Meanwhile, one edge of the mesa M may be formed to have recesses or protrusions.

The dielectric layer 29 covers the conductive oxide layer 28 and covers the side of the mesa (M). A portion of the dielectric layer 29 partially covers the first conductive semiconductor layer 23 exposed around the mesa M, as described with reference to FIG. 5 .

Meanwhile, the dielectric layer 29 has a plurality of openings 29a that expose the conductive oxide layer 28, and the positions of the openings 29a are adjusted to improve resistance to electrical overload and electrostatic discharge. This will be explained again later.

The metal reflective layer 31 is disposed on the dielectric layer 29 and connects to the conductive oxide layer 28 through the openings 29a of the dielectric layer 29a.

In this embodiment, the conductive oxide layer 28 and the metal reflective layer 31 cover most of the upper surface of the mesa (M). However, the edges of the conductive oxide layer 28 and the metal reflective layer 31 are spaced apart from the edge of the mesa (M), and in particular, are spaced further apart from one edge of the mesa (M) adjacent to the external contact portions (35a1). In particular, by moving the edge of the conductive oxide layer 28 further away from the external contact portions 35a1, device defects due to electrical overload or electrostatic discharge can be prevented.

The lower insulating layer 33 covers the dielectric layer 29 and the metal reflection layer 31, and may cover a portion of the first conductive semiconductor layer 23 exposed around the mesa (M). The lower insulating layer 33 exposes the first conductivity type semiconductor layer 23 in the recess areas of the mesa (M). Additionally, the lower insulating layer 33 may cover the first conductive semiconductor layer 23, but may also be formed to expose near the edge of the first conductive semiconductor layer 23, as shown. The lower insulating layer 33 also has a second opening 33b exposing the metal reflective layer 31.

Meanwhile, in this embodiment, the first pad metal layer 35a is disposed on the upper part of the mesa M except for the area where the external contact portions 35a1 are formed. In the embodiment of FIG. 5, the first pad metal layer 35a covers not only the upper area of the mesa (M) but also the side surface, and covers a portion of the first conductivity type semiconductor layer 23 around the mesa (M). . Additionally, the edge of the first pad metal layer 35a may be located on the mesa M in the area between the recesses of the mesa M.

Additionally, the first pad metal layer 35a may include a wide area biased toward one side of the mesa M and a narrow area extending from the area. The external contact portions 35a1 are formed along one edge of the mesa M, and may be formed within recesses formed at one edge of the mesa M. The external contact portions 35a1 may be formed to have an elongated shape along the longitudinal direction of the mesa (M). Additionally, as shown, the external contact portions 35a1 may be formed by a wide region and a narrow region of the first pad metal layer 35a.

The first pad metal layer 35a may have protrusions along one edge of the mesa M, and these protrusions may form external contact portions 35a1. Additionally, the area between the protrusions at the edge of the first pad metal layer 35a may be located on the mesa (M) and further on the conductive oxide layer 28.

Meanwhile, the second pad metal layer 35b may be disposed in the upper area of the mesa (M). The second pad metal layer 35b may be formed long along a narrow area of the first pad metal layer 35a. The second pad metal layer 35b may be electrically connected to the metal reflection layer 31 through the second openings 33b of the lower insulating layer 33. The second openings 33b of the lower insulating layer 33 may be disposed below the second bump pad 39b, but as shown, may be disposed to be spaced apart from the second bump pad 39b in the horizontal direction. there is.

In this embodiment, the openings 29a of the dielectric layer 29 are arranged spaced apart from the edge of the mesa M, in particular further away from the edge of the mesa M adjacent to the external contacts 35a1. In particular, in the openings 29a located below the first bump pad 39a, the separation distance Dv1 of the openings 29a closest to one external contact portion 35a1 in the vertical direction is the outer contact portion 35a1. It is larger than the separation distance Ds of the opening 29a closest to the contact portion 35a1. Furthermore, the opening 29a spaced closest to the external contact portion 35a1 is disposed farther from the edge of the mesa M than the opening closest to the edge of the mesa M.

The positions of the openings 29a located below the first bump pad 39a as well as the openings 29a located below the second bump pad 39a may be adjusted in position, and the positions of the first bump pad 39a and The positions of the openings 29a located below the second bump pad 39b may also be adjusted. That is, as shown in FIG. 9, the separation distance Dv2 of the opening 29a spaced apart from the external contact part 35a1 in the vertical direction is the distance of the opening 29a closest to the external contact part 35a1. It can be greater than (Ds). The openings 29a disposed below the second bump pad 39b may also be disposed in the same manner as shown.

Figure 10 is a schematic plan view for explaining a light emitting diode according to another embodiment of the present invention.

Referring to FIG. 10, the light emitting diode according to this embodiment is generally similar to the light emitting diode described with reference to FIG. 9, but the difference is that the dielectric layer 29 has openings 29a and 129a of different sizes.

In this embodiment, the relatively large openings 129a are disposed closer to the external contacts 35a1 than the small openings 29a. In particular, in the lower area of the first bump pad 39a, the openings 129a are disposed closer to the external contact portion 35a1 than the openings 29a. Furthermore, the openings 129a may be disposed closer to the external contact portions 35a1 than the openings 29a in the lower region of the second bump pad 39b and other regions.

The relatively large openings 129a prevent current from concentrating at a specific point and improve the resistance of the light emitting diode to electrical overload or electrostatic discharge.

In this embodiment, the openings 129a are shown as circular, but their shape may vary. In particular, the openings 129a may have an elongated shape along the longitudinal direction of the mesa M, for example, an oval shape or a bar shape.

Figure 11 is a schematic plan view for explaining a light emitting diode according to another embodiment of the present invention.

Referring to FIG. 11, the light emitting diode according to this embodiment is generally similar to the light emitting diode described with reference to FIG. 10, except that the bar-shaped openings 129b are disposed adjacent to the external contact portions 35a1. There is a difference.

In particular, a bar-shaped opening 129b may be disposed under the first bump pad 39a, and further, bar-shaped openings 129b may be disposed under the second bump pad 39b and other areas. The bar-shaped openings 129b may be arranged parallel to the first opening 33a of the lower insulating layer 33 or the external contact portions 35a1.

The opening 129b is disposed between the external contact part 35a1 and the openings 29a, and prevents current from concentrating on a specific point, thereby improving the resistance of the light emitting diode to electrical overload or electrostatic discharge. The ends of the bar-shaped openings 129b are formed to have a relatively wide width to facilitate patterning.

Figure 12 is a schematic plan view for explaining a light emitting diode according to another embodiment of the present invention.

Referring to FIG. 12, the light emitting diode according to this embodiment is generally similar to the light emitting diode described with reference to FIG. 11, but the difference is that one bar-shaped opening 129c is formed continuously across the external contact portions 35a1. There is. The bar-shaped opening 129c does not necessarily have to be straight. In particular, a portion of the opening 129c located in a lower area of the first bump pad 39a may be disposed farther from the external contact portion 35a1 than other portions.

FIG. 13 is a schematic plan view for explaining a light emitting diode according to another embodiment of the present invention, and FIG. 14 is a schematic cross-sectional view taken along the cutting line C-C of FIG. 13.

Referring to Figures 13 and 14, the light emitting diode according to this embodiment is generally similar to the previously described embodiments, but a plurality of light emitting cells (C1, C2) are formed, and these light emitting cells (C1, C2) There is a difference in this series connection.

The first and second light emitting cells C1 and C2 are disposed on the substrate 21. The first and second light emitting cells C1 and C2 are separated from each other by a separation region I exposing the substrate 21. Accordingly, the semiconductor layers of the first light emitting cell C1 and the second light emitting cell C2 are spaced apart from each other. The first and second light emitting cells C1 and C2 are arranged facing each other and may each have a square or rectangular shape. In particular, the first and second light emitting cells C1 and C2 may have an elongated rectangular shape facing each other.

The separation area (I) separates the light emitting cells (C1, C2) from each other. Accordingly, the surface of the substrate 21 is exposed through the semiconductor layers in the isolation region I. The separation region (I) is formed using a photo and etching process. By forming a photoresist pattern with a gently sloping surface and using this as a mask to etch the semiconductor layers, a relatively gently sloping side surface is formed in the separation region (I). can form them.

The light emitting cells (C1, C2) face each other with the separation region (I) in between. The sides of the light emitting cells C1 and C2 that face each other are defined as the inner side, and the other sides are defined as the outer side. Accordingly, the first conductive semiconductor layers 23 in the first and second light emitting cells C1 and C2 also include inner and outer surfaces, respectively. For example, the first conductive semiconductor layer 23 may include one inner surface and three outer surfaces.

A mesa (M) is disposed on each first conductive semiconductor layer 23. The mesa (M) may be located limited to the inside of the area surrounded by the first conductive semiconductor layer 23, and therefore, the areas near the edge adjacent to the outer surfaces of the first conductive semiconductor layer 23 are the mesa (M). ) and is exposed to the outside. In another embodiment, the side of the mesa (M) and the side of the first conductivity type semiconductor layer 23 on the sidewall of the isolation region (I) may be continuous with each other.

Each mesa (M) includes a second conductive semiconductor layer 27 and an active layer 25. The active layer 25 is interposed between the first conductive semiconductor layer 23 and the second conductive semiconductor layer 27. Each mesa M has recesses, and in these recesses, as described in detail later, first openings 33a of the lower insulating layer 33 are formed, and the first openings 33a are connected to external contact portions ( 35a1) is formed.

Meanwhile, a conductive oxide layer 28 is disposed on each mesa (M), and the dielectric layer 29 covers the conductive oxide layer 28 and the mesa (M) on each light emitting cell (C1, C2). The conductive oxide layer 28 makes ohmic contact with the second conductive semiconductor layer 27. The conductive oxide layer 28 may be disposed over almost the entire area of the mesa (M) in the upper area of the mesa (M). However, the conductive oxide layer 28 may be spaced apart from the edge of the mesa (M).

The dielectric layer 29 covers the upper area and side surfaces of the mesa (M), and may cover the first conductive semiconductor layer exposed around the mesa (M). The dielectric layer 29 also has openings 29a, 129b, the bar-shaped openings 129b being arranged between the external contacts 35a1 and the other openings 29a. In this embodiment, the bar-shaped openings 129b are shown and described as an example, but in addition to the bar shape, openings of circular, oval or other shapes having a larger size than the openings 29a may be disposed, and may be arranged continuously. A single long line-shaped opening may be disposed on each mesa (M).

The metal reflective layer 31 is disposed on the dielectric layer 29 and connects to the conductive oxide layer 28 through the openings 29a and 129b of the dielectric layer 29. The metal reflective layer 31 is disposed in the upper area of the mesa (M) of each light emitting cell (C1, C2).

The lower insulating layer 33 covers the mesas M and covers the metal reflective layer 31 and the dielectric layer 29. The lower insulating layer 33 also covers the first conductive semiconductor layer 23 and the substrate 21 exposed to the outside of the dielectric layer 29. When the substrate 21 is a patterned sapphire substrate, the lower insulating layer 33 may be formed along the shape of the protrusions on the substrate 21.

The lower insulating layer 33 has first openings 33a exposing the first conductive semiconductor layer 23 within the recesses of each mesa (M), and also has a metal reflection layer ( 31) and a third opening 33b2 exposing the metal reflective layer 31 on the first light emitting cell C1. The first openings 33a expose the first conductive semiconductor layer 23 along the outer surfaces of the mesa (M), and the third openings 33b2 expose the first light emitting cell (C1) near the separation region (I). ) exposes the metal reflective layer 31 on the surface. The third openings 33b2 may generally have an elongated shape along the separation region I, but are not necessarily limited thereto and may have various shapes.

Meanwhile, the second openings 33b1 are located on the second light emitting cell C2 and may be located in a lower area of the second bump pad 39b. However, in another embodiment, the second openings 33b1 may be arranged to be spaced apart in the horizontal direction from the second bump pad 39b on the second light emitting cell C2.

Meanwhile, the first pad metal layer 35a, the second pad metal layer 35b, and the connection metal layer 35c are disposed on the lower insulating layer 33.

The first pad metal layer 35a is disposed on the first light emitting cell C and makes ohmic contact with the first conductive semiconductor layer 23 exposed around the mesa M. As well shown in FIG. 13, the first pad metal layer 35a makes ohmic contact with the first conductive semiconductor layer 23 through the first opening 33a of the lower insulating layer 33 along the perimeter of the mesa M. Thus, external contact portions 35a1 can be formed. In the drawing, the first pad metal layer 35a is shown intermittently in contact with the first conductive semiconductor layer 23 within the recesses of the mesa M along the circumference of the mesa M. However, the present invention It is not limited to this, and continuous contact may be possible. That is, the lower insulating layer 33 is formed to have a first opening 33a continuously exposing the first conductivity type semiconductor layer 23 along the perimeter of the mesa M, and the first pad metal layer 35a is formed at the lower portion M. It is also possible to continuously contact the first conductive semiconductor layer 23 through the first opening 33a of the insulating layer 33.

Meanwhile, the bar-shaped openings 129b of the dielectric layer 29 may be parallel to the first openings 33a of the lower insulating layer 33, and thus may be parallel to the external contact portions 35a1.

The second pad metal layer 35b is disposed on the second light emitting cell C2 and is connected to the metal reflection layer 31 on the second light emitting cell C2 through the second opening 33b1 of the lower insulating layer 33. . The second pad metal layer 35b is located on the mesa (M) and is insulated from the first conductive semiconductor layer 23. For example, the second pad metal layer 35b may be spaced apart from the sides of the mesa M on the second light emitting cell C2.

Meanwhile, the connecting metal layer 35c is electrically connected to the metal reflection layer 31 on the first light-emitting cell C1 through the third opening 33b2 of the lower insulating layer 33, and is connected to the second light-emitting cell C2. It can be electrically connected to the first conductivity type semiconductor layer 23 of the second light emitting cell C2 through the first opening 33a. Accordingly, the first and second light emitting cells C1 and C2 are connected in series to each other through the connecting metal layer 33c.

The connection metal layer 35c may contact the first conductive semiconductor layer 23 within the recesses of the mesa M along the edge of the second light emitting cell C1 to form external contact portions 35a1. . In particular, the connecting metal layer 35c may contact the first conductive semiconductor layer 23 continuously or intermittently along the perimeter of the mesa (M). Additionally, the connection metal layer 35c may surround the second pad metal layer 35b, and a boundary area 35bc may be formed between the connection metal layer 35c and the second pad metal layer 35b. Meanwhile, a boundary area 35ac may be formed between the connection metal layer 35c and the first pad metal layer 35a. These boundary regions 35ac and 35bc are covered with an upper insulating layer 137, which will be described later.

The first and second pad metal layers 35a and 35b and the connection metal layer 35c may be formed together with the same material through the same process. For example, the first and second pad metal layers 35a, 35b and the connection metal layer 35c may include an ohmic reflective layer such as an Al layer, and the ohmic reflective layer may be formed on an adhesive layer such as Ti, Cr, or Ni. You can. Additionally, a protective layer having a single or multiple layer structure of Ni, Cr, Au, etc. may be formed on the ohmic reflection layer. The first and second pad metal layers 35a and 35b and the connection metal layer 35c may have a multilayer structure of, for example, Cr/Al/Ni/Ti/Ni/Ti/Au/Ti.

The upper insulating layer 37 is disposed on the first pad metal layer 35a, the second pad metal layer 35b, and the connecting metal layer 35c, and has a first opening 37a exposing the first pad metal layer 35a, and It has a second opening 37b exposing the second pad metal layer 35b. The upper insulating layer 37 also covers the first pad metal layer 35a and the connecting metal layer 35c connected to the first conductivity type semiconductor layer 23 around the mesa M. As shown in FIG. 13, the area between the first pad metal layer 35a and the connection metal layer 35c and the edge of the first conductive semiconductor layer 23 is covered with the upper insulating layer 37. The upper insulating layer 37 may also cover the connecting metal layer 35c on the separation region I, and may be formed to have irregularities along the shape of the connecting metal layer 35c. The upper insulating layer 37 protects the first and second pad metal layers 35a and 35b and the connecting metal layer 35c from external environments such as moisture.

Meanwhile, the first opening 37a is formed limited to the upper region of the first pad metal layer 35a, and is therefore spaced apart from the connecting metal layer 35c and the third opening 33b2 of the lower insulating layer 33. . Additionally, the second opening 37b is also located limited on the second pad metal layer 35b and is spaced apart from the connection metal layer 35c.

In this embodiment, the first and second pad metal layers 35a and 35b exposed through the first and second openings 37a and 37b of the upper insulating layer 37 are bonding pads to which solder is directly bonded. can be used In contrast, as described with reference to FIGS. 1 and 2, the first and second bump pads 39a and 39b are exposed through the first and second openings 37a and 37b of the upper insulating layer 37. It may cover the first and second pad metal layers 35a and 35b, respectively. The first and second bump pads 39a and 39b may be formed within the first and second openings 37a and 37b of the upper insulating layer 37, but are not limited thereto, and may be formed within the first and second openings 37a and 37b of the upper insulating layer 37. (37a, 37b) can also be covered and sealed.

Figure 15 is a schematic plan view for explaining a light emitting diode according to another embodiment of the present invention.

Referring to FIG. 15, the light emitting diode according to this embodiment includes six light emitting cells (C1, C2, C3, C4, C5, C6), and these light emitting cells are connected in series. Each of the light emitting cells C1 to C6 includes a first conductive semiconductor layer 23 and a mesa M, as described with reference to FIG. 13, and is separated from each other by a separation region.

Each mesa (M) has a via hole 30a exposing the first conductive semiconductor layer 23, and the lower insulating layer 33 exposes the first conductive semiconductor layer 23 within each via hole 30a. It has a first opening 33a that is exposed. Additionally, the lower insulating layer 33 has a second opening 33b exposing the metal reflection layer 31 on each light emitting cell.

Meanwhile, the first pad metal layer 35a is disposed on the first light emitting cell C1 and forms internal contact portions 35a2 within the via holes 30a within the first light emitting cell C1. The second pad metal layer 35b is disposed on the last light emitting cell, that is, the sixth light emitting cell C6, and is connected to the metal reflection layer 31 through the second opening 33b. Meanwhile, the connecting metal layers 35c connect neighboring light emitting cells to each other in series. The connection metal layers 35c electrically connect the metal reflection layers 31 of neighboring light emitting cells to the first conductive semiconductor layer 23. Internal contact portions 35a2 are formed within the via holes 30a of the second to sixth light emitting cells C2 to C6 by the connecting metal layers 35c.

In this embodiment, internal contact parts 35a2 are formed instead of external contact parts 35a1, but external contact parts 35a1 may also be formed.

Meanwhile, in this embodiment, the dielectric layer 29 includes openings 229b along with openings 29a. The openings 29a are widely distributed on each mesa M. Meanwhile, the openings 229b surround the internal contact portions 35a2 on each mesa M. The opening 229b is disposed between the internal contact portion 35a2 and the openings 29a. That is, the opening 229b is disposed closer to the internal contact portion 35a2 than the openings 29a. Accordingly, it is possible to prevent device defects from occurring due to electrical overload or electrostatic discharge in the opening adjacent to the internal contact portion 35a2.

Meanwhile, the first bump pad 39a is disposed on the first light emitting cell C1, and the second bump pad 39b is disposed on the sixth light emitting cell C6. The first to sixth light emitting cells C1 to C6 are connected in series between the first bump pad 39a and the second bump pad 39b.

In this embodiment, the opening 229b is shown as having a ring shape surrounding the via hole 30a, but the present invention is not limited thereto. For example, the opening 229b may be formed in a portion of the outer circumference of the via hole 30a. However, the opening 229b may have a longer shape than the opening 29a. In another embodiment, the openings of the dielectric layer 29 surrounding the via holes 30a on each mesa M may be connected to each other to form an opening 329b as shown in FIG. 16.

(Electrostatic discharge experiment example)

In the embodiment of FIG. 9 together with the light emitting diodes of FIGS. 9 to 12 (Examples 1 to 4), a light emitting diode (comparative example) in which openings 29a are disposed adjacent to external contacts 35a1. The electrostatic discharge characteristics of were compared.

Sixteen samples were prepared and voltages from 1 kV to 6 kV were applied three times at 0.3 second intervals to check whether device defects occurred. From 1kV to 4kV, the voltage was increased by 1kV, and from 4kV to 6kV, the voltage was increased by 0.5kV.

In the light emitting diode of the comparative example, all light emitting diodes failed due to electrostatic discharge at a voltage of 4 kV, and in the light emitting diode of Example 1 of FIG. 9, 2 device defects occurred at 4 kV and 14 devices failed at 4.5 kV.

The light emitting diode of Example 2 in FIG. 10 had 2 device defects at 4.5 kV and 14 devices at 5 kV, and the light emitting diode of Example 3 in FIG. 11 had 1 device defect at 4.5 kV and 6 devices at 5 kV. 6 device defects occurred at 5.5kV.

Meanwhile, in the light emitting diode of Example 4 of FIG. 12, one device defect occurred at 4 kV, seven device defects occurred at 5.5 kV, and eight device defects occurred at 6 kV.

The results of the above experiment are shown in Table 1 below.

Number of device defects (total 16) Applied voltage (kV) One 2 3 4 4.5 5 5.5 6 Comparative example - - - 16 Example 1 - - - 2 14 Example 2 - - - 2 14 Example 3 - - - - One 6 6 3 Example 4 - - - One - - 7 8

Referring to Table 1, it can be seen that the light emitting diodes of Examples 1 to 4 have stronger resistance to electrostatic discharge than the comparative examples. In particular, the light emitting diode of Example 4 (FIG. 12) has an opening in the shape of a long bar. It can be confirmed that has the strongest resistance to electrostatic discharge.

Figure 17 is an exploded perspective view to explain a lighting device using a light emitting diode according to an embodiment of the present invention.

Referring to FIG. 17, the lighting device according to this embodiment includes a diffusion cover 1010, a light emitting device module 1020, and a body portion 1030. The body portion 1030 may accommodate the light emitting device module 1020, and the diffusion cover 1010 may be disposed on the body portion 1030 to cover the top of the light emitting device module 1020.

The body portion 1030 is not limited as long as it can accommodate and support the light emitting device module 1020 and supply electrical power to the light emitting device module 1020. For example, as shown, the body portion 1030 may include a body case 1031, a power supply device 1033, a power case 1035, and a power connection unit 1037.

The power supply device 1033 is accommodated in the power case 1035 and is electrically connected to the light emitting device module 1020, and may include at least one IC chip. The IC chip can adjust, convert, or control the characteristics of the power supplied to the light emitting device module 1020. The power case 1035 may accommodate and support the power supply device 1033, and the power case 1035 with the power supply device 1033 fixed therein may be located inside the body case 1031. . The power connection unit 115 may be disposed at the bottom of the power case 1035 and coupled to the power case 1035. Accordingly, the power connection unit 1037 is electrically connected to the power supply device 1033 inside the power case 1035 and can serve as a passage through which external power can be supplied to the power supply device 1033.

The light emitting device module 1020 includes a substrate 1023 and a light emitting device 1021 disposed on the substrate 1023. The light emitting device module 1020 may be provided on the upper part of the body case 1031 and electrically connected to the power supply device 1033.

The substrate 1023 is not limited as long as it can support the light emitting device 1021, and may be, for example, a printed circuit board including wiring. The substrate 1023 may have a shape corresponding to the fixing portion on the upper part of the body case 1031 so that it can be stably fixed to the body case 1031. The light emitting device 1021 may include at least one of the light emitting diodes according to the embodiments of the present invention described above.

The diffusion cover 1010 may be placed on the light emitting device 1021 and may be fixed to the body case 1031 to cover the light emitting device 1021. The diffusion cover 1010 may be made of a light-transmitting material, and the directivity characteristics of the lighting device may be adjusted by adjusting the shape and light transmittance of the diffusion cover 1010. Therefore, the diffusion cover 1010 may be transformed into various forms depending on the purpose of use and application of the lighting device.

Figure 18 is a cross-sectional view illustrating a display device using a light emitting diode according to another embodiment of the present invention.

The display device of this embodiment includes a display panel 2110, a backlight unit that provides light to the display panel 2110, and a panel guide that supports a lower edge of the display panel 2110.

The display panel 2110 is not particularly limited and may be, for example, a liquid crystal display panel including a liquid crystal layer. A gate driving PCB that supplies a driving signal to the gate line may be further positioned at the edge of the display panel 2110. Here, the gate driving PCB may not be formed on a separate PCB but may be formed on a thin film transistor substrate.

The backlight unit includes a light source module including at least one substrate and a plurality of light emitting devices 2160. Furthermore, the backlight unit may further include a bottom cover 2180, a reflective sheet 2170, a diffusion plate 2131, and optical sheets 2130.

The bottom cover 2180 is opened upward and can accommodate a substrate, a light emitting element 2160, a reflective sheet 2170, a diffusion plate 2131, and optical sheets 2130. Additionally, the bottom cover 2180 may be combined with a panel guide. The substrate may be positioned below the reflective sheet 2170 and surrounded by the reflective sheet 2170. However, it is not limited to this, and if a reflective material is coated on the surface, it may be located on the reflective sheet 2170. In addition, the substrate may be formed in plural, and the plurality of substrates may be arranged side by side, but the present invention is not limited to this and may be formed as a single substrate.

The light emitting device 2160 may include a light emitting diode according to the embodiments of the present invention described above. The light emitting elements 2160 may be regularly arranged in a certain pattern on the substrate. Additionally, a lens 2210 is disposed on each light-emitting device 2160 to improve the uniformity of light emitted from the plurality of light-emitting devices 2160.

The diffusion plate 2131 and the optical sheets 2130 are located on the light emitting device 2160. Light emitted from the light emitting device 2160 may be supplied to the display panel 2110 in the form of a planar light source through the diffusion plate 2131 and the optical sheets 2130.

As such, the light emitting device according to the embodiments of the present invention can be applied to a direct display device such as the present embodiment.

Figure 19 is a cross-sectional view for explaining a display device using a light emitting diode according to another embodiment of the present invention.

A display device equipped with a backlight unit according to this embodiment includes a display panel 3210 on which an image is displayed, and a backlight unit disposed on the back of the display panel 3210 to irradiate light. Furthermore, the display device includes a frame 240 that supports the display panel 3210 and houses a backlight unit, and covers 3240 and 3280 that surround the display panel 3210.

The display panel 3210 is not particularly limited and may be, for example, a liquid crystal display panel including a liquid crystal layer. A gate driving PCB that supplies a driving signal to the gate line may be further positioned at the edge of the display panel 3210. Here, the gate driving PCB may not be formed on a separate PCB but may be formed on a thin film transistor substrate. The display panel 3210 is fixed by covers 3240 and 3280 located at the top and bottom, and the cover 3280 located at the bottom can be coupled to the backlight unit.

The backlight unit that provides light to the display panel 3210 includes a lower cover 3270 with a portion of the upper surface opened, a light source module disposed on one inner side of the lower cover 3270, and a light source module positioned in parallel with the light source module to emit point light. It includes a light guide plate 3250 that converts to surface light. In addition, the backlight unit of this embodiment includes optical sheets 3230 located on the light guide plate 3250 to diffuse and converge light, and disposed below the light guide plate 3250 to transmit light traveling in the lower direction of the light guide plate 3250. It may further include a reflective sheet 3260 that reflects in the direction of the display panel 3210.

The light source module includes a substrate 3220 and a plurality of light emitting elements 3110 arranged on one surface of the substrate 3220 at regular intervals. The substrate 3220 is not limited as long as it supports the light emitting device 3110 and is electrically connected to the light emitting device 3110. For example, it may be a printed circuit board. The light emitting device 3110 may include at least one light emitting diode according to the embodiments of the present invention described above. Light emitted from the light source module is incident on the light guide plate 3250 and supplied to the display panel 3210 through the optical sheets 3230. Through the light guide plate 3250 and the optical sheets 3230, a point light source emitted from the light emitting elements 3110 may be transformed into a planar light source.

In this way, the light emitting device according to the embodiments of the present invention can be applied to an edge-type display device such as this embodiment.

Figure 20 is a cross-sectional view illustrating an example of applying a light emitting diode to a headlamp according to another embodiment of the present invention.

Referring to FIG. 20, the headlamp includes a lamp body 4070, a substrate 4020, a light emitting element 4010, and a cover lens 4050. Furthermore, the headlamp may further include a heat dissipation unit 4030, a support rack 4060, and a connection member 4040.

The substrate 4020 is fixed by a support rack 4060 and spaced apart from the lamp body 4070. The substrate 4020 is not limited as long as it can support the light emitting device 4010, and may be, for example, a substrate with a conductive pattern such as a printed circuit board. The light emitting device 4010 is located on the substrate 4020 and can be supported and fixed by the substrate 4020. Additionally, the light emitting device 4010 can be electrically connected to an external power source through the conductive pattern of the substrate 4020. Additionally, the light emitting device 4010 may include at least one light emitting diode according to the embodiments of the present invention described above.

The cover lens 4050 is located on the path along which light emitted from the light emitting device 4010 travels. For example, as shown, the cover lens 4050 may be arranged to be spaced apart from the light-emitting device 4010 by the connecting member 4040, and may be placed in a direction to provide light emitted from the light-emitting device 4010. You can. The beam angle and/or color of light emitted from the headlamp to the outside may be adjusted by the cover lens 4050. Meanwhile, the connecting member 4040 fixes the cover lens 4050 to the substrate 4020 and may also serve as a light guide that is arranged to surround the light emitting element 4010 and provides a light emission path 4045. At this time, the connecting member 4040 may be formed of a light-reflective material or coated with a light-reflective material. Meanwhile, the heat dissipation unit 4030 may include a heat dissipation fin 4031 and/or a heat dissipation fan 4033, and radiates heat generated when the light emitting device 4010 is driven to the outside.

In this way, the light emitting device according to the embodiments of the present invention can be applied to a headlamp like this embodiment, especially a headlamp for a vehicle.

In the above, various embodiments of the present invention have been described, but the present invention is not limited to these embodiments. Additionally, matters or components described in one embodiment may be applied to other embodiments as long as they do not depart from the technical spirit of the present invention.

Claims (22)

A first conductive semiconductor layer;
a mesa located on the first conductivity type semiconductor layer and including an active layer and a second conductivity type semiconductor layer;
a transparent conductive oxide layer disposed on the mesa and electrically connected to the second conductive semiconductor layer;
a dielectric layer covering the conductive oxide layer and having a plurality of openings exposing the conductive oxide layer;
a metal reflective layer disposed on the dielectric layer and connected to the conductive oxide layer through openings in the dielectric layer;
a lower insulating layer that covers the mesa and the metal reflective layer and includes at least one first opening exposing the first conductive semiconductor layer and a second opening exposing the metal reflective layer;
a first pad metal layer disposed on the lower insulating layer and electrically connected to the first conductive semiconductor layer through the at least one first opening;
a second pad metal layer disposed on the lower insulating layer and electrically connected to the metal reflection layer through the second opening; and
An upper insulating layer covering the first pad metal layer and the second pad metal layer and including a first opening exposing the first pad metal layer and a second opening exposing the second pad metal layer,
A light emitting diode wherein the openings of the dielectric layer include a narrow, elongated bar-shaped opening adjacent to at least one of the first openings of the lower insulating layer. In claim 1,
The dielectric layer includes openings of other shapes in addition to the bar-shaped opening,
A light emitting diode wherein the bar-shaped opening is disposed between a corresponding first opening of the lower insulating layer and other shaped openings of the dielectric layer. In claim 2,
The first opening of the corresponding lower insulating layer has an elongated shape in one direction,
A light emitting diode wherein the bar-shaped opening of the dielectric layer is disposed parallel to the first opening of the corresponding lower insulating layer. In claim 3,
A light emitting diode wherein the bar-shaped opening of the dielectric layer is longer than the first opening of the corresponding lower insulating layer. In claim 1,
The lower insulating layer has a plurality of first openings exposing the first conductive semiconductor layer around the mesa,
A light emitting diode wherein the first pad metal layer has external contact portions that contact the first conductive semiconductor layer at the plurality of first openings. In claim 5,
The dielectric layer has a plurality of bar-shaped openings each adjacent to the plurality of first openings. In claim 5,
A light emitting diode wherein the bar-shaped opening of the dielectric layer is disposed long across the external contact portions. In claim 1,
first bump pad; and
Further comprising a second bump pad,
The first bump pad and the second bump pad are electrically connected to the first pad metal layer and the second pad metal layer through first and second openings of the upper insulating layer, respectively,
At least a portion of the bar-shaped opening is disposed below the first bump pad. In claim 8,
A portion of the bar-shaped opening is a light emitting diode disposed below the second bump pad. In claim 1,
It further includes a substrate located on the side of the first conductive semiconductor layer,
The substrate is a light emitting diode that transmits light generated in the active layer. In claim 1,
The first pad metal layer has protrusions along one edge of the mesa (M),
The first pad metal layer has external contacts contacting the first conductive semiconductor layer near an edge of the mesa, wherein the external contacts are formed by the protrusions,
A light emitting diode wherein an area between the protrusions among the edges of the first pad metal layer is located on the conductive oxide layer. A first conductive semiconductor layer;
a mesa located on the first conductivity type semiconductor layer and including an active layer and a second conductivity type semiconductor layer;
a transparent conductive oxide layer disposed on the mesa and electrically connected to the second conductive semiconductor layer;
a dielectric layer covering the conductive oxide layer and having a plurality of openings exposing the conductive oxide layer;
a metal reflective layer disposed on the dielectric layer and connected to the conductive oxide layer through openings in the dielectric layer;
a lower insulating layer that covers the mesa and the metal reflective layer and includes at least one first opening exposing the first conductive semiconductor layer and a second opening exposing the metal reflective layer;
a first pad metal layer disposed on the lower insulating layer and electrically connected to the first conductive semiconductor layer through the at least one first opening;
a second pad metal layer disposed on the lower insulating layer and electrically connected to the metal reflection layer through the second opening; and
An upper insulating layer covering the first pad metal layer and the second pad metal layer and including a first opening exposing the first pad metal layer and a second opening exposing the second pad metal layer,
The openings in the dielectric layer include openings having different sizes, wherein at least one of the openings in the dielectric layer adjacent to the first opening in the upper insulating layer is located farther from the first opening in the upper insulating layer. A light emitting diode having a greater width or length than at least one other opening. In claim 12,
A light emitting diode wherein the opening of the dielectric layer having the greater width or length has a bar shape. In claim 12,
first bump pad; and
Further comprising a second bump pad,
The first bump pad and the second bump pad are electrically connected to the first pad metal layer and the second pad metal layer through first and second openings of the upper insulating layer, respectively,
At least a portion of the opening of the dielectric layer having the greater width or length is disposed below the first bump pad. In claim 14,
At least one opening of the dielectric layer having the greater width or length extends from a lower part of the first bump pad to a lower part of the second bump pad. In claim 12,
The mesa has a via hole exposing the first conductivity type semiconductor layer,
The first openings of the lower insulating layer include openings exposing the first conductivity type semiconductor layer within the via hole,
The first pad metal layer includes an internal contact portion that contacts the first conductivity type semiconductor layer within the via hole,
A light emitting diode wherein the opening of the dielectric layer having the greater width or length is disposed adjacent to the via hole. In claim 16,
A light emitting diode wherein the opening of the dielectric layer disposed adjacent to the via hole surrounds the via hole. In claim 12,
The first pad metal layer includes external contact portions that contact the first conductive semiconductor layer outside the mesa,
The external contact parts are spaced apart from each other,
A light emitting diode wherein openings of the dielectric layer having the greater width or length are respectively disposed adjacent to the external contacts. In claim 12,
The dielectric layer has a lower refractive index than the second conductive semiconductor layer and the conductive oxide layer, and has a thickness in the range of 300 nm to 800 nm. In claim 19,
A light emitting diode wherein the conductive oxide layer has a thickness ranging from 3 nm to 50 nm. In claim 12,
It further includes a substrate located on the side of the first conductive semiconductor layer,
The substrate is a light emitting diode that transmits light generated in the active layer. A first conductive semiconductor layer;
a mesa located on the first conductivity type semiconductor layer and including an active layer and a second conductivity type semiconductor layer;
a transparent conductive oxide layer disposed on the mesa and electrically connected to the second conductive semiconductor layer;
a dielectric layer covering the conductive oxide layer and having a plurality of openings exposing the conductive oxide layer;
a metal reflective layer disposed on the dielectric layer and connected to the conductive oxide layer through openings in the dielectric layer;
a lower insulating layer that covers the mesa and the metal reflective layer and includes at least one first opening exposing the first conductive semiconductor layer and a second opening exposing the metal reflective layer;
a first pad metal layer disposed on the lower insulating layer and electrically connected to the first conductive semiconductor layer through the at least one first opening;
a second pad metal layer disposed on the lower insulating layer and electrically connected to the metal reflection layer through the second opening; and
An upper insulating layer covering the first pad metal layer and the second pad metal layer and including a first opening exposing the first pad metal layer and a second opening exposing the second pad metal layer,
The openings of the dielectric layer include openings located below the first opening of the upper insulating layer, and among the openings of the dielectric layer located below the first opening of the upper insulating layer and adjacent to the first opening of the lower insulating layer. A light emitting diode wherein the separation distance of the opening vertically spaced apart from the first opening of the lower insulating layer is longer than the separation distance of the opening of the dielectric layer closest to the first opening of the lower insulating layer from the first opening of the lower insulating layer. .

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