KR102610341B1 - Oxide Thin Film Transistor Based Scan Driver Circuit - Google Patents

Abstract

A scan driver circuit is disclosed. The scan driver circuit according to the present disclosure may include a first oxide TFT to a tenth oxide TFT. The scan driver circuit according to the present disclosure includes a mechanism that allows the circuit to operate stably even when some of the oxide TFTs exhibit depletion mode characteristics. This scan driver circuit can operate based on four clock signals. The first clock signal and the second clock signal are signals in which a first low level voltage and a high level voltage are alternately repeated. The second clock signal is out of phase with the first clock signal. The third clock signal and the fourth clock signal are signals in which a second low level voltage lower than the first low level voltage and the high level voltage are alternately repeated. The third clock signal is in phase with the first clock signal. The fourth clock signal is in phase with the second clock signal.

Description

Scan driver circuit based on oxide thin film transistor {Oxide Thin Film Transistor Based Scan Driver Circuit}

The disclosure below relates to a scan driver circuit that controls pixel switches of a display panel.

In small and medium-sized OLED (Organic Light Emitting Diode) displays used in smartphones, etc., low-temperature polycrystalline silicon (LTPS) TFT is used to form the pixel circuit and scan driver circuit. The existing LTPS TFT has the advantage of high charge mobility and stable characteristics, but has the problem of high manufacturing cost. On the other hand, if both the pixel circuit and scan driver circuit of a small and medium-sized OLED display are configured using the oxide TFT used in recent large-sized OLED displays, not only does it have the advantage of lowering manufacturing costs, but it can also reduce driving power consumption based on low leakage current. There are also advantages. However, oxide TFTs have a disadvantage in that they often exhibit depletion mode characteristics due to their relatively low charge mobility and lack of stability. In the case of oxide TFTs that exhibit depletion mode characteristics, there is a critical problem in that they do not turn off completely even when 0 V is applied between their gate terminal and source terminal, which reduces the operational stability of the circuit and actually increases power consumption. To compensate for these shortcomings, the scan driver circuit has become complicated, so it is still difficult to apply oxide TFT to small and medium-sized OLED displays. Therefore, much research is being conducted to develop scan driver circuits based on oxide TFTs with a simple structure.

The problem to be solved by the present disclosure is to provide a scan driver circuit that operates stably and can reduce manufacturing costs and/or power consumption.

The problems to be solved by the present disclosure are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

According to one aspect of the present disclosure, a scan driver circuit is provided. This scan driver circuit includes a first terminal connected to an input terminal for receiving scan input pulses, a first oxide TFT having a gate terminal and a second terminal to which a third clock signal is supplied, a gate terminal to which a high power voltage is supplied, An eighth oxide TFT having a first terminal and a second terminal connected to the second terminal of the first oxide TFT, a gate terminal to which the third clock signal is supplied, a first terminal and a second terminal to which the high power voltage is supplied. A fifth oxide TFT having a terminal, a second terminal to which a first clock signal is supplied, a gate terminal and a first terminal commonly connected to the second terminal of the first oxide TFT and the second terminal of the eighth oxide TFT. It has a ninth oxide TFT, a second terminal connected to the first terminal of the ninth oxide TFT, a gate terminal commonly connected to the second terminal of the first oxide TFT and the second terminal of the eighth oxide TFT, and a second terminal connected to the first terminal of the ninth oxide TFT. A fourth oxide TFT having one terminal, a gate terminal commonly connected to the second terminal of the fifth oxide TFT and the first terminal of the fourth oxide TFT, a first terminal to which the high voltage level is supplied, and the ninth terminal. A tenth oxide TFT having a second terminal commonly connected to the first terminal of the oxide TFT and the second terminal of the fourth oxide TFT, a gate terminal to which a fourth clock signal is supplied, a first terminal, and a second terminal. A third oxide TFT, a gate terminal commonly connected to the first terminal of the third oxide TFT and the first terminal of the eighth oxide TFT, a first terminal to which a second clock signal is supplied, and a second terminal connected to an output node. a seventh oxide TFT having a second terminal of the fifth oxide TFT, a gate terminal commonly connected to the first terminal of the fourth oxide TFT and a gate terminal of the tenth oxide TFT, and a second terminal of the third oxide TFT. A second oxide TFT having a first terminal connected to a terminal and a second terminal to which a low power voltage is supplied, and a second terminal of the fifth oxide TFT, a first terminal of the fourth oxide TFT, and the tenth oxide TFT It may include a sixth oxide TFT having a gate terminal commonly connected to the gate terminal of , a first terminal connected to the output node, and a second terminal to which the low power voltage is supplied.

In one embodiment, the first clock signal is a signal in which a first low level voltage and a high level voltage are alternately repeated, and the second clock signal is a signal in which the first low level voltage and the high level voltage are alternately repeated. signal - the second clock signal is out of phase with the first clock signal - and the third clock signal alternately repeats a second low level voltage lower than the first low level voltage and the high level voltage. signal - the third clock signal is in phase with the first clock signal -, the fourth clock signal is a signal in which the second low level voltage and the high level voltage are alternately repeated - the fourth clock signal is in phase with the second clock signal.

In one embodiment, the scan driver circuit has one terminal commonly connected to the first terminal of the third oxide TFT, the first terminal of the eighth oxide TFT, and the gate terminal of the seventh oxide TFT, and the other terminal. further includes a capacitor (C2) connected to the output node.

In one embodiment, the scan driver circuit has one terminal connected to the second terminal of the fifth oxide TFT, the first terminal of the fourth oxide TFT, the gate terminal of the tenth oxide TFT, and the gate terminal of the second oxide TFT. It further includes a capacitor C1 that is commonly connected to the terminal and whose other terminal is supplied with the low power voltage.

In one embodiment, the scan driver circuit is configured such that the first clock signal and the third clock signal have the high level voltage, the second clock signal has the first low level voltage, and the fourth clock signal has the high level voltage. In response to the scan input pulse being input to the input terminal in a first time period having a second low level voltage, the first clock signal has the first low level voltage and the third clock signal has the second low level voltage. It operates to output a high-level scan output signal to the output node in a second time period in which the second clock signal and the fourth clock signal have a low-level voltage and the high-level voltage.

In one embodiment, the fifth oxide TFT has depletion mode characteristics, and the fifth oxide TFT transmits the second low level of the third clock signal to the gate of the fifth oxide TFT in the second time period. It is operated to turn off in response to voltage being supplied.

In one embodiment, the fourth oxide TFT has depletion mode characteristics, wherein the first clock signal has the first low level voltage and the third clock signal has the second low level voltage. In a time section in which the second clock signal and the fourth clock signal have the high level voltage, the first terminal of the ninth oxide TFT and the second terminal of the fourth oxide TFT are connected through the tenth oxide TFT. It is operated to turn off in response to the high power supply voltage being supplied.

In one embodiment, the first to tenth oxide TFTs are n-channel oxide TFTs.

According to the disclosed embodiments, there is a technical effect of implementing a scan driver circuit that operates stably and can reduce manufacturing costs and/or power consumption.

1 is a diagram illustrating a circuit diagram of an embodiment of a scan driver circuit based on an oxide thin film transistor (TFT) according to the present disclosure.
FIG. 2 is a diagram showing a timing diagram of the clock signals in FIG. 1 and signals at various nodes in the scan driver circuit.

Specific structural or functional descriptions of the embodiments are disclosed for illustrative purposes only and may be changed and implemented in various forms. Accordingly, the actual implementation form is not limited to the specific disclosed embodiments, and the scope of the present disclosure includes changes, equivalents, or substitutes included in the technical idea described in the embodiments.

Although terms such as “first” or “second” may be used to describe various components, these terms should be interpreted only for the purpose of distinguishing one component from another component. For example, a “first component” may be named a “second component” and similarly, a “second component” may also be named a “first component”.

When a component is referred to as being “connected” to another component, it should be understood that it may be directly connected or connected to the other component, but that other components may exist in between.

Singular expressions include plural expressions unless the context clearly dictates otherwise. In the present disclosure, terms such as "comprise" or "have" are intended to designate the presence of the described features, numbers, steps, operations, components, parts, or combinations thereof, and are intended to indicate the presence of one or more other features or numbers, It should be understood that this does not exclude in advance the possibility of the presence or addition of steps, operations, components, parts, or combinations thereof.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the art. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the related technology, and should not be interpreted in an idealized or overly formal sense unless explicitly defined in the present disclosure. No.

Hereinafter, embodiments will be described in detail with reference to the attached drawings. In the description with reference to the accompanying drawings, identical components will be assigned the same reference numerals regardless of the reference numerals, and overlapping descriptions thereof will be omitted.

1 is a diagram illustrating a circuit diagram of an embodiment of a scan driver circuit based on an oxide thin film transistor (TFT) according to the present disclosure. FIG. 2 is a diagram showing a timing diagram of the clock signals in FIG. 1 and signals at various nodes in the scan driver circuit.

The scan driver circuit 100 of FIG. 1 may be configured to receive a scan input pulse (Scan[n-1]) from an input terminal and output a scan output signal (Scan[n]) from an output node in response. The scan output signal (Scan[n]) can be supplied to one of the pixel switches included in a pixel circuit arranged in a display panel, such as an OLED (Organic Light Emitting Diode) display panel, to control the pixel switch. . The scan driver circuit 100 according to the present disclosure may include a plurality of oxide TFTs. In one embodiment, the scan driver circuit 100 may be designed based on an n-channel oxide TFT. The scan driver circuit 100 according to the present disclosure includes not only the two clock signals (CK1 and CK2) previously used to complement the depletion mode characteristics of the oxide TFT, but also the clock signals and their waveform patterns correspond to each other, but low It can be operated based on two additional clock signals (CLK1, CLK2) that only step down in level to a lower voltage. For this, four clocks can be used. The first clock generates a clock signal (CK1) in which the low level voltage (VGL) and the high level voltage are alternately repeated (see FIG. 2). The second clock generates a clock signal CK2 in which the low level voltage VGL and the high level voltage are alternately repeated (see FIG. 2). Here, the clock signal CK2 is out of phase with the clock signal CK1. The third clock generates a clock signal (CKL1) in which low-level voltage (VGLL) and high-level voltage are alternately repeated, and its waveform pattern corresponds to the clock signal (CK1), but goes down to a lower voltage (VGLL) only at the low level. (See Figure 2). The fourth clock alternately repeats the low level voltage (VGLL) and the high level voltage and generates a clock signal (CKL2) whose waveform pattern corresponds to the clock signal (CK2) but goes down to a lower voltage (VGLL) only at the low level. (See Figure 2). Here, the clock signal CKL2 is out of phase with the clock signal CKL1. In one embodiment, the duty cycle of the clock signals CK1, CK2, CKL1, and CKL2 may be between about 40 percent and 45 percent. The oxide TFTs included in the scan driver circuit 100 according to the present disclosure may be operated based on a high power supply voltage (VGH) and a low power supply voltage (VGL). In a TFT, among the two terminals other than the gate terminal, the terminal to which a high voltage is supplied or maintained is called the drain terminal, and the terminal to which a low voltage is supplied or maintained is called a source terminal. Therefore, the following description For convenience, one of the two terminals other than the gate terminal of the TFT will be referred to as the first terminal, and the other terminal will be referred to as the second terminal.

Referring to FIG. 1, the scan driver circuit 100 according to the present disclosure includes a first terminal connected to an input terminal for receiving a scan input pulse (Scan[n-1]), and a gate terminal to which a clock signal (CKL1) is supplied. and a first oxide TFT (M1) having a second terminal. The scan driver circuit 100 includes an eighth oxide TFT (M8) having a gate terminal to which a high power voltage (VGH) is supplied, a second terminal connected to the second terminal of the first oxide TFT (M1), and a first terminal. More may be included. Here, the voltage at the node between the second terminal of the first oxide TFT (M1) and the second terminal of the eighth oxide TFT (M8) is referred to as P[n], and the voltage at the node between the second terminal of the eighth oxide TFT (M8) is referred to as P[n]. The voltage at is called Q[n]. The scan driver circuit 100 may further include a fifth oxide TFT (M5) having a gate terminal to which a clock signal (CLK1) is supplied, a first terminal and a second terminal to which a high power voltage (VGH) is supplied. The scan driver circuit 100 has a second terminal to which the clock signal CK1 is supplied, a voltage P[ n] may further include a ninth oxide TFT (M9) having a gate terminal to which n] is supplied and a first terminal. The scan driver circuit 100 has a second terminal connected to the first terminal of the ninth oxide TFT (M9), a second terminal between the second terminal of the first oxide TFT (M1) and the second terminal of the eighth oxide TFT (M8). It may further include a fourth oxide TFT (M4) having a first terminal and a gate terminal to which a signal P[n] from the node is supplied. The scan driver circuit 100 includes a gate terminal commonly connected to the second terminal of the fifth oxide TFT (M5) and the first terminal of the fourth oxide TFT (M4), and a first terminal to which a high voltage level (VGH) is supplied. and a tenth oxide TFT (M10) having a second terminal connected to a node between the first terminal of the ninth oxide TFT (M9) and the second terminal of the fourth oxide TFT (M4). Here, the voltage at the node between the second terminal of the fifth oxide TFT (M5), the first terminal of the fourth oxide TFT (M4), and the gate terminal of the tenth oxide TFT (M10) is referred to as QB[n].

Continuing to refer to FIG. 1 , the scan driver circuit 100 may further include a third oxide TFT (M3) having a gate terminal to which the clock signal (CKL2) is supplied, a first terminal, and a second terminal. The scan driver circuit 100 includes a gate terminal commonly connected to the first terminal of the third oxide TFT (M3) and the first terminal of the eighth oxide TFT (M8), a first terminal to which a clock signal (CK2) is supplied, and It may further include a seventh oxide TFT (M7) having a second terminal connected to an output node where the scan output signal (Scan[n]) is output. The scan driver circuit 100 has one terminal commonly connected to the first terminal of the third oxide TFT (M3), the first terminal of the eighth oxide TFT (M8), and the gate terminal of the seventh oxide TFT (M7). and may further include a capacitor (C2) whose other terminal is connected to the output node. The scan driver circuit 100 includes a gate terminal commonly connected to the second terminal of the fifth oxide TFT (M5), the first terminal of the fourth oxide TFT (M4), and the gate terminal of the tenth oxide TFT (M10), and a third terminal. It may further include a second oxide TFT (M2) having a first terminal connected to the second terminal of the oxide TFT (M3) and a second terminal to which a low power voltage (VGL) is supplied. The scan driver circuit 100 includes a gate terminal and an output node commonly connected to the second terminal of the fifth oxide TFT (M5), the first terminal of the fourth oxide TFT (M4), and the gate terminal of the tenth oxide TFT (M10). It may further include a sixth oxide TFT (M6) having a first terminal connected to and a second terminal to which a low power voltage (VGL) is supplied. The scan driver circuit 100 has one terminal connected to the second terminal of the fifth oxide TFT (M5), the first terminal of the fourth oxide TFT (M4), the gate terminal of the tenth oxide TFT (M10), and the second oxide terminal. It may further include a capacitor (C1) that is commonly connected to the gate terminal of the TFT (M2) and whose other terminal is supplied with a low power supply voltage (VGL).

Hereinafter, the operation of the scan driver circuit 100 will be described in detail with reference to FIGS. 1 and 2.

First, the scan input pulse (Scan[n -1]) transitions to the high level. In this case, the oxide TFT (M1) turns on and the voltage (P[n]) becomes high level, the oxide TFT (M8) turns on, the voltage (Q[n]) becomes high level and the oxide TFT (M7) turns on. do. Additionally, the oxide TFT (M9) and oxide TFT (M4) are turned on, the oxide TFT (M10) is turned on, the oxide TFT (M5) is turned on, the voltage (QB[n]) is at a high level, and the oxide TFT (M2) is turned on. is turned on, the oxide TFT (M6) is turned on, and the oxide TFT (M3) is turned off. In this state, both the oxide TFT (M7) and the oxide TFT (M6) are on, so the output node is connected to the low level voltage of the clock signal (CK2) and at the same time is pulled down to the low power supply voltage (VGL), resulting in scan output. The signal (Scan[n]) becomes low level.

At the beginning of the second time period when the clock signal CK1 and CKL1 are in a low level state and the clock signal CK2 and CLK2 are in a high level state, the scan input pulse (Scan[n-1 ]) transitions to the low level. In this case, the oxide TFT (M1) is turned off, the voltage (P[n]) remains at a high level, and the voltage (Q[n]) is also at a high level, so the oxide TFT (M7) is turned on and the clock signal ( The high level voltage of CK2) is transmitted to the output node, and as a result, the scan output signal (Scan[n]) becomes high level. Meanwhile, the oxide TFT (M8) is turned off. The reason is that the capacitor C2 is charged to a high level voltage during the first time period, and as the scan output signal Scan[n] rises to the high level voltage, the voltage Q[n] increases to the high level voltage. The voltage increases by two times, and that voltage is transferred to the node where the voltage (P[n]) is provided, resulting in the gate-source voltage of the oxide TFT (M8) ( ) is lower than the threshold voltage. On the other hand, the oxide TFT (M9), oxide TFT (M4) and oxide TFT (M3) are turned on and the oxide TFT (M10) and oxide TFT (M5) are turned off and the voltage (QB[n]) is at low level. , Accordingly, the oxide TFT (M2) and the oxide TFT (M6) are turned off to isolate the output node from the low power supply voltage (VGL). The above stable operation of the scan driver circuit 100 according to the present disclosure is made possible by a configuration that supplies the clock signal (CKL1) to the gate terminal of the oxide TFT (M5). In order for the scan driver circuit 100 to operate stably in the second time period, the voltage (QB[n]) must be maintained at a low level to turn off the oxide TFT (M6). If the gate terminal of the oxide TFT (M5) is turned off, If the clock signal CK1 is supplied as before and the oxide TFT (M5) has depletion mode characteristics, the oxide TFT (M5) is not completely turned off. Then, the high power supply voltage (VGH) affects the low-level voltage (QB[n]) through the oxide TFT (M5), causing the voltage (QB[n]) to increase slightly, and thus the oxide TFT (M2) and the oxide TFT (M6) may be slightly turned on. Therefore, in the present disclosure, stable operation of the scan driver circuit 100 is achieved by completely turning off the oxide TFT (M5) using the low voltage (VGLL) of the clock signal (CKL1).

In the third time period when the clock signal (CK1) and the clock signal (CKL1) are in the high level state and the clock signal (CK2) and the clock signal (CLK2) are in the low level state, the scan input pulse (Scan[n-1]) remains at the low level. In this case, the oxide TFT (M1) is turned on and the voltage (P[n]) transitions to a low level, and the oxide TFT (M8) is turned on and the voltage (Q[n]) also transitions to a low level, causing the oxide TFT (M7) to turn on. turns off. Additionally, the oxide TFT (M9), oxide TFT (M4), and oxide TFT (M3) are turned off, and the oxide TFT (M10) and oxide TFT (M5) are turned on, and the voltage (QB[n]) becomes high level, thereby turning the oxide TFT (M10) on. The TFT (M2) and the oxide TFT (M6) are turned on and the scan output signal (Scan[n]) becomes low level.

Even in the fourth time period when the clock signal (CK1) and clock signal (CKL1) are in a low level state and the clock signal (CK2) and clock signal (CLK2) are in a high level state, the scan input pulse (Scan[n-1]) It still remains at a low level. In this case, the oxide TFT (M1) is turned off and the voltage (P[n]) is maintained at a low level, the oxide TFT (M8) is turned on and the voltage (Q[n]) is also maintained at a low level, and the oxide TFT (M7) is maintained at a low level. ) also remains off. Meanwhile, the oxide TFT (M9) and oxide TFT (M4) are turned off, the oxide TFT (M10) and oxide TFT (M3) are turned on, the oxide TFT (M5) is turned off, and the voltage (QB[n]) is maintained at a high level. Accordingly, the oxide TFT (M2) and the oxide TFT (M6) are turned on and the scan output signal (Scan[n]) is maintained at a low level. The above stable operation of the scan driver circuit 100 according to the present disclosure is made possible by a configuration in which an oxide TFT (M9) and an oxide TFT (M10) are added compared to the existing one. In order for the scan driver circuit 100 to operate stably in the fourth time period, the voltage (QB[n]) must be maintained at a high level to keep the oxide TFT (M6) in the on state. If the oxide TFT (M9) ) and if there is no oxide TFT (M10) and the oxide TFT (M4) has depletion mode characteristics, the voltage (P[n]) will not be low enough to turn off the oxide TFT (M4), so the oxide TFT (M4) M4) does not turn off completely. Then, the low level voltage of the clock signal (CK1) may affect the voltage (QB[n]) in the high level state, causing the voltage (QB[n]) to be slightly lowered, and as a result, the oxide TFT (M6) will be completely turned on. It won't be possible. Therefore, in the present disclosure, the oxide TFT (M9) and the oxide TFT (M10) are added to the circuit 100 to apply a high power voltage (VGH) to the oxide TFT (M9) and the oxide TFT (M10) through the oxide TFT (M10) in the on state. The voltage between the gate and source of the oxide TFT (M4) ( ) is lower than the threshold voltage to completely turn off the oxide TFT (M4).

As described above, according to the scan driver circuit 100 of the present disclosure, even when some oxide TFTs with depletion mode characteristics exist in the circuit 100, the circuit ( 100) can operate stably. In addition, the scan driver circuit 100 of the present disclosure is constructed using an oxide TFT that not only has a lower manufacturing cost than the existing LTPS TFT but also has a significantly lower leakage current, so the manufacturing cost is reduced compared to the existing LTPS TFT scan driver circuit. This can have the effect of reducing power consumption by lowering the screen refresh rate of the OLED display.

In the above description, the meaning of a description that a component is connected or combined with another component not only means that the component is directly connected or combined with the other component, but also one or more other components interposed between them. It should be understood to include the meaning that it can be connected or combined through elements. In addition, terms used to describe relationships between components (e.g., ‘on’, ‘above’, ‘above’, ‘between’, ‘between’, etc.) should be interpreted with a similar meaning.

In the embodiments disclosed herein, the arrangement of the components shown may vary depending on the environment or requirements in which the technology is implemented. For example, some components may be omitted or some components may be integrated and implemented as one. Additionally, the arrangement order and connection of some components may change.

As described above, although the embodiments have been described with limited drawings, those skilled in the art can apply various technical modifications and variations based on this. For example, the described techniques are performed in a different order than the described method, and/or components of the described system, structure, device, circuit, etc. are combined or combined in a different form than the described method, or other components are used. Alternatively, appropriate results may be achieved even if substituted or substituted by an equivalent.

Therefore, other implementations, other embodiments, and equivalents of the claims also fall within the scope of the claims described below.

M1: First oxide TFT
M2: Second oxide TFT
M3: Tertiary oxide TFT
M4: Quaternary oxide TFT
M5: Fifth oxide TFT
M6: sixth oxide TFT
M7: Seventh oxide TFT
M8: 8th oxide TFT
M9: 9th oxide TFT
M10: 10th oxide TFT

Claims (8)

As a scan driver circuit,
A first oxide TFT having a first terminal connected to an input terminal for receiving a scan input pulse, a gate terminal to which a third clock signal is supplied, and a second terminal,
An eighth oxide TFT having a gate terminal to which a high power voltage is supplied, a second terminal and a first terminal connected to the second terminal of the first oxide TFT,
A fifth oxide TFT having a gate terminal to which the third clock signal is supplied, a first terminal and a second terminal to which the high power voltage is supplied,
A ninth oxide TFT having a second terminal to which a first clock signal is supplied, a gate terminal and a first terminal commonly connected to the second terminal of the first oxide TFT and the second terminal of the eighth oxide TFT,
A fourth terminal having a second terminal connected to the first terminal of the ninth oxide TFT, a gate terminal and a first terminal commonly connected to the second terminal of the first oxide TFT and the second terminal of the eighth oxide TFT oxide TFT,
A gate terminal commonly connected to the second terminal of the fifth oxide TFT and the first terminal of the fourth oxide TFT, the first terminal to which the high voltage level is supplied, the first terminal of the ninth oxide TFT, and the first terminal of the fourth oxide TFT. A tenth oxide TFT having a second terminal commonly connected to the second terminal of the four oxide TFT,
A third oxide TFT having a gate terminal to which a fourth clock signal is supplied, a first terminal, and a second terminal,
A seventh oxide having a gate terminal commonly connected to the first terminal of the third oxide TFT and the first terminal of the eighth oxide TFT, a first terminal to which a second clock signal is supplied, and a second terminal connected to an output node. TFTs,
A gate terminal commonly connected to the second terminal of the fifth oxide TFT, the first terminal of the fourth oxide TFT, and the gate terminal of the tenth oxide TFT, and the first terminal connected to the second terminal of the third oxide TFT and a second oxide TFT having a second terminal to which a low power supply voltage is supplied, and
A gate terminal commonly connected to the second terminal of the fifth oxide TFT, the first terminal of the fourth oxide TFT, and the gate terminal of the tenth oxide TFT, the first terminal connected to the output node, and the low power supply voltage are supplied. comprising a sixth oxide TFT having a second terminal
Scan driver circuit. According to paragraph 1,
The first clock signal is a signal in which a first low level voltage and a high level voltage are alternately repeated,
The second clock signal is a signal in which the first low level voltage and the high level voltage are alternately repeated - the second clock signal is a clock signal in the form of the first clock signal shifted by a half cycle -,
The third clock signal is a signal in which a second low level voltage lower than the first low level voltage and the high level voltage are alternately repeated - the third clock signal is in phase with the first clock signal -,
The fourth clock signal is a signal in which the second low level voltage and the high level voltage are alternately repeated - the fourth clock signal is in phase with the second clock signal -,
Scan driver circuit. According to paragraph 2,
A capacitor (C2), one terminal of which is commonly connected to the first terminal of the third oxide TFT, the first terminal of the eighth oxide TFT, and the gate terminal of the seventh oxide TFT, and the other terminal connected to the output node. containing more
Scan driver circuit. According to paragraph 3,
One terminal is commonly connected to the second terminal of the fifth oxide TFT, the first terminal of the fourth oxide TFT, the gate terminal of the tenth oxide TFT, and the gate terminal of the second oxide TFT, and the other terminal is connected to the second terminal of the fifth oxide TFT. Further comprising a capacitor (C1) supplied with a low power supply voltage.
Scan driver circuit. According to paragraph 2,
The scan driver circuit is,
A first time period in which the first clock signal and the third clock signal have the high level voltage, the second clock signal has the first low level voltage, and the fourth clock signal has the second low level voltage. In response to the scan input pulse being input to the input terminal,
A second time period in which the first clock signal has the first low level voltage, the third clock signal has the second low level voltage, and the second clock signal and the fourth clock signal have the high level voltage. Operates to output a high-level scan output signal from the output node,
Scan driver circuit. According to clause 5,
The fifth oxide TFT has depletion mode characteristics,
The fifth oxide TFT is operated to be turned off in response to the second low level voltage of the third clock signal being supplied to the gate of the fifth oxide TFT in the second time period,
Scan driver circuit. According to clause 5,
The fourth oxide TFT has depletion mode characteristics,
The fourth oxide TFT is configured such that the first clock signal has the first low level voltage, the third clock signal has the second low level voltage, and the second clock signal and the fourth clock signal have the high level. Operated to turn off in response to the high power supply voltage being supplied to the first terminal of the ninth oxide TFT and the second terminal of the fourth oxide TFT through the tenth oxide TFT in a time period having a voltage,
Scan driver circuit. According to paragraph 1,
The first to tenth oxide TFTs are n-channel oxide TFTs,
Scan driver circuit.