KR102599084B1 - Photoconductive semiconductor switch and method of fabricating the same - Google Patents

Abstract

A photoconductive semiconductor switch according to the present invention includes a semiconductor substrate, a pair of electrodes disposed on both ends of the semiconductor substrate in a first direction, and extending in the first direction between the pair of electrodes and spaced apart in the second direction. It includes fin structures disposed so as to be disposed, and an opaque resin layer buried between the fin structures on the semiconductor substrate.

Description

Photoconductive semiconductor switch and method of fabricating the same}

The present invention relates to a photoconductive semiconductor switch and a method of manufacturing the same, and more specifically, to a photoconductive semiconductor switch having a periodically arranged fin structure for dispersing current filaments and a photoconductive semiconductor switch having a periodic fin structure using a half cut process. It relates to a method of manufacturing a semiconductor switch.

Photoconductive Semiconductor Switch (PCSS) is a semiconductor switch that utilizes the phenomenon of a rapid increase in electrical conductivity when appropriate light that can generate optical carriers is incident on a semiconductor material with high sheet resistance.

Figure 1 shows a perspective view of a conventional photoconductive semiconductor switch.

Referring to FIG. 1 , the photoconductive semiconductor switch 10 includes a semiconductor substrate 11 and a pair of electrodes 12 and 13 disposed on the semiconductor substrate 11 to be spaced apart from each other. The electrodes 12 and 13 may form ohmic contact with the semiconductor substrate 11 through heat treatment. When light is incident on the semiconductor substrate 11 between the electrodes 12 and 13 while a predetermined voltage is applied between the electrodes 12 and 13, the electrical conductivity increases and the Current flows in

If the electrical conductivity of the photoconductive semiconductor switch increases linearly as the size of the incident light increases, that is, if the size of the incident light and the electrical conductivity value have a linear relationship, it is called ‘linear mode’. If there is a nonlinear relationship in which the electrical conductivity value of the photoconductive semiconductor switch increases rapidly compared to the size of the incident light, it is called a ‘nonlinear mode’.

In the case of a GaAs photoconductive semiconductor switch using a gallium arsenide (GaAs) substrate with intrinsic or very little dopant added, it operates in ‘nonlinear mode’ when the potential difference between the two electrodes is large. For example, when a potential difference greater than approximately 4kV/cm to 8kV/cm depending on the type of GaAs substrate is applied to both ends of the electrodes of the photoconductive semiconductor switch, it operates in a nonlinear mode.

When a GaAs photoconductive semiconductor switch operates in ‘nonlinear mode’, a filamentation phenomenon in which a large amount of switching current is concentrated in a small area may occur. The filamentation phenomenon occurs mainly at the interface between the electrodes 12 and 13 and the semiconductor substrate 11, and is especially concentrated at the point where the lower edge of the electrodes 12 and 13 and the semiconductor substrate 11 meet. . This worsens the characteristics of the area where the filamentation phenomenon occurs, resulting in a decrease in overall device durability.

Several methods have been proposed to control current concentration in photoconductive semiconductor switches. For example, a method of forming a thick, high-doped layer under the electrode, a method of introducing an opposed electrode that forms two electrodes on both sides of the substrate, and a method of introducing an opposed electrode on the back of the semiconductor substrate. A back-side illumination method, etc. has been proposed. However, these methods cannot solve the filamentation phenomenon of the switching current itself.

The problem to be solved by the present invention is to provide a photoconductive semiconductor switch in which current paths are physically separated by creating a periodic pin structure on a semiconductor substrate.

The problem to be solved by the present invention is to provide a method of manufacturing a photoconductive semiconductor switch having a periodic pin structure.

As a technical means for achieving the above-described technical problems, a photoconductive semiconductor switch according to one aspect of the present invention includes a semiconductor substrate, a pair of electrodes disposed on both ends of the semiconductor substrate in the first direction, and the pair of electrodes. It includes fin structures extending in the first direction and spaced apart in the second direction between electrodes, and an opaque resin layer buried between the fin structures on the semiconductor substrate.

According to one example, the fin structures may be integrated with the semiconductor substrate.

According to another example, both ends of the fin structures may be electrically connected to the pair of electrodes, respectively.

According to another example, the top surface of the fin structures, the top surface of the pair of electrodes, and the top surface of the opaque resin layer may be at the same level.

According to another example, the opaque resin layer may block a laser beam having a wavelength between 700 nm and 1000 nm.

According to another example, the semiconductor substrate may be a gallium arsenide (GaAs) substrate.

According to another example, the thickness of each of the fin structures may be thinner than the gap between the fin structures.

A method of manufacturing a photoconductive semiconductor switch according to an aspect of the present invention includes forming a plurality of first trenches extending in a first direction and spaced apart in a second direction on a first side of a semiconductor wafer using a half-cut process; Applying an opaque resin material on the semiconductor wafer in which the plurality of first trenches are formed to form an opaque resin layer buried in the plurality of first trenches, wherein the plurality of first trenches in which the opaque resin layer is embedded are forming a plurality of second trenches extending in the second direction and spaced apart in the first direction on the first surface of the formed semiconductor wafer, depositing an electrode material in the plurality of second trenches to form the plurality of second trenches 2. It includes forming an electrode layer buried in the trench, and dicing the semiconductor wafer along first scribe lines extending in the first direction and second scribe lines extending in the second direction.

According to one example, before forming the opaque resin layer, the step of wet etching the semiconductor wafer on which the plurality of first trenches are formed may be further included.

According to another example, the plurality of second trenches may be formed using a half cut process.

According to another example, a plurality of extending in the first direction, spaced apart in the second direction, and having a width greater than the width of the first trench are provided on the first surface of the semiconductor wafer between the plurality of first trenches. The method may further include forming a third trench. The opaque resin layer may be buried in the plurality of first trenches and the plurality of third trenches. The first scribe lines may be located on the opaque resin layer buried in the plurality of third trenches, and the second scribe lines may be located on the electrode layer buried in the plurality of second trenches.

The photoconductive semiconductor switch according to an embodiment of the present invention has a periodically arranged pin structure, thereby physically separating current paths between electrodes. Accordingly, current filamentation can be suppressed by physically separating the current path into a plurality of pin structures. Even if current filamentation occurs on the semiconductor substrate, the durability of the photoconductive semiconductor switch can be improved by preventing excessive energy from being concentrated at one point by dispersing it in a plurality of fin structures.

By embedding opaque epoxy between the fin structures, the current filaments can be physically separated more completely by preventing the laser beam that triggers the photoconductive semiconductor switch from hitting the bottom of the trench.

According to the method of manufacturing a photoconductive semiconductor switch according to an embodiment of the present invention, a fin structure is formed by periodically forming trenches through a half-cut process, and the manufacturing time and manufacturing cost of the photoconductive semiconductor switch can be reduced.

Figure 1 shows a perspective view of a conventional photoconductive semiconductor switch.
Figure 2 shows a perspective view of a photoconductive semiconductor switch according to an embodiment of the present invention.
FIGS. 3 to 5 are cross-sectional views of a photoconductive semiconductor switch according to an embodiment of the present invention. FIG. 3 is a cross-sectional view taken along the cutting line III-III of FIG. 2, and FIG. 4 is a cross-sectional view taken along the cutting line Ⅵ-VI of FIG. 2. It is a cross-sectional view cut along, and FIG. 5 is a cross-sectional view cut along the cutting line V-V of FIG. 2.
6A and 6B to 11 are plan and cross-sectional views for explaining a method of manufacturing a photoconductive semiconductor switch according to an embodiment of the present invention.

Below, with reference to the attached drawings, various embodiments will be described in detail so that those skilled in the art can easily implement the technical idea of the present disclosure. However, since the technical idea of the present disclosure can be modified and implemented in various forms, it is not limited to the embodiments described in this specification. In describing the embodiments disclosed in this specification, if it is determined that detailed description of related known technologies may obscure the gist of the technical idea of the present disclosure, detailed descriptions of the known technologies will be omitted. Identical or similar components will be assigned the same reference number and duplicate descriptions thereof will be omitted.

The terms used in this specification are solely for describing specific embodiments, and are not intended to limit the present invention to the dictionary meaning of the terms. In this specification, when an element is described as being "connected" to another element, this includes not only the case of being "directly connected" but also the case of being "indirectly connected" with another element in between. When an element is said to “include” another element, this means that it does not exclude another element in addition to the other element, but may further include another element, unless specifically stated to the contrary.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

Figure 2 shows a perspective view of a photoconductive semiconductor switch according to an embodiment of the present invention. FIGS. 3 to 5 are cross-sectional views of a photoconductive semiconductor switch according to an embodiment of the present invention. FIG. 3 is a cross-sectional view taken along the cutting line III-III of FIG. 2, and FIG. 4 is a cross-sectional view taken along the cutting line Ⅵ-VI of FIG. 2. It is a cross-sectional view cut along, and FIG. 5 is a cross-sectional view cut along the cutting line V-V of FIG. 2.

2 to 5, the photoconductive semiconductor switch 100 includes a semiconductor substrate 110 having fin structures 110f thereon, a pair of electrodes 120 and 130, and an opaque resin layer. Includes (140).

The semiconductor substrate 110 may include a group III-V semiconductor material. For example, the semiconductor substrate 110 may include gallium arsenide (GaAs) or indium phosphide (InP). The semiconductor substrate 110 may be a GaAs substrate. The semiconductor substrate 110 may have a (dark resistivity) of about 10 ⁷ Ω·cm and a carrier mobility of about 5 to 8,000 cm ² /V·s.

Both ends of the semiconductor substrate 110 in the first direction may have electrode arrangement areas where a pair of electrodes 120 and 130 are disposed. The semiconductor substrate 110 has fin arrangement regions in which fin structures 110f are disposed between the electrode arrangement regions. The thickness of the electrode placement areas may be thinner than the thickness of the pin placement areas.

A pair of electrodes 120 and 130 are disposed on electrode arrangement areas at both ends of the semiconductor substrate 110 in the first direction D1. A pair of electrodes 120 and 130 may include a gold (Au)-based alloy material. According to one embodiment, the pair of electrodes 120 and 130 may be formed by sequentially stacking germanium (Ge), gold (Au), nickel (Ni), and gold (Au) and then annealing them. According to another embodiment, the pair of electrodes 120 and 130 may be formed by sequentially stacking germanium (Ge), nickel (Ni), and gold (Au) and then annealing them. A pair of electrodes 120 and 130 may form an ohmic contact with the semiconductor substrate 100 through an annealing process.

According to one embodiment, the top surface of the pair of electrodes 120 and 130 may be at the same level as the top surface of the semiconductor substrate 100. According to another embodiment, the top surface of the pair of electrodes 120 and 130 may be lower than the top surface of the semiconductor substrate 100.

According to one embodiment, the back surface of the pair of electrodes 120 and 130 may be at the same level as the back surface of the opaque resin layer 140. According to another embodiment, the back surface of the pair of electrodes 120 and 130 may be higher than the back surface of the opaque resin layer 140.

The fin structures 110f may extend in the first direction D1 between the pair of electrodes 120 and 130 and may be arranged to be spaced apart in the second direction D2. The fin structures 110f may be partition walls between trenches TR that extend in the first direction D1 and are spaced apart in the second direction D2. 2 and 3, the number of fin structures 110f is shown as nine, but this is by way of example only and there may be fewer or more than nine.

According to one embodiment, the fin structures 110f may be integrated with the semiconductor substrate 110. For example, the fin structures 110f may be formed by forming trenches TR in the flat semiconductor substrate 110 . A current path between a pair of electrodes 120 and 130 is formed in physically separated fin structures 110f. Therefore, the current paths are physically separated, and even if a filamentation phenomenon occurs, the filamentation phenomenon occurs due to a relatively small current.

Both ends of the fin structures 110f may be electrically connected to a pair of electrodes 120 and 130, respectively. Both ends of the fin structures 110f may be in direct contact with a pair of electrodes 120 and 130, respectively.

According to one embodiment, the thickness of the fin structures 110f may be equal to the width of the trench TR. Both the thickness of the fin structures 110f and the width of the trench TR may be approximately 20 μm.

According to another example, the thickness of the fin structures 110f may be thinner than the width of the trench TR. By reducing the thickness of the fin structures 110f and increasing the number of fin structures 110f, the possibility of a filamentation phenomenon occurring can be further reduced.

According to another example, the thickness of the fin structures 110f may be thicker than the width of the trench TR. By ensuring that the fin structures 110f have a stable thickness, a structurally stable photoconductive semiconductor switch 100 can be manufactured.

The thickness of the fin structures 110f and the width of the trench TR are defined as dimensions in the second direction D2. The thickness of the fin structures 110f and the width of the trench TR may vary depending on the shape of the incident light source.

The height of the fin structures 110f may be about 50 μm. The height of the fin structures 110f is defined as the dimension in the third direction D3 from the bottom surface of the trench TR to the top surface of the fin structures 110f.

The opaque resin layer 140 is buried in the trenches TR between the fin structures 110f. The opaque resin layer 140 may include epoxy. The opaque resin layer 140 may be formed of a low-viscosity insulating resin. The opaque resin layer 140 can suppress discharge phenomena around the electrodes 120 and 130 and improve insulation performance between channel regions formed in the fin structures 110f.

According to one embodiment, the opaque resin layer 140 may be opaque to visible light. The opaque resin layer 140 may block a laser beam having a wavelength between 700 nm and 1000 nm from reaching the bottom surface of the trenches TR. The opaque resin layer 140 can block a laser beam with a wavelength of 825 nm. The opaque resin layer 140 suppresses photoelectric phenomena from occurring on the bottom surfaces of the trenches TR due to light incident on the photoconductive semiconductor switch 100, so that the channel regions formed in the fin structures 110f It can improve electrical separation between livers.

Since the pair of electrodes 120 and 130 is embedded in the semiconductor substrate 110, side ends of the fin structures 110f may directly contact the pair of electrodes 120 and 130. When voltage is applied to the pair of electrodes 120 and 130 and light is incident on the photoconductive semiconductor switch 100, the current filament is not only distributed into the fin structures 110f but also along the thickness direction of the semiconductor substrate 110. It can also be distributed. Accordingly, the current filamentation phenomenon that occurs at the boundary between the pair of electrodes 120 and 130 and the semiconductor substrate 110 can be reduced, and the lifespan of the photoconductive semiconductor switch 100 can be improved.

6A and 6B to 11 are plan and cross-sectional views for explaining a method of manufacturing the photoconductive semiconductor switch 100 according to an embodiment of the present invention.

Referring to FIGS. 6A and 6B , first trenches TRa may be formed on the first surface of the semiconductor wafer 210, extending in the first direction D1 and spaced apart in the second direction D2. The first trenches TRa may be periodically arranged along the second direction D2. The first trenches TRa may have the same width. The first trenches TRa may be formed throughout the semiconductor wafer 210 in the first direction D1 as shown in FIG. 6A.

According to one embodiment, the first trenches TRa may be formed through a half cut process using wafer dicing saw equipment. According to another embodiment, the first trenches TRa may be formed using a dry etching process using a reactive ion etcher (RIE), or a wet etching process using an ammonia-hydrogen peroxide mixture.

According to one embodiment, third trenches TRc extending in the first direction D1 and spaced apart in the second direction D2 may be formed on the first surface of the semiconductor wafer 210. The third trenches TRc may have the same width and may have a greater width than the first trenches TRa. A scribe line for dicing the semiconductor wafer 210 into a plurality of photoconductive semiconductor switches (100 in FIG. 2) may be located on the third trenches TRc.

According to one embodiment, the third trenches TRc may be formed by performing a half cut process using wafer dicing saw equipment overlapping several times. According to another embodiment, the third trenches TRc may be formed at once through a dry etching process.

According to one embodiment, to prevent the fin structures 210f' between the first trenches TRa and between the first trench TRa and the third trench TRc from collapsing during the half cut process, Before the half cut process, the entire surface of the semiconductor wafer 210 may be coated with photoresist or a similar resin.

Referring to FIGS. 7A and 7B , the semiconductor wafer (210 in FIGS. 6A and 6B ) on which the first trenches (TRa) and the third trenches (TRc) are formed is wet etched to form a space between the first trenches (TRa). , and the thickness of the fin structures 210f' between the first trench TRa and the third trench TRc may be reduced. In addition, the side and bottom surfaces of the first trenches (TRa) and the third trenches (TRc) are rough immediately after performing a half cut process using a wafer dicing saw equipment, but the wet It can be flattened by etching.

After the wet etching process of FIGS. 7A and 7B , the semiconductor wafer 210 has first and third trenches TRa' and TRc' of increased width and fin structures 210f of reduced thickness. The wet etching process of FIGS. 7A and 7B may be omitted.

Referring to FIGS. 8A and 8B , by applying an opaque resin material on the semiconductor wafer 210 in which the first and third trenches TRa' and TRc' are formed, the first and third trenches TRa' and TRc' are formed. An opaque resin layer 240 embedded in TRc') is formed.

According to one embodiment, after applying an opaque resin material on the semiconductor wafer 210, a full-face polishing process may be performed until the first and third trenches TRa' and TRc' are exposed. A cleaning process may be performed after the polishing process. Residues can also be removed through processes such as oxygen ashing.

Referring to FIG. 9, the opaque resin layer 240 is buried in the first and third trenches TRa' and TRc' and extends in the second direction D2 on the first surface of the semiconductor wafer 210. Second trenches TRb may be formed spaced apart in one direction D1. The first direction D1 and the second direction D2 may be perpendicular to each other. The second trenches TRb may be formed periodically in the first direction D1.

According to one embodiment, the second trenches TRb may be formed through an etching process. For example, the second trenches TRb extending in the second direction may be formed using a dry etching process using a reactive ion etcher (RIE), or a wet etching process using an ammonia-hydrogen peroxide mixture. The depth of the second trenches TRb may be smaller than the depth of the first and third trenches TRa and TRc.

According to another embodiment, the second trenches TRb may be formed through a half cut process. The depth of the second trenches TRb may be substantially the same as the depth of the first and third trenches TRa and TRc.

Referring to FIG. 10 , an electrode layer 250 buried in the second trenches TRb may be formed by depositing an electrode material on the second trenches TRb. According to one embodiment, the electrode layer 250 may be buried in the second trenches TRb by depositing an electrode material using a hard mask that exposes the second trenches TRb. According to another embodiment, after depositing an electrode material on the front surface of the semiconductor wafer 210 in which the second trenches TRb are formed, a polishing process and a cleaning process are performed to form an electrode layer ( 250) can be formed.

After the electrode layer 250 is buried in the second trenches TRb or after depositing the electrode material, an annealing process may be performed so that the electrode layer 250 forms an ohmic contact with the semiconductor wafer 210.

According to one embodiment, the electrode material may be a material in which germanium (Ge), gold (Au), nickel (Ni), and gold (Au) are sequentially stacked. According to another embodiment, the electrode material may be a material in which germanium (Ge), nickel (Ni), and gold (Au) are sequentially stacked.

Referring to FIG. 11, the semiconductor wafer 210 on which the electrode layer 250 is formed is formed by first scribe lines SLa extending in the first direction D1 and second scribe lines extending in the second direction D2. By dicing along (SLb), a plurality of photoconductive semiconductor switches (100 in FIG. 2) can be manufactured.

The first scribe lines SLa may be located on the opaque resin layer 240 buried in the third trenches (TRc in FIG. 6A). The second scribe lines SLb may be located on the electrode layer 250 buried in the second trenches (TRb in FIG. 9). As the semiconductor wafer 210 is diced along the second scribe lines SLb, the electrode layer 250 may be separated into a pair of electrode layers (120 and 130 in FIG. 2).

The various embodiments described in this specification are illustrative and are not intended to be used independently from each other. Embodiments described herein may be implemented in combination with each other.

The scope of the present invention is indicated by the claims described below rather than the detailed description above, and all changes or modified forms derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention. do.

Claims (11)

forming a plurality of first trenches extending in a first direction and spaced apart in a second direction on a first surface of a semiconductor wafer using a half cut process;
forming an opaque resin layer buried in the plurality of first trenches by applying an opaque resin material on the semiconductor wafer in which the plurality of first trenches are formed;
forming a plurality of second trenches extending in the second direction and spaced apart in the first direction on the first surface of the semiconductor wafer where the plurality of first trenches filled with the opaque resin layer are formed;
forming an electrode layer buried in the plurality of second trenches by depositing an electrode material in the plurality of second trenches; and
dicing the semiconductor wafer along first scribe lines extending in the first direction and second scribe lines extending in the second direction to form a photoconductive semiconductor switch. Manufacturing method. In claim 1,
Before forming the opaque resin layer, the method of manufacturing a photoconductive semiconductor switch further includes wet etching the semiconductor wafer on which the plurality of first trenches are formed. In claim 1,
A method of manufacturing a photoconductive semiconductor switch, wherein the plurality of second trenches are formed using a half cut process. In claim 1,
Forming a plurality of third trenches on the first surface of the semiconductor wafer between the plurality of first trenches, extending in the first direction, spaced apart in the second direction, and having a width greater than the width of the first trench. Includes further steps,
The opaque resin layer is buried in the plurality of first trenches and the plurality of third trenches,
The first scribe lines are located on the opaque resin layer buried in the plurality of third trenches,
The method of manufacturing a photoconductive semiconductor switch, wherein the second scribe lines are located on the electrode layer buried in the plurality of second trenches. In claim 1,
The photoconductive semiconductor switch,
semiconductor substrate;
a pair of electrodes disposed on both ends of the semiconductor substrate in a first direction;
pin structures extending in the first direction and arranged to be spaced apart in a second direction between the pair of electrodes; and
A method of manufacturing a photoconductive semiconductor switch, comprising the opaque resin layer embedded between the fin structures on the semiconductor substrate. In claim 5,
A method of manufacturing a photoconductive semiconductor switch, wherein the fin structures are integral with the semiconductor substrate. In claim 5,
A method of manufacturing a photoconductive semiconductor switch, characterized in that both ends of the pin structures are electrically connected to the pair of electrodes, respectively. In claim 5,
A method of manufacturing a photoconductive semiconductor switch, wherein the upper surfaces of the fin structures, the upper surfaces of the pair of electrodes, and the upper surfaces of the opaque resin layer are at the same level. In claim 5,
A method of manufacturing a photoconductive semiconductor switch, characterized in that the thickness of each of the fin structures is thinner than the gap between the fin structures. In claim 1,
A method of manufacturing a photoconductive semiconductor switch, wherein the semiconductor wafer is a gallium arsenide (GaAs) wafer. In claim 1,
A method of manufacturing a photoconductive semiconductor switch, wherein the opaque resin layer blocks a laser beam with a wavelength between 700 nm and 1000 nm.

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