JPH07162022A - Semiconductor photodetector, manufacture thereof and processing of semiconductor - Google Patents

Abstract

PURPOSE:To reduce the capacity of an element and to contrive to improve the frequency characteristics having a small series resistance of the element by providing a region encircled with an element-isolating groove and separated from a diffused region with an electrode-forming groove of a depth to reach a buffer layer and a second main electrode which makes an ohmic contact with the buffer layer in the electrode-forming groove. CONSTITUTION:A first high-doped InP buffer layer 84 of an N-type impurity concentration of 1X10<18> pieces/cm<2>, a second N-type InP buffer layer 86, an N<-> InGaAs optical absorption layer 88 and an N<-> InP window layer 90 are laminated in order on a semiinsulative InP substrate 82. The layer 90 is provided with a diffused region 92 of a P-type impurity such as zinc. The region 92 is provided with an element-isolating loop-shaped groove 100, encircling a P<+> diffused region 92, in a prescribed part. Moreover, a region encircled with the groove 100 and separated from the P<+> region 92 is provided with an electrode- forming groove 102 of a depth to reach the layer 84, so that N side electrode 108 comes into contact with the layer 84.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor processing technique,
In particular, it relates to a method for manufacturing a semiconductor light receiving element.

[0002]

2. Description of the Related Art As a semiconductor light receiving element utilizing the photovoltaic effect of a conventional pn junction diode, for example, a mesa photodiode is known. In this photodiode, the substrate surface is exposed around the light receiving portion and the light receiving portion is formed into a mesa shape, whereby the element capacitance is reduced and the response time is shortened.

By the way, in the mesa type photodiode,
A large step is formed between the mesa-shaped light receiving portion and the surface of the substrate around it. It is not easy to form the wiring electrode over this step. In addition, disconnection of the wiring electrode is likely to occur between the shoulder of the mesa portion and the substrate surface.

Therefore, the inventor of the present application has proposed in Japanese Patent Application No. 4-85783 a semiconductor light receiving element having a structure in which the disconnection of the wiring electrode hardly occurs without increasing the element capacitance. Hereinafter, an example of this semiconductor light receiving element will be briefly described as a first conventional example with reference to the drawings. FIG. 5 is a sectional perspective view for explaining a conventional semiconductor light receiving element.

The semiconductor light receiving element of the first conventional example (hereinafter also referred to as an element) is formed on a substrate 10 of semi-insulating InP with n ⁺ −.
Second buffer layer 14 of InP of the first buffer layer ^12, n-InP, n - light absorbing layer 16 of -InGaAs, ⁿ has a p-type diffusion region 18 in a part - -InP of the window layer 2
0s are sequentially formed.

A p-side electrode 22 is provided on a predetermined portion of the p-type diffusion region 18, and a p-side electrode 22 is provided on a predetermined region of the window layer away from the p-type diffusion region 18 via an insulating film 24. Side wiring electrodes 26 are provided. Further, an n-side electrode 32 is provided on a part of the window layer 20,
An n-side wiring electrode 34 is provided on the n-side electrode 32. The insulating film 24 portion on the p-type diffusion region 18 also serves as the antireflection film 36 of the light receiving portion.

The element isolation groove 28 is formed in a closed loop shape in a plane pattern with a depth reaching the InP substrate 10 from the surface of the window layer 20. p
The side wiring electrode 26 becomes the space wiring 30 and the p-side electrode 22.
Connected with. The element separation groove 28 electrically separates the inner part and the outer part of the closed loop. As a result, the capacitance generated under the p-side wiring electrode 18 can be reduced.

[0008]

However, in the above-described conventional semiconductor light receiving element, since the n-side electrode is formed on the window layer, the contact resistance of the n-side electrode increases. On the other hand, in the case of the mesa type semiconductor light receiving element, the n-side electrode could be formed on the buffer layer exposed around the mesa portion. Therefore, the structure of the conventional semiconductor device described above has a problem in that the series resistance of the device is increased and the frequency characteristics of the device are deteriorated.

Therefore, a first object of the present invention is to provide a semiconductor light receiving element having a small element capacitance, a small series resistance, and excellent frequency characteristics.

Therefore, in the first invention according to this application, in order to reduce the contact resistance, the electrode forming groove is formed so that the tip of the groove reaches the buffer layer on the substrate. As a result, since the element isolation groove and the electrode formation groove having different depths are formed, there is a problem that the manufacturing process of the semiconductor light receiving element becomes complicated.

Therefore, a second object of the present invention is to provide a method for manufacturing a semiconductor light receiving element in which the element separating groove and the electrode forming groove can be formed in one etching step.

A third object of the present invention is to provide a semiconductor processing method capable of forming holes having different depths by a single etching process.

[0013]

In order to achieve the first object of the present invention, according to the semiconductor light receiving element of the first invention, the impurity concentration of the first conductivity type is 5 on the semi-insulating substrate. ×
A stack comprising a buffer layer having a concentration higher than 10 ¹⁷ pieces / cm ² and a light absorption layer, and a window layer provided with a diffusion region for impurities of the second conductivity type, which are sequentially laminated on a predetermined portion of the diffusion region. In a semiconductor light receiving element having a first main electrode, surrounding a diffusion region, and having an element isolation groove having a depth reaching the base, a region surrounded by the element isolation groove and separated from the diffusion region. The region is provided with an electrode forming groove having a depth reaching the buffer layer, and a second main electrode in ohmic contact with the buffer layer in the electrode groove.

In order to achieve the second object of the present invention, according to the method for forming a semiconductor light receiving element of the second invention, the impurity concentration of the first conductivity type is 5 × on the semi-insulating substrate.
A step of sequentially laminating a buffer layer having a concentration higher than 10 ¹⁷ pieces / cm ² , a light absorption layer, and a window layer, and forming a layered body in which a diffusion region of the second conductivity type impurity is provided in the window layer; On the window layer in which the diffusion region is formed, an element isolation opening for forming an element isolation groove surrounding the diffusion region is provided as an etching mask, and is a region surrounded by the element isolation opening. An opening for forming a groove for electrode formation in a region separated from the diffusion region,
The step of forming an etching mask having an electrode opening whose opening is narrower than the element isolation opening, and the laminated body is etched once through the etching mask to obtain a semi-insulating property. A step of simultaneously forming an element isolation groove reaching the substrate and an electrode formation groove reaching the buffer layer, a step of removing an etching mask after etching, an element isolation groove and an electrode formation groove are formed. A step of forming an insulating film on the formed window layer, and etching the insulating film to form an insulating film portion in at least a part of a region on the diffusion layer and an insulating film part in a region including a groove for an electrode. First removing ohmic contact with the diffusion layer
And a step of individually forming a main electrode and a second main electrode which makes ohmic contact with the buffer layer in the electrode groove.

Further, in order to achieve the third object of the present invention, according to the semiconductor processing method of the third invention, the first hole portion having the first depth and the first hole portion are formed in the base of the semiconductor. In forming the second hole having a second depth shallower than the depth of the first hole, the first opening is formed on the first hole formation-scheduled region of the base of the semiconductor, and the second hole is planned to be formed. A step of forming an etching mask having a second opening smaller than the size of the first opening on the region; and etching the base of the semiconductor once through the etching mask to form the first hole. And a second hole portion shallower than the first hole portion are formed at the same time.

[0016]

According to the structure of the semiconductor light receiving element of the first invention,
In addition to the element isolation groove, an electrode formation groove is formed. Whereas the element isolation groove needs to reach the element substrate,
The tip of the groove for electrode formation needs to reach the buffer layer on the substrate. This is because the contact area between the electrode forming groove and the buffer layer is increased to reduce the contact resistance. As a result, it is possible to obtain a semiconductor light receiving element having a small element capacitance and a small series resistance and excellent frequency characteristics.

By the way, in the first invention, the depths of the element isolation trench and the electrode formation trench are different from each other. Therefore, according to the method of manufacturing the semiconductor light receiving element of the second invention, the width of the opening for forming the electrode forming groove is
By making the opening narrower than the opening for forming the element isolation groove, the element isolation groove and the electrode formation groove having a shallower depth than the element isolation groove are simultaneously formed by one etching.

According to the semiconductor processing method of the third aspect of the invention, the fact that the etching rate changes depending on the size of the opening of the etching mask makes it possible to form holes having different depths in one etching step. It can be formed at the same time.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An example of a semiconductor processing method and a semiconductor light receiving element manufacturing method of the present invention will be described below with reference to the drawings. It should be noted that each drawing merely schematically shows the size, shape, and arrangement relationship of each constituent component to the extent that the present invention can be understood. Therefore, it is obvious that the present invention is not limited to this illustrated example.

First Embodiment In a first embodiment, an example of the structure of the semiconductor light receiving element of the present invention will be described. FIG. 1 is a sectional perspective view for explaining the semiconductor light receiving element of the first embodiment.

In this embodiment, 8 on a semi-insulating InP substrate
2, the first buffer layer 8 of high concentration InP (hereinafter, n ⁺ -InP) having an n-type impurity concentration of 1 × 10 ¹⁸ / cm ^2.
4, n-InP second buffer layer 86, n ^-- InGa
A light absorbing layer 88 of As and a window layer 90 of n ⁻ -InP are sequentially laminated. The window layer 90 is provided with a diffusion region (p ⁺ diffusion region) 92 of a p-type impurity such as zinc (Zn) or cadmium (Cd). Hereinafter, the semi-insulating InP substrate 82, the first and second buffer layers 84 and 86, the light absorption layer 88 and the p ⁺ diffusion region 9 will be described.
The window layer 90 provided with 2 is collectively referred to as a laminated body 104. The impurity concentration of the first buffer layer 82 may be 5 × 10 ¹⁷ pieces / cm ² or more in order to reduce the resistance.

A p-side electrode 110 is provided as a first main electrode on a predetermined portion of the diffusion region 92. Further, it has a closed-loop element isolation groove 100 surrounding the p ⁺ diffusion region 92 when viewed in a plan pattern. The element isolation trench 100 is used to electrically insulate the inner and outer regions of the element isolation trench loop from the semi-insulating InP substrate 8.
Has reached 2.

Then, in a region surrounded by the element isolation trench 100 and separated from the p ⁺ diffusion region 92, the first
The electrode forming groove 102 having a depth reaching the buffer layer 84 is provided. In the electrode groove 102, the electrode forming groove 10 is formed.
2, an n-side electrode 108 is provided as a second main electrode in ohmic contact with the first buffer layer 84. In this embodiment, a plurality of electrode forming grooves 102 are provided in order to widen the ohmic contact area between the n-side electrode 108 and the first buffer layer 84. Further, on the n-side electrode 108, the n-side electrode 10
8 is provided with an n-side wiring electrode 112 that makes electrical contact.

On the other hand, an insulating film 106 is provided on the portion of the laminated body 104 where the p-side and n-side electrodes 110 and 108 are not provided and on the element separating groove 100. A p-side wiring electrode 114 that is in electrical contact with the p-side electrode 110 is provided on the insulating film 106. A portion 116 of the p-side wiring electrode 114 on the element isolation groove 100 is formed by a space wiring method. The insulating film portion 116a on the p ⁺ diffusion region 92 also serves as a reflection film.

As described above, in the semiconductor light receiving element of the present invention, the n-side electrode 108 makes ohmic contact with the first buffer layer 84 having a high carrier concentration in the electrode forming groove 102. As a result, for example, in the structure of the conventional example,
The contact resistance of the n-side electrode 108, which was about 10Ω, can be reduced to 1Ω or less. Moreover, since the current path can be formed without the high-resistance layers such as the light absorption layer 88 and the window layer 90, the series resistance of the device can be reduced.

Second Embodiment In a second embodiment, an example of the method of manufacturing the semiconductor light receiving element of the present invention will be described. FIGS. 2A to 2C are sectional process diagrams of the first half used to describe the second embodiment. And (A)-(C) of FIG. 3 are sectional process drawings of the latter half following (C) of FIG.

In the present embodiment, in manufacturing a planar type semiconductor light receiving element, first, on a semi-insulating InP substrate 82, a high concentration InP (n × type impurity concentration of 1 × 10 ¹⁸ / cm ² ) is formed. Hereinafter, the first buffer layer 84 of n ⁺ -InP), the second buffer layer 86 of n-InP, and the n ⁻ -InG
aAs light absorption layer 88, n ^-- InP window layer 90
Are sequentially laminated. The respective layers may be stacked by a crystal growth method such as a metal organic chemical vapor deposition method, a halide vapor phase epitaxy method, and a liquid phase epitaxy method. Next, a diffusion region 92 of p-type impurities such as zinc (Zn) or cadmium (Cd) is provided in the window layer 90. Hereinafter, the substrate, the first and second buffer layers, the light absorption layer, and the window layer provided with the diffusion region are collectively referred to as a laminated body 104. Further, the impurity concentration of the first buffer layer is 5 × in order to reduce the resistance.
The number is 10 ¹⁷ pieces / cm ² or more ((A) of FIG. 2).

Next, an etching mask 94 is formed on the window layer 90 in which the diffusion region 92 is formed by using, for example, SiO ₂ or SiN. This etching mask 94
Has an element isolation opening 96 and an electrode opening 98. The element isolation opening 96 is provided to form an element isolation groove 100 surrounding the diffusion region 92, and its width is 3 to 5 μm. In addition, the electrode forming opening 98 is
It is provided in order to form the electrode formation groove 102 in a region surrounded by the element isolation opening 96 and separated from the diffusion region 92. The width of the electrode opening 98 is 1 to 2 μm.
m, and the width of the element isolation opening 96 is narrower than 3 to 5 μm ((B) of FIG. 2).

Next, the laminated body 104 is etched once through the etching mask 94 to obtain the substrate 8
2, the element isolation trench 100 reaching 2 and the first buffer layer 84
And the electrode forming groove 102 reaching the above are simultaneously formed. Here, RIBE (React using Ar and Cl ₂
Etching is performed by ive Ion Beam Etching). At this time, by increasing the partial pressure of Cl ₂ , the chemical etching effect is strengthened rather than the physical etching effect, and the anisotropy is weakened.
As a result, the etching depth can be controlled by the width of the opening of the etching mask. Further, a plurality of electrode forming grooves 102 may be formed in order to widen the contact area between the first buffer layer 84 and the n-side electrode 108 (FIG. 2).
(C)).

Next, after removing the etching mask 94, an insulating film 106 is formed on the window layer 90 in which the element isolation groove 100 and the electrode formation groove 102 are formed.
The insulating film 106 on the diffusion region 92 also serves as the antireflection film 106a of the light receiving portion of the semiconductor light receiving element ((A) of FIG. 3).

Next, the insulating film 106 is etched to remove a region including the electrode forming groove 102 and at least a part of the insulating film 106 on the diffusion layer 92, and then, the electrode forming groove 102 is formed. An n-side electrode 108 in ohmic contact with the first buffer layer 84 and a p-side electrode 110 in ohmic contact with the diffusion layer 92 are individually formed ((B) of FIG. 3).

Next, the n-side electrode 108 and the p-side electrode 11
N-side wiring electrode 112 and p, which are electrically connected to 0, respectively.
The side wiring electrode 114 is formed. In forming the p-side wiring electrode 114, for example, the element isolation trench 100 is once filled with a resist (not shown), and then the p-side wiring electrode 114 is formed and the resist is removed to form the element isolation trench. The n-side wiring electrode 104 portion on 100 can be used as the space wiring 116 ((C) of FIG. 3).

Third Embodiment In a third embodiment, an example of the semiconductor processing method of the present invention will be described. FIGS. 4A and 4B are cross-sectional process drawings for explaining the third embodiment.

In this embodiment, first, as a base of a semiconductor, a semi-insulating InP substrate 60, an n ⁺ -InP layer 62,
n-InP layer 64, n-InGaAs layer 66, n ^-- I
A laminated body 70 in which the nP layers 68 are sequentially laminated is prepared.

Next, in this laminated body 70, a first hole 72 having a first depth reaching the substrate 60 and a second depth shallower than the first depth reaching the n ⁺ -InP layer 62. To form the second hole portion 74 of the laminated body 70, a first opening portion 76 is formed on the region where the first hole portion 72 is to be formed, and a second hole portion 74 is formed on the region to be formed. An etching mask 80 having a second opening 78 smaller than the size of the first opening 76 is formed ((A) of FIG. 4).

Next, the laminated body 70 is etched once through the etching mask 80, and the first hole 72 having a depth reaching the substrate 60 and the n shallower than the first hole 72 are formed. ^A second hole portion 74 reaching the ⁺ -InP layer 62 is formed at the same time ((B) of FIG. 4).

In the above-mentioned embodiment, the example in which the present invention is formed under the specific conditions has been described, but the present invention can be modified and modified in many ways. For example, in the above-described third embodiment, a laminated body in which an n ⁺ -InP layer or the like is provided on a semi-insulating InP substrate as a base is used, but this is a comparison of the depths of the first and second holes. In order to facilitate the above, in the third invention, it is not necessary to limit the structure of the base to the laminated body of this embodiment.

Further, in the above-mentioned first and second embodiments,
Although the first main electrode of the semiconductor element is the p-side electrode and the second main electrode is the n-side electrode, in these inventions, the first main electrode is the n-side electrode, the second main electrode is the p-side electrode, and the buffer layer is The conductivity type of the light absorption layer and the window layer may be p-type, and n-type impurities may be diffused to form a diffusion region.

[0039]

According to the structure of the semiconductor light receiving element of the first invention, the electrode forming groove is formed in addition to the element separating groove. The groove for element isolation needs to reach the substrate of the element, whereas the groove for electrode formation needs to reach the tip of the buffer layer on the substrate. This is because the contact area between the electrode forming groove and the buffer layer is increased to reduce the contact resistance. As a result, it is possible to obtain a semiconductor light receiving element having a small element capacitance and a small series resistance and excellent frequency characteristics.

By the way, in the first invention, the depths of the element isolation trench and the electrode formation trench are different from each other. Therefore, according to the method of manufacturing the semiconductor light receiving element of the second invention, the width of the opening for forming the electrode forming groove is
By narrowing the opening for forming the element isolation groove, the element isolation groove and the electrode formation groove having a depth shallower than the element isolation groove can be easily formed simultaneously by one etching. be able to.

As a result, it is possible to easily manufacture a high-performance and highly reliable semiconductor light-receiving element having a small element capacitance, a small series resistance, an excellent frequency characteristic.

Further, according to the semiconductor processing method of the third aspect of the invention, the fact that the etching rate changes depending on the size of the opening of the etching mask is utilized to make holes having different depths in one etching step. It can be formed at the same time.

[Brief description of drawings]

FIG. 1 is a partial cross-sectional perspective view of a semiconductor light receiving element according to a first embodiment.

FIG. 2A to FIG. 2C are sectional process diagrams of the first half used to describe the second embodiment.

3A to 3C are cross-sectional process diagrams of the second half following FIG. 2C.

FIG. 4A and FIG. 4B are sectional process drawings for explaining the third embodiment.

FIG. 5 is a sectional perspective view for explaining the structure of a conventional semiconductor light receiving element.

[Explanation of symbols]

10: Substrate 12: First Buffer Layer 14: Second Buffer Layer 16: Light Absorption Layer 18: P-Type Diffusion Region 20: Window Layer 22: P-Side Electrode 24: Insulating Film 26: P-Side Wiring Electrode 28: Element Separation Groove 30: Spatial wiring 32: n-side electrode 34: n-side wiring electrode 60: substrate 62: n ⁺ -InP layer 64: n-InP layer 66: n-InGaAs layer 68: n ^-- InP layer 70: laminated body 72 : 1st hole part 74: 2nd hole part 76: 1st opening part 78: 2nd opening part 80: Etching mask 82: Substrate 84: 1st buffer layer 86: 2nd buffer layer 88: Light absorption layer 90: Window Layer 92: P ⁺ diffusion region 94: Etching mask 96: Element isolation opening 98: Electrode formation groove 100: Element isolation groove 102: Electrode formation groove 104: Laminated body 106: Insulating film 106a: Antireflection film 1 08: n-side electrode 110: p-side electrode 112: n-side wiring electrode 114: p-side wiring electrode 116: spatial wiring

Claims (3)

[Claims] 1. A buffer layer, a light absorbing layer, and a second conductivity type impurity having a first conductivity type impurity concentration of higher than 5 × 10 ¹⁷ pieces / cm ² on a semi-insulating substrate. A laminated body in which window layers having regions are sequentially laminated, a first main electrode is provided on a predetermined portion of the diffusion region, the diffusion region is surrounded, and an element isolation groove having a depth reaching the base is formed. In the semiconductor light receiving device provided, in a region surrounded by the device isolation groove, in a region separated from the diffusion region, an electrode forming groove having a depth reaching the buffer layer, the electrode groove A semiconductor light receiving device comprising a second main electrode in ohmic contact with the buffer layer. 2. A buffer layer, a light absorption layer, and a window layer having a first conductivity type impurity concentration of higher than 5 × 10 ¹⁷ impurities / cm ² are sequentially laminated on a semi-insulating substrate, and the window is formed. A step of forming a laminated body in which a diffusion region of the second conductivity type impurity is provided in a layer, and an element isolation groove surrounding the diffusion region is formed as an etching mask on the window layer in which the diffusion region is formed. An opening for forming an electrode forming groove in a region surrounded by the opening for element isolation and separated from the diffusion region in a region surrounded by the opening for element isolation A step of forming an etching mask having an electrode opening whose opening is narrower than the element isolation opening;
Performing a single etching to simultaneously form the element isolation groove reaching the semi-insulating substrate and the electrode forming groove reaching the buffer layer; and the etching mask after performing the etching. And a step of forming an insulating film on the window layer in which the element separating groove and the electrode forming groove are formed, and etching the insulating film to form a region on the diffusion layer. After removing at least a part of the insulating film portion and an insulating film portion in a region including the electrode groove, a first main electrode that makes ohmic contact with the diffusion layer, and the buffer layer and ohmic contact with the electrode groove. And a step of individually forming a second main electrode in contact with the semiconductor light receiving element. 3. When forming a first hole portion having a first depth and a second hole portion having a second depth shallower than the first depth in a semiconductor underlayer, The first hole is formed on the first hole formation planned region.
Forming an opening, and forming an etching mask having a second opening smaller than the size of the first opening on the second hole formation-scheduled region; A method for processing a semiconductor, comprising: performing a single etching through an etching mask to simultaneously form a first hole and a second hole shallower than the first hole.