JPH11330529A - Semiconductor light receiving device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the manufacture of a semiconductor light receiving device which can cope with an optical transmission system which is high-speed at about 10 Gb/s and is of large capacity and besides which can be manufactured, having a high yield without needing a high level of technique, in the case of a semiconductor light receiving device which receives the light in the band of 1 μm in wavelength and amplifies it. SOLUTION: This manufacture has a process of accumulating the light absorbing layer 12 consisting of one conductivity type of compound semiconductor for generating electrons and positive holes in pairs by absorbing light, on one conductivity type of compound semiconductor substrate 11, a process of a field drop layer consisting of one conductivity type of compound semiconductor doped with impurities in higher concentration than the light absorbing layer 12 on the light absorbing layer 12, and a process of accumulating a doubling layer 15 consisting of an opposite conductivity type of compound semiconductor doped with impurities lower in concentration than the field drop layer 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor light receiving device and a method of manufacturing the same, and more particularly, to an APD (Avalanche Photo Diode) for receiving and multiplying light in a wavelength of 1 .mu.m.
) And a method for producing the same.

[0002]

2. Description of the Related Art In recent years, optical communication technology using so-called 1 .mu.m band light having a wavelength of 1.3, 1.55 .mu.m has become an important basic technology that supports today's advanced information society. Indispensable optical elements for the development of this technology are a high-performance laser as an oscillator and a light-receiving element capable of responding with high sensitivity and high speed as a receiver.

[0003] Among these, the APD as a light receiving element is expected to be a receiver capable of a high sensitivity and a high speed response because the element itself has an amplifying function, and can be applied to a next-generation 10 Gb / s large-capacity optical communication system. Is considered to be an element. 1 μm band APD is InGaAs lattice-matched to InP
Alternatively, a structure in which InGaAsP is used as a light absorbing layer and InP is used as a multiplication region is used. A high electric field required for avalanche multiplication is realized by forming a pn junction in the multiplication region and applying a reverse bias.

At the beginning of research and development, a structure was proposed in which a pn junction was provided in an InGaAs layer and the light absorption layer and the multiplication region were both InGaAs. However, good multiplication characteristics could not be achieved with InGaAs. Therefore, only APDs having a heterostructure in which InP / InGaAs (P) are stacked survive at present.
The point of improving the performance of this structure is to set the electric field value Eh at the heterojunction interface in a narrow range so that no multiplication occurs in the light absorbing layer and the carriers generated in the light absorbing layer run at high speed. That is, an electric field value is set between an upper limit that does not cause multiplication and a lower limit for causing the carrier to travel at a high speed, and an electric field value in the vicinity of a pn junction in order to realize good multiplication characteristics within the multiplication region. Is precisely controlled to a predetermined value.

[0005] In addition to balancing these two points,
In terms of manufacturing technology, it is important that
It becomes important. With the structure proposed so far,
Of APD capable of satisfying both, and this structure
FIG. 6 shows the electric field distribution at the time of applying the reverse bias. Figure
6, the n-type impurity concentration is 2 × 10¹⁸/
cm^ThreeContaining n ⁺-Compound semiconductor group consisting of InP
An n-type impurity concentration of 3 × 10^Fifteen/ Cm ^ThreeContains
Light absorption layer 2 made of an InGaAs film having a thickness (d) of 1 μm
And multiplication regions 4 to 6 made of InP are laminated.
You.

Further, between the light absorbing layer 2 and the electric field dropping layers 4 in the multiplication regions 4 to 6, n
Containing a type impurity concentration of 3 × 10 ¹⁵ / cm ^3, and a film thickness of 0.
The composition gradient layer 3 made of 2 μm InGaAsP is interposed. The multiplication regions 4 to 6 are composed of three compound semiconductor layers and have an n-type impurity concentration of 7 × 10
^An electric field drop layer 4 of n ⁺ -InP having a film thickness of 50 nm and containing ¹⁷ / cm ³ and an n-type impurity concentration of 3 × 10 ¹⁵ / c
Multiplier layer 5 of 200 nm thick n ⁺ -InP containing m ³ and contact of 1.3 μm thick p ⁺ -InP containing p-type impurity concentration of 1 × 10 ¹⁸ / cm ³ Layer 6 is formed.

The contact layer 6 is formed in contact with the multiplication layer 5 by diffusing a high-concentration p-type impurity into the n ⁻ -InP layer, and forms a pn junction with the multiplication layer 5. Further, the contact layer 6 functions as a high-concentration layer for connecting electrodes. The electric field distribution when a reverse bias is applied in this structure is shown in the right diagram of FIG. The maximum electric field value Emax is determined by the thickness of the multiplication layer 5. Further, the hetero electric field value Eh is Ema
It is a value obtained by subtracting the electric field drop determined by the n-type impurity concentration and the film thickness of the electric field lowering layer 4 from x. The allowable range of the hetero electric field value Eh is 0.5 ± 0.1 × 10 ⁵ V / cm. When the film thickness of the multiplication layer 5 is 200 nm, the maximum electric field value Emax is 5.7 × 10 ⁵ V / cm.

[0008]

By the way, in this structure, a pn junction is formed by diffusion of an impurity.
There is a problem that the position of the pn junction is likely to fluctuate, and it is difficult to control the thickness of the multiplication layer 5 with good reproducibility as designed. That is, as the pn junction position approaches the hetero interface, the multiplication layer 5 becomes thinner, and the maximum electric field value Emax increases. Conversely, p
When the n-junction position is farther from the hetero interface, the film thickness of the multiplication layer 5 increases, and the maximum electric field value Emax decreases.

As described above, the pn junction is usually formed by diffusion of a p-type impurity. Therefore, when the contact layer 6 having a high p-type impurity concentration is formed in contact with the multiplication layer 5 having a low carrier concentration, The range in which the pn junction position can be controlled is considerably large at ± 0.1 to 0.05 μm or more. this is,
In addition to the fact that the diffusion process itself is fluctuated under the influence of the surface state, the p-type impurity easily moves in the crystal, so that the distribution of the p-type impurity does not become steep and there is a region where the distribution changes slowly. This is because the distribution fluctuates.

As a result, the range of the thickness of the multiplication layer 5 is 0.2
The variation of Emax exceeds the allowable range of variation of Eh of ± 0.1 × 10 ⁵ V / cm. Therefore, at a high yield, 10 Gb / s
However, there is a problem that a high-performance APD applicable to a large-capacity optical communication system cannot be manufactured. The present invention has been made in view of the problems of the related art, and can be applied to a high-speed and large-capacity optical communication system of about 10 Gb / s and does not require advanced technology. It is an object of the present invention to provide a semiconductor light receiving device that can be manufactured with a high yield and a manufacturing method thereof.

[0011]

Means for Solving the Problems In order to solve the above problems, the invention according to claim 1 relates to a method for manufacturing a semiconductor light receiving device, wherein light is absorbed on a compound semiconductor substrate of one conductivity type by absorbing light. Depositing a light-absorbing layer made of a compound semiconductor of one conductivity type that generates a pair of holes, and, on the light-absorbing layer, a compound semiconductor of one conductivity type doped with an impurity at a higher concentration than the light-absorbing layer. Depositing an electric field lowering layer, and doping, on the electric field lowering layer, an impurity having a lower concentration than the electric field lowering layer to multiply electrons or holes (carriers) generated by the light by an avalanche effect. Depositing a multiplication layer made of a compound semiconductor of the opposite conductivity type.

According to a second aspect of the present invention, there is provided the method for manufacturing a semiconductor light receiving device according to the first aspect, wherein the one conductivity type is an n-type and the opposite conductivity type is a p-type. I have. The invention according to claim 3 relates to the method for manufacturing a semiconductor light receiving device according to claim 1 or 2, wherein the material of the light absorbing layer is InGaAs or InGaAs substantially lattice-matched with InP.
P, and the material of the electric field drop layer and the multiplication layer is In.
P.

According to a fourth aspect of the present invention, there is provided a semiconductor light receiving device, comprising: a one-conductivity type compound semiconductor formed on a one-conductivity type compound semiconductor substrate, which absorbs light to generate an electron-hole pair. A light-absorbing layer formed on the light-absorbing layer, an electric-field-drop layer formed of a one-conductivity-type compound semiconductor doped with an impurity at a higher concentration than the light-absorbing layer, and formed on the electric-field-drop layer. And a multiplication layer made of an opposite conductivity type compound semiconductor doped with an impurity at a lower concentration than the electric field drop layer, wherein the multiplication layer multiplies electrons or holes (carriers) generated by the light by an avalanche effect. It is characterized by:

According to a fifth aspect of the present invention, there is provided the semiconductor light receiving device according to the fourth aspect, wherein a hetero barrier generated between the light absorbing layer and the electric field dropping layer due to a difference in forbidden band width is reduced. A composition gradient layer made of a compound semiconductor of one conductivity type having a lower conductivity than that of the electric field drop layer. The invention according to claim 6 is
6. The method for manufacturing a semiconductor light receiving device according to claim 4, wherein a contact layer made of an opposite conductivity type compound semiconductor having a higher conductivity than the multiplication layer is formed on the multiplication layer. It is characterized by becoming.

According to the present invention, of the layers on both sides of the pn junction formed at the interface between the one conductivity type field drop layer and the opposite conductivity type multiplication layer, the field drop layer has a high impurity concentration, The multiplication layer has a low impurity concentration. For example, when the electric field lowering layer is n-type and the multiplication layer is p-type, the p-type impurity is generally easier to move than the n-type impurity. Therefore, even if the p-type impurity diffuses from the p-type side to the n-type side through the pn junction interface due to a subsequent heat treatment or the like, unlike the conventional case, it does not become so much that the tip surface of the high-concentration electric field drop layer is retreated.

It is relatively easy to adjust the p-type impurity concentration of the p-type layer with high accuracy by using a method of doping during ion implantation or film formation. Therefore, if the multiplication layer of the opposite conductivity type having a low impurity concentration is made sufficiently thick, the maximum electric field value can be determined by the impurity concentration of the multiplication layer. Further, when forming a high-concentration opposite-conductivity-type contact layer in contact with a low-concentration opposite-conductivity-type multiplication layer, the same-conductivity-type layers come into contact with each other. The concentration difference between the multiplication layer and the contact layer is smaller than in the case of contact. For this reason, the variation in the thickness of the low concentration multiplication layer can be further reduced.

As a result, it is possible to form a laminated structure with good reproducibility of the maximum electric field value, which contributes to an improvement in yield. The hetero electric field value Eh is determined by the maximum electric field value and the impurity concentration and thickness of the electric field drop layer. Since the impurity concentration and thickness of the electric field lowering layer can be formed with relatively good reproducibility, the hetero electric field value Eh can be formed with good reproducibility if the maximum electric field value can be formed with good reproducibility.

Further, the contact layer and the multiplication layer of the opposite conductivity type are partially formed on the electric field drop layer of the one conductivity type, and are formed around the contact layer and the multiplication layer and on the electric field drop layer.
A first guard ring layer made of an opposite conductivity type compound semiconductor having the same or lower conductivity than the multiplication layer is formed so as to be in contact with the contact layer and the multiplication layer.

That is, the pn junction formed at the interface between the electric field drop layer and the first guard ring layer is disposed around the pn junction formed at the interface between the electric field drop layer and the multiplication layer. Become. By the way, when the pn junction formed at the interface between the electric field drop layer and the multiplication layer is exposed, the exposed surface may be affected from the outside and the breakdown voltage may be reduced.
The pn junction related to the multiplication layer is the p-type junction related to the first guard ring layer.
The first guard ring layer is protected by the n-junction, and the thickness in the thickness direction of the first guard ring layer is larger than the thickness of the multiplication layer, and has the same or smaller conductivity as the multiplication layer. .

Therefore, the pn of the first guard ring layer
The withstand voltage of the junction is higher than the withstand voltage of the pn junction relating to the multiplication layer. If the difference in breakdown voltage is sufficiently secured, the pn junction related to the first guard ring layer is exposed. Therefore, even if the breakdown voltage of the pn junction related to the first guard ring layer is slightly reduced, the entire device is multiplied. It has a withstand voltage that is physically determined by the thickness of the layer.

In addition, a second guard ring layer of one conductivity type having the same or lower conductivity than the first guard ring layer is formed around the outer periphery of the first guard ring layer of the opposite conductivity type. Have been. That is, the pn junction formed at the interface between the electric field drop layer and the first guard ring layer is covered by the second guard ring layer of the same conductivity type as the electric field drop layer.

In this case, a pn junction formed at the interface between the first guard ring layer and the second guard ring layer is exposed on the element surface. Since the pn junction related to the guard ring layer is shielded from the external atmosphere, the withstand voltage can be further improved as compared with the case where the second guard ring layer is not provided.

[0023]

Next, an embodiment of the present invention will be described with reference to the drawings. (First Embodiment) FIG. 1 is a cross-sectional view showing a configuration of a semiconductor light receiving device according to a first embodiment of the present invention. 1 is a graph showing an electric field distribution when a reverse bias is applied.

As shown in the left diagram of FIG. 1, n ⁺ -InP
A light absorption layer 12 made of InGaAs or InGaAsP having a thickness (d) of 1 μm and containing an n-type impurity having a concentration of 3 × 10 ¹⁵ / cm ³ , which is substantially lattice-matched with InP, on a compound semiconductor substrate 11 made of A composition gradient layer 13 made of InGaAsP having a thickness of 200 nm and containing an n-type impurity having a concentration of 3 × 10 ¹⁵ / cm ³ , and a 50 nm-thick InP containing an n-type impurity having a concentration of 7 × 10 ¹⁷ / cm ^3. Field drop layer 1 consisting of
4 and a multiplication layer 15 made of InP and having a thickness of 1.5 μm and containing a p-type impurity having a concentration of 6 × 10 ¹⁶ / cm ³ are stacked in this order. Further, on the multiplication layer 15, an insulating film 16 and an electrode 18 for applying a negative voltage, which is in contact with the multiplication layer 15 through the opening 17 of the insulating film 16, are formed. On the compound semiconductor substrate 1 side, an electrode 19 for applying a positive voltage is formed.

The composition gradient layer 13 has the composition of the light absorbing layer 1.
From 2 to the electric field drop layer 14, the hetero barrier is alleviated. Next, a method for creating the above structure will be described. That is, from the light absorption layer 12 to the multiplication layer 1
Deposit up to 5 continuously using metal organic chemical vapor deposition (MOVPE). Using silicon (Si) and cadmium (Cd) as an n-type impurity and a p-type impurity, respectively.
In both cases, these layers 12 to
Doping during 15.

The conditions such as the impurity concentration and the film thickness of each layer are set so that the maximum electric field value Emax is 5.7 × 10 ⁵ V / cm and the hetero electric field value Eh is 0.5 × 10 ⁵ V / cm. doing. These electric field values can correspond to 10 Gb / s. Actually, it was confirmed that the reproducibility and uniformity of the concentration control were within ± 3% in the doping of the p-type impurity and the n-type impurity by the MOVPE method.

Further, of the layers on both sides of the pn junction,
On the n-type side, the electric field drop layer 14 having a high impurity concentration is used.
The mold side is a multiplication layer 15 having a low impurity concentration. For this reason, unlike the conventional case, even if the p-type impurity diffuses from the p-type side to the n-type side through the pn junction interface, the p-type impurity is not so much as to retreat the tip surface of the high-concentration electric field drop layer 14. Therefore,
As described below, it is sufficiently possible to control the electric field distribution so as to fall within a design range capable of supporting 10 Gb / s.

That is, the variation of the electric field distribution can be observed through the variation of the avalanche breakdown voltage Vb. For the variation of the electric field distribution of ± 0.1 × 10 ⁵ V / cm, Vb is calculated to be 30.4. ± 2V. Actually, a mesa structure was formed on 10 wafers having a diameter of 2 inches for element separation and the reproducibility and uniformity of Vb were evaluated.
It was confirmed that it was within the range of 0.2 ± 3 V, and a high value of about 70% was obtained as the wafer yield. In contrast, FIG.
In the conventional structure shown in the left figure, the wafer yield is about 10%
Thus, the yield was significantly improved by the structure of the present invention.

In the structure shown in the first embodiment,
Although it was confirmed that the electric field distribution corresponding to 10 Gb / s can be controlled stably, it was confirmed that the electric field distribution was actually 10 Gb / s.
It cannot be made to correspond to. because,
This is because, in this structure, the depletion layer extends about 0.8 μm into the multiplication layer 15 made of p-InP, so that the traveling distance of carriers becomes longer.

In order to actually make the structure correspond to 10 Gb / s, it is necessary to make the thickness of the multiplication layer 15 thinner.
This aspect will be described with reference to the following second embodiment. (Second Embodiment) The left drawing of FIG. 2 is a cross-sectional view showing a configuration of a semiconductor light receiving device according to a second embodiment of the present invention. The right diagram of FIG. 2 is a diagram showing an electric field distribution when a reverse bias is applied in the structure of the left diagram.

The difference from the first embodiment is that p-
In contact with the multiplication layer 21 made of InP, a higher concentration p
Type impurity concentration of 2 × 10 ¹⁸ / cm ³ and a film thickness of 1.2
That is, a contact layer 22 made of p ⁺ -InP having a thickness of μm is provided. Further, the thickness of the multiplication layer 21 is set to 0.3 μm.
By making it as thin as m, the traveling distance of the carrier is shortened, and a structure capable of responding to high-speed response is provided. Note that the contact layer 22 also contributes to lowering the resistance during electrode formation. Note that, in FIG. 2, components denoted by the same reference numerals as those in FIG. 1 indicate the same components as those in FIG.

Each of the layers 11 to 14, 21, and 22 is deposited by the MOVPE method as in the first embodiment.
In the structure of FIG. 1 of the first embodiment, the cutoff frequency fc at the time of low multiplication was 7 GHz, whereas in the second embodiment, fc = 9 GHz was obtained. It can be said that the effect of forming the contact layer 22 made of p ⁺ -InP and reducing the thickness of the multiplication layer 21 made of p-InP is sufficiently exhibited.

(Third Embodiment) In the first and second embodiments, the guard ring is not particularly mentioned. However, a guard ring is required when an element is actually formed. By providing the guard ring, it is possible to realize excellent reliability and uniform multiplication at the light receiving unit.

FIG. 3 is a configuration diagram of a semiconductor light receiving device according to a third embodiment of the present invention. In the third embodiment, as shown in FIG. 3, unlike the first and second embodiments, the third embodiment has a guard ring layer 21b. in this case,
Among the layers formed on the compound semiconductor substrate 11, n ⁺ −
The layer structure up to the electric field drop layer 14 made of InP is the same as in the first and second embodiments.

As shown in FIG. 3, after the same multi-layer structure as that of FIG. 1 is formed up to the multiplication layer 15, the high concentration p-type impurity 2 × 10 ¹⁸ / p in the multiplication layer 21a in the region to become the light receiving portion. cm ³
The contact layer 22a made of InP containing is selectively formed. The contact layer 22a has a light receiving diameter φ of 30 μm.
m, and the thickness is 1.2 μm. The multiplication layer 21a
As in the second embodiment, the p-type impurity concentration is 6 × 1
0 ¹⁶ / cm ³ and a film thickness (d) of 0.3 μm.

Next, a method of creating the structure shown in FIG. 3 will be described. First, as in FIG. 1 of the first embodiment, compound semiconductor layers 11 to 1 are formed on a compound semiconductor substrate 11.
5 is formed. Next, a multiplication layer 21 in a region to be a light receiving section
A high concentration p-type impurity of 2 × 10 ¹⁸ / cm ³ is selectively diffused into a to form a p ⁺ -type contact layer 22a. Although the controllability of diffusion for forming the contact layer 22a is not good, Emax is determined by the p-type impurity concentration of the multiplication layer, and thus is not affected by the diffusion for forming the contact layer 22a. .

Thereafter, for isolation between elements, the multiplication layer 15 is etched to leave a portion outside the contact layer 22a and to become the guard ring layer 21b, thereby forming a mesa structure. Thereby, the contact layer 22a and the multiplication layer 21a
And a guard ring layer 21b made of p-type InP having a conductivity equal to or lower than that of the multiplication layer 21a and in contact with the contact layer 22a and the multiplication layer 21a. Formed.

That is, at the periphery of the pn junction formed at the interface between the electric field drop layer 14 and the multiplication layer 21a, the electric field drop layer 14
A pn junction formed at the interface between the gate ring and the guard ring layer 21b is disposed. By the way, when the pn junction formed at the interface between the electric field drop layer 14 and the multiplication layer 21a is exposed, the exposed surface may be affected from the outside and the breakdown voltage may be reduced. However, in this embodiment, The pn junction of the multiplication layer 21a is protected by the pn junction of the guard ring layer 21b, and the thickness of the guard ring layer 21b in the thickness direction is larger than the thickness of the multiplication layer 21a.
It has a conductivity equal to or less than 1a.

Therefore, the pn of the guard ring layer 21b
The breakdown voltage of the junction is higher than the breakdown voltage of the pn junction related to the multiplication layer 21a. If the breakdown voltage difference is sufficiently ensured, the pn junction of the guard ring layer 21b is exposed. Therefore, even if the breakdown voltage of the pn junction of the guard ring layer 21b is slightly reduced, the thickness of the multiplication layer 21a as a whole element is increased. As a result, it has a withstand voltage that is physically determined.

According to the above structure, the breakdown voltage Vb of the pn junction relating to the multiplication layer 21a of the light receiving section is actually 21.5V. On the other hand, the withstand voltage Vb of the pn junction of the guard ring layer 21b formed so as to surround the periphery is 30.4 V
become. As a result, 8.9 V is obtained as the withstand voltage difference, and a good guard ring structure can be realized. (Fourth Embodiment) Since the multiplication characteristic is defined by the maximum electric field value Emax, the multiplication factor is 10 times larger than that of the third embodiment.
In order to obtain a high multiplication characteristic exceeding
It is necessary to increase the maximum electric field value Emax by increasing the type impurity concentration.

In order to stably produce an element corresponding to a system of 10 Gb / s, a margin for design is required. If possible, the p-type impurity concentration of the multiplication layer is set to 1 × 10 ¹⁷ / cm ³
It is desirable that Therefore, a guard ring layer having a p-type impurity concentration lower than that of the multiplication layer is required. FIG.
FIG. 14 is a configuration diagram of a semiconductor light receiving device according to a fourth embodiment of the present invention. The layer structure and the semiconductor material from the light absorption layer 12 to the electric field drop layer 14 are the same as those of the first to third embodiments.

In FIG. 3 of the third embodiment, assuming that the p-type impurity concentration of the multiplication layer 21a is simply 1 × 10 ¹⁷ / cm ³ , Vb in the light receiving region is 20.2 V, and Vb in the guard ring portion is Becomes 22.6V, and the withstand voltage difference becomes only 2.4V. In order to keep the hetero electric field value Eh within a predetermined range, the n-type impurity concentration of the electric field lowering layer 14 is set to 7.5 × 10 ¹⁷ / c.
there is a need to change to m ^3.

The structure shown in FIG. 4 is designed so that a sufficient withstand voltage difference can be obtained even if the p-type impurity concentration of the multiplication layer 21c is increased. The layer structure of the light receiving portion is in contact with the electric field drop layer 14 and includes a multiplication layer 21c made of p-InP having a p-type impurity concentration of 1 × 10 ¹⁷ / cm ³ and a thickness of 0.3 μm, and a multiplication layer 21c. And a contact layer 22b made of p ⁺ -InP and having a film thickness of 1.2 μm and having a p-type impurity concentration of 2 × 10 ¹⁸ / cm ³ .

On the other hand, the layer structure of the guard ring portion
Is a p-type impurity concentration of 6 × 10¹⁶/ Cm ^ThreeIncluding, the film thickness
It is made of a 1.5 μm p-InP film. Third embodiment
It has the same structure as In this case, Vb = 20.
Vb of guard ring portion is 30.4V with respect to 2V
As a result, 10.2 V is obtained as the breakdown voltage difference. Therefore, withstand pressure
A guard ring structure with a margin for the difference can be realized.

Next, a method for producing this laminated structure will be described below. The crystal growth step is divided into two successive steps. That is, in the first growth, the p-InP film to be the multiplication layer 21c is stacked on the compound semiconductor substrate 11. Thereafter, the p-InP film is mesa-etched, and p-I
The multiplication layer 21c is formed while leaving the nP film.

In the second growth, p-I including the same p-type impurity concentration as the guard ring layer 21b of the third embodiment is lower than the p-type impurity concentration of the multiplication layer 21c over the entire surface.
An nP film is formed. Next, as in the third embodiment, a p-type impurity is selectively diffused in the p-InP film of the light-receiving portion to form ap ⁺ -type contact layer 22b.

Thereafter, as in the third embodiment, the mesa-etching is performed on the guard ring layer 21d outside the contact layer 22b for element isolation. Then, after forming the insulating film 16, the contact hole 17 is formed except for the light receiving region. Subsequently, an electrode 18 that contacts the contact layer 22b and the guard ring layer 21d through the contact hole 17 except for the light receiving region is formed. continue,
An electrode 19 is formed on the substrate 11 side. Thus, the semiconductor light receiving device is completed.

(Fifth Embodiment) In the third and fourth embodiments, mesa etching and passivation for protecting a step portion of the mesa are required for element isolation, and the number of steps is increased. From the viewpoint of simplification of the process, it is desirable to have a planar structure without mesa processing.

The structure shown in FIG. 5 is a planar type having the same layer structure as the third embodiment shown in FIG. The layer configuration up to the electric field lowering layer 14 made of InP is the same as that of the fourth embodiment, and in FIG. 5, components denoted by the same reference numerals as those in FIG. 3 indicate the same components as those in FIG. When the structure according to the fifth embodiment is formed, p-In serving as a multiplication layer is formed.
Rather than doping a p-type impurity during the growth of the P film, a 1.5 μm-thick n ⁻ -InP film serving as a second guard ring layer 21 g is formed in contact with the n ⁺ -InP of the electric field lowering layer. Thereafter, a p-type impurity is selectively introduced into the n ⁻ -InP film by an ion implantation method to form a multiplication layer 21 e made of p-InP and a first guard ring layer 21 f made of p ⁻ -InP. .

In the above case, when the ion implantation is performed to form the multiplication layer 21e, the p-type impurity to be implanted has an atomic radius of 6 × 10 ¹⁶ / cm ³ to a depth of about 1.5 μm. Of beryllium (Be) having a small dose of 5 × 10 ¹³ / cm ² and an acceleration energy of 14
After ion implantation under 0 keV implantation conditions, 700
Heat treatment at 20 ° C. for 20 minutes.

The contact layer 22c is made of Cd by a thermal diffusion method.
Is created by selectively spreading. The multiplication layer 21
e and the contact layer 22c may be formed by any method as long as these regions can be selectively formed. For example, both may be formed by ion implantation.

As described above, according to the fifth embodiment, the conductivity around the outer periphery of the p-type first guard ring layer 21f is equal to or lower than that of the first guard ring layer 21f. An n-type second guard ring layer 21g having the following structure is formed. That is, the pn junction formed at the interface between the electric field drop layer 14 and the first guard ring layer 21f is covered with the same n-type second guard ring layer 21g as the electric field drop layer 14.

In this case, a pn junction formed at the interface between the first guard ring layer 21f and the second guard ring layer 21g is exposed on the element surface. Since the pn junction related to the first guard ring layer 21f is more shielded from the external atmosphere, the withstand voltage can be further improved as compared with the case where the second guard ring layer 21g is not provided.

(Sixth Embodiment) FIG. 6 is a planer type of FIG. 4 of the fourth embodiment. Also in this structure, as in the fifth embodiment, a 1.5 μm-thick n ⁻
-InP is deposited, and then the multiplication layer 21h and the first guard ring layer 21i are formed by selective ion implantation.

Regarding the first guard ring layer 21i,
The ion implantation conditions are the same as in the fifth embodiment. On the other hand, the p-type impurity concentration of the multiplication layer 21h is 1 × 10 ¹⁷ / cm ³
In order to realize the above, only the dose is increased to 8 × 10 ¹³ / cm ² . After the ion implantation, Cd is diffused only in the light receiving portion so that the multiplication layer 21h remains, and a contact layer 22d containing a high concentration of p-type impurities is formed.

The multiplication layer 21h and the contact layer 22
The formation of d may be any method as long as it can selectively create these regions. For example, all may be formed by ion implantation. Also in the above-described sixth embodiment, because of the planar structure, the same functions and effects as those of the fifth embodiment are obtained in addition to the functions and effects of the fourth embodiment.

[0057]

As described above, according to the semiconductor light receiving device of the present invention, by forming the low-concentration opposite-conductivity-type multiplication layer in contact with the high-concentration one-conductivity-type field-drop layer,
The n-junction position is determined by the thickness of the electric field drop layer, and the maximum electric field value Emax can be precisely controlled mainly by adjusting the carrier concentration of the multiplication layer.

As a result, a semiconductor light receiving device that can support a large-capacity high-speed communication system up to 10 Gb / s can be manufactured with a high yield. In addition, by surrounding the multiplication region of the light receiving portion with a guard ring layer of the opposite conductivity type, or further surrounding the guard ring layer of the opposite conductivity type with a guard ring layer of one conductivity type, higher reliability is achieved. A semiconductor light receiving device can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor light receiving device according to a first embodiment of the present invention.

FIG. 2 is a sectional view illustrating a method for manufacturing a semiconductor light receiving device according to a second embodiment of the present invention.

FIG. 3 is a sectional view illustrating a method for manufacturing a semiconductor light receiving device according to a third embodiment of the present invention.

FIG. 4 is a sectional view illustrating a method for manufacturing a semiconductor light receiving device according to a fourth embodiment of the present invention.

FIG. 5 is a sectional view illustrating a method for manufacturing a semiconductor light receiving device according to a fifth embodiment of the present invention.

FIG. 6 is a sectional view illustrating a method for manufacturing a semiconductor light receiving device according to a sixth embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a semiconductor light receiving device according to a conventional example.

[Explanation of symbols]

Reference Signs List 11 compound semiconductor substrate, 12 light absorption layer, 13 composition gradient layer, 14 electric field drop layer, 15, 21, 21 a, 21 c, 21 e, 21 h multiplication layer, 16 insulating film, 17 contact hole, 18, 19 electrode, 21 b, 21d guard ring, 21f, 21i first guard ring, 21g, 21j second guard ring, 22, 22a to 22d contact layer.

Claims (6)

[Claims] 1. A step of depositing a light absorbing layer made of a compound semiconductor of one conductivity type that absorbs light and generates an electron-hole pair on a compound semiconductor substrate of one conductivity type; Depositing an electric field drop layer made of a compound semiconductor of one conductivity type doped with an impurity at a higher concentration than the light absorbing layer; and forming electrons or holes generated by the light on the electric field drop layer. Depositing a multiplication layer made of an opposite conductivity type compound semiconductor doped with an impurity at a lower concentration than the electric field drop layer, wherein the multiplication layer is multiplied by the avalanche effect. Production method. 2. The method according to claim 1, wherein the one conductivity type is n-type, and the opposite conductivity type is p-type. 3. The material of the light absorbing layer is InGaAs or InGaAsP, which is substantially lattice-matched with InP, and the material of the electric field drop layer and the multiplication layer is InP. 3. The method for manufacturing a semiconductor light receiving device according to item 2. 4. A light-absorbing layer formed on a one-conduction-type compound semiconductor substrate and formed of a one-conduction-type compound semiconductor that absorbs light and generates an electron-hole pair; An electric field drop layer formed of a one-conductivity type compound semiconductor doped with an impurity at a higher concentration than the light absorption layer; and an electron or hole generated by the light formed on the electric field drop layer. And a multiplying layer made of an opposite conductivity type compound semiconductor doped with an impurity at a lower concentration than the electric field lowering layer for multiplying (carrier) by an avalanche effect. 5. A one conductivity type compound having a lower conductivity than the electric field drop layer, which alleviates a hetero barrier generated between the light absorption layer and the electric field drop layer due to a difference in band gap therebetween. 5. The semiconductor light receiving device according to claim 4, wherein a composition gradient layer made of a semiconductor is formed. 6. A contact layer comprising a compound semiconductor of the opposite conductivity type having a higher conductivity than that of the multiplication layer is formed on the multiplication layer. A semiconductor light receiving device according to claim 1.