KR102571353B1 - Display Device and Driving Method Thereof - Google Patents

Abstract

A display device of the present invention includes a first sub-pixel group including a pair of sub-pixels disposed adjacent to each other in a horizontal direction and sharing a data line with each other; and a second subpixel group including subpixels not sharing a data line, wherein the first subpixel groups included in the nth (n>1) horizontal line and the second subpixel group included in the n+1th horizontal line 1 sub-pixel groups share different data lines.

Description

Display device and driving method thereof {Display Device and Driving Method Thereof}

The present invention relates to a display device and a method for driving the same.

An active matrix type organic light emitting display device includes organic light emitting diodes (hereinafter, referred to as "light emitting devices") that emit light by itself, and has advantages such as fast response speed, high luminous efficiency, luminance, and viewing angle.

An organic light emitting display device arranges subpixels including light emitting elements in a matrix form, and adjusts the luminance of the subpixels according to the gray level of image data. Each of the subpixels includes a driving TFT (Thin Film Transistor) that controls a driving current input to the light emitting device according to its own gate-source voltage (Vgs). The amount of light emitted from the light emitting element is proportional to the driving current, and the display gray level (luminance) is controlled by the amount of light emitted.

As a method of reducing the number of output channels of a data driving circuit in such a display device, a DRD (Double Rate Driving) driving type panel is known. The DRD panel has an advantage in that the number of data lines and the number of source drive ICs can be reduced to 1/2 compared to conventional ones by time-divisionally supplying data voltages to left and right adjacent subpixels through one data line.

However, in a DRD panel, charging characteristics or light emitting characteristics between R (Red), G (Green), and B (Blue) subpixels may vary depending on how data lines are shared and driven. The difference in characteristics between these sub-pixels causes noise such as horizontal lines, vertical lines, and grid patterns in a display image, thereby deteriorating image quality.

An object of the present invention is to provide a display device capable of preventing deterioration of image quality while reducing the number of output channels of a data driving circuit and a driving method thereof.

In order to solve the above problems, a display device according to an embodiment of the present invention includes a first subpixel group including a pair of subpixels disposed adjacently in a horizontal direction and sharing a data line with each other; and a second subpixel group including subpixels not sharing a data line, wherein the first subpixel groups included in the nth (n>1) horizontal line and the second subpixel group included in the n+1th horizontal line One sub-pixel group includes display panels sharing different data lines.

In the second sub-pixel group, the second sub-pixel groups included in the n-th horizontal line and the second sub-pixel groups included in the n+1-th horizontal line may share different data lines.

In the horizontal line, subpixels are arranged in units of three subpixels including a red (R) subpixel, a green (G) subpixel, and a blue (B) subpixel, and one adjacent one of the three subpixels It is possible that a pair of subpixels is the first subpixel group and the other subpixel is the second subpixel group.

In the nth horizontal line, the red (R) subpixel and the green (G) subpixel share a first data line, the blue (B) subpixel is connected to a second data line, and the n+1th subpixel In a horizontal line, the red (R) subpixel may be connected to the first data line, and the green (G) subpixel and blue (B) subpixel may share the second data line.

a scan driver supplying a scan signal; and a data driver supplying a data voltage to the data line, wherein when the scan signal is input, among the three subpixels included in the nth horizontal line and the three subpixels included in the n+1th horizontal line, Two subpixels are selected, and the data driver may supply corresponding data voltages to a first data line and a second data line respectively connected to the two subpixels to which the scan signal is input.

Among the subpixels included in the first subpixel group of the nth horizontal line and the subpixels included in the first subpixel group of the n+1th horizontal line, a subpixel of the same color is selected in the same scan signal period. A data voltage may be supplied from each corresponding data line.

A subpixel included in the first subpixel group of the nth horizontal line and a subpixel of the same color among the subpixels included in the first subpixel group of the n+1th horizontal line may receive the same scan signal. there is.

When a first scan signal is input, a subpixel connected to the first data line and a subpixel connected to the second data line among the subpixels included in the nth horizontal line are selected and supplied with the corresponding data voltage, and the second scan signal is input. When a signal is input, among the subpixels included in the n+1th horizontal line, a subpixel connected to the first data line and a subpixel connected to the second data line are selected to receive corresponding data voltages, and receive a third scan signal. At the time of input, a subpixel included in the nth horizontal line to which data voltage is not supplied and a subpixel included in the n+1th horizontal line to which data voltage is not supplied are respectively A data voltage may be supplied through the first data line and the second data line that are selected and connected to the corresponding subpixel.

A scan line to which the third scan signal is input may be shared by a subpixel included in the nth horizontal line and a subpixel included in the n+1th horizontal line.

A method of driving a display device according to an embodiment of the present invention includes a data driver supplying data voltages to data lines, a scan driver supplying scan signals to scan lines, and a matrix-type arrangement, wherein the data lines and scan lines are A method of driving a display device including a display panel including connected subpixels, wherein a red (R) subpixel included in an n (n>1) th horizontal line of the display panel when a first scan signal is input, green (G) selecting a subpixel connected to a first data line and a subpixel connected to a second data line among subpixels and blue (B) subpixels and supplying data voltages to each of them; When a second scan signal is input, a subpixel connected to the first data line among red (R) subpixels, green (G) subpixels, and blue (B) subpixels included in the n+1th horizontal line and the second data line selecting subpixels connected to the line and supplying data voltages to each of the subpixels; and when a third scan signal is input, a subpixel included in the nth horizontal line to which data voltage is not supplied and a subpixel included in the n+1th horizontal line to which data voltage is not supplied are selected. and supplying corresponding data voltages through the first data line and the second data line, respectively.

On the horizontal line, subpixels are arranged in units of three subpixels including a red (R) subpixel, a green (G) subpixel, and a blue (B) subpixel, and a data line among the three subpixels is arranged. a first subpixel group including a pair of mutually shared subpixels; and a second subpixel group including subpixels not sharing a data line.

The first subpixel groups included in the nth horizontal line and the first subpixel groups included in the n+1th horizontal line may include display panels sharing different data lines.

A display device and method of driving the same according to the present invention include DRD driving pixels sharing a data line and normal driving pixels not sharing a data line in one display panel, and the DRD driving pixels are the nth line and the n+1 In the second line, different data lines are shared. With this configuration, it is possible to prevent a luminance deviation from occurring between subpixels of the same color. Also, according to an embodiment of the present invention, one of the DRD driving pixels shares one scan line in the n-th line and the n+1-th line. With this configuration, whereas conventionally, 4 scan signals per 2 horizontal lines were required, when the present invention is applied, data can be supplied to 2 horizontal lines within 3 scan signal output periods, and scan signal lines can also be reduced. As a result, the driving frequency may increase, the PPI may increase, and the size of the bezel may decrease.

1 is a schematic block diagram of a display device according to an embodiment of the present invention.
2 is a schematic circuit configuration diagram of a subpixel.
3 is a diagram showing a comparison between a subpixel arrangement of a normal panel and a subpixel arrangement of a double rate driving (DRD) panel.
4 is a diagram showing a sub-pixel arrangement of a display device according to an exemplary embodiment of the present invention.
5 is a diagram showing a pixel array of a display device according to a first embodiment of the present invention.
6 is a driving waveform diagram of the pixel array of FIG. 5 .
7 is a diagram showing a pixel array of a display device according to a second embodiment of the present invention.
8 is a driving waveform diagram of the pixel array of FIG. 7 .
9 to 12 are simulation results of a method of driving a display device according to an exemplary embodiment of the present invention.

Advantages and features of this specification, and methods of achieving them, will become clear with reference to embodiments described below in detail in conjunction with the accompanying drawings. However, this specification is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only these embodiments make the disclosure of this specification complete, and common knowledge in the art to which this specification belongs. It is provided to completely inform the person who has the scope of the invention, and this specification is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of this specification are illustrative, so this specification is not limited to the matters shown. Like reference numbers designate like elements throughout the specification. When 'includes', 'has', 'consists of', etc. mentioned in this specification is used, other parts may be added unless 'only' is used. In the case where a component is expressed in the singular, the case including the plural is included unless otherwise explicitly stated.

In interpreting the components, even if there is no separate explicit description, it is interpreted as including the error range.

In the case of a description of a positional relationship, for example, when the positional relationship of two parts is described as 'on ~', 'upon ~', '~ below', 'next to', etc., 'right' Or, unless 'directly' is used, one or more other parts may be located between the two parts.

Although first, second, etc. may be used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present specification.

Like reference numbers designate substantially like elements throughout the specification.

Hereinafter, embodiments of the present specification will be described in detail with reference to the accompanying drawings. In the following description, if it is determined that a detailed description of a known function or configuration related to the present specification may unnecessarily obscure the gist of the present specification, the detailed description will be omitted.

1 is a schematic block diagram of a display device according to an embodiment of the present invention.

Referring to FIG. 1 , the display device includes an image processor 110, a timing controller 120, a scan driver 130, a data driver 140, a power supply 180, and a display panel 150.

The image processor 110 outputs a data enable signal DE along with the data signal DATA supplied from the outside. The image processor 110 may output one or more of a vertical sync signal, a horizontal sync signal, and a clock signal in addition to the data enable signal DE, but these signals are omitted for convenience of description.

The timing controller 120 receives a data signal DATA along with a data enable signal DE or driving signals including a vertical synchronization signal, a horizontal synchronization signal, and a clock signal from the image processing unit 110 . The timing controller 120 generates a gate timing control signal (GDC) for controlling the operation timing of the scan driver 130 and a data timing control signal (DDC) for controlling the operation timing of the data driver 140 based on the driving signal. outputs

The data driver 140 samples and latches the data signal DATA supplied from the timing controller 120 in response to the data timing control signal DDC supplied from the timing controller 120, and then data based on the gamma reference voltage. Convert to voltage and output. The data driver 140 outputs data voltages through data lines DL1 to DLn. The data driver 140 may be formed in the form of an integrated circuit (IC).

The scan driver 130 outputs a scan signal in response to the gate timing control signal GDC supplied from the timing controller 120 . The scan driver 130 outputs a scan signal composed of a scan high voltage and a scan low voltage through the scan lines GL1 to GLm. The scan driver 130 is formed in the form of an integrated circuit (IC) or formed in the display panel 150 in a gate-in-panel method.

The power supply 180 is connected to the first power line EVDD and the second power line EVSS disposed on the display panel 150 . The power supply unit 180 outputs first potential power (high potential voltage) and second potential power (low potential voltage) through the first power line EVDD and the second power line EVSS. The first potential power (high potential voltage) and the second potential power (low potential voltage) delivered through the first power line EVDD and the second power line EVSS are the subpixels SP of the display panel 150. ) is authorized.

The display panel 150 displays an image corresponding to data voltages and scan signals supplied from the data driver 140 and scan driver 130 and power supplied from the power supply 180 . The display panel 150 includes subpixels SP that operate to display an image.

The subpixels SP include a red (R) subpixel, a green (G) subpixel, and a blue (B) subpixel. The subpixels SP may have one or more different light emitting areas according to light emitting characteristics.

As shown in FIG. 2 , one subpixel includes a switching transistor SW, a driving transistor DR, a capacitor Cst, a compensation circuit CC, and an organic light emitting diode OLED.

The switching transistor SW performs a switching operation so that the data voltage supplied through the first data line DL1 is stored as a data voltage in the capacitor Cst in response to the scan signal supplied through the first scan line GL1. The driving transistor DR operates to allow a driving current to flow between the first power line EVDD and the second power line EVSS according to the data voltage stored in the capacitor Cst. The organic light emitting diode OLED operates to emit light according to a driving current formed by the driving transistor DR.

The compensation circuit CC is a circuit added in the subpixel to compensate for the threshold voltage of the driving transistor DR. The compensation circuit (CC) may be configured in various forms including one or more transistors.

3 is a diagram showing a comparison between a pixel array of a normal panel and a pixel array of a double rate driving (DRD) panel for reducing the number of output channels.

In the normal panel as shown in (A) of FIG. 3, the output channels of the data driving circuit are connected to the data lines DL on a one-to-one basis. Red (R) subpixels, green (G) subpixels, and blue (B) subpixels are arranged along the vertical direction and connected to the data line DL.

In the DRD panel as shown in (B) of FIG. 3 , a pair of subpixels R and G horizontally adjacent to each other with the data line DL interposed therebetween share the data line DL. Accordingly, the number of data lines DL can be reduced. The subpixels R and G sharing the data line DL are charged by receiving the data voltage supplied in a time division manner. As shown in (B) of FIG. 3, when all sub-pixels are driven by DRD in a display panel in which a unit pixel is composed of three sub-pixels: a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel. Luminance deviation may occur between subpixels of the same color. Accordingly, a pair of subpixels R and G are driven by the DRD method and the other subpixel B is driven by the normal method, thereby reducing luminance deviation between subpixels of the same color.

4 is a diagram showing a sub-pixel arrangement of a display device according to an exemplary embodiment of the present invention.

In the display device according to the exemplary embodiment of the present invention, red (R) subpixels, green (G) subpixels, and blue (B) subpixels are arranged in a matrix form. In the following description, a red (R) subpixel will be referred to as an R subpixel, a green (G) subpixel as a G subpixel, and a blue (B) subpixel as a B subpixel. Each of the subpixels are arranged adjacently in the horizontal direction and are divided into a first group that shares a data line and a second group that does not share a data line. The first group includes DRD driving pixels and the second group includes normal driving pixels. Here, in the DRD driving pixel, subpixels of the previous line and subpixels of the next horizontal line share different data lines.

Referring to (a) of FIG. 4 , in the first horizontal line, the R0 subpixel and the G0 subpixel share the first data line DL1 to drive the DRD. And, the remaining B0 subpixels are connected to the second data line DL2 to be normally driven. In the second horizontal line, the R1 subpixel is normally driven, and the G1 subpixel and the B1 subpixel are DRD driven by sharing the second data line DL2. That is, the first data line DL1 is shared on the first horizontal line (n-th line), and the second data line DL2 is shared on the second horizontal line (n+1-th line).

Referring to FIG. 4(b) showing another embodiment, the R0 subpixel in the first horizontal line is a normal driving pixel, and the G0 subpixel and the B0 subpixel share the second data line DL2. In the second line, the R1 subpixel and the G1 subpixel share the first data line DL, and the remaining B0 subpixels are normally driven. That is, the second data line DL2 is shared in the first horizontal line (n-th line), and the first data line DL1 is shared in the second horizontal line (n+1-th line).

As such, the display device according to the embodiment of the present invention includes both DRD driving pixels and normal driving pixels in one panel, and the DRD driving pixels share different data lines in the nth line and the n+1th line. do. With this configuration, it is possible to prevent a luminance deviation from occurring between subpixels of the same color.

FIG. 5 is a diagram showing a pixel array of the display device according to the first embodiment of the present invention, and FIG. 6 is a driving waveform diagram of the pixel array of FIG. 5 .

5 is a circuit diagram showing a part of a pixel array as a first embodiment of the pixel array.

The pixel array includes data lines DL1 to DL2 and scan lines GL1 to GL4 crossing the data lines DL1 to DL2. The sub-pixels R1 to R2, G1 to G2, and B1 to B2 control the connection of the data lines DL1 to DL2 according to the scan signals Scan1 to Scan4 input to the scan lines GL1 to GL4. A first TFT (T1), a second TFT (T2) controlling the connection to the reference (Ref) line, and a third TFT (T3) controlling the connection to the first power line (EVDD) are respectively included.

An R1 subpixel, a G1 subpixel, and a B1 subpixel are arranged on an nth horizontal line (n Line) of the pixel array.

In the R1 sub-pixel, the first TFT T1 has a gate electrode connected to the first scan line GL1, a first electrode connected to the first data line DL1, and a second electrode connected to the gate electrode of the third TFT T3. this is connected In the second TFT T2, a gate electrode is connected to the second scan line GL2, a first electrode is connected to the reference line Ref, and a second electrode is connected to the R1 subpixel. The third TFT (T3) has a gate electrode connected to the second electrode of the first TFT (T1), a first electrode connected to the first power line EVDD, and a second electrode connected to the R1 subpixel. When the first scan signal SCAN1 is input to the first scan line GL1 in the R1 subpixel, the first data voltage Data1 input to the first data line DL is charged in the R1 subpixel.

In subpixel G1, the gate electrode of the first TFT (T1) is connected to the second scan line (GL2), the first electrode is connected to the first data line (DL1), and the gate electrode of the third TFT (T3) is connected to the second electrode. this is connected In the second TFT T2, a gate electrode is connected to the second scan line GL2, a first electrode is connected to the reference line Ref, and a second electrode is connected to the G1 subpixel. The third TFT (T3) has a gate electrode connected to the second electrode of the first TFT (T1), a first electrode connected to the first power line EVDD, and a second electrode connected to the G1 subpixel. When the second scan signal SCAN2 is input from the G1 subpixel, the first data voltage Data1 input to the first data line DL1 is charged in the G1 subpixel.

In subpixel B1, the first TFT (T1) has a gate electrode connected to the first scan line GL1, a first electrode connected to the second data line DL2, and a second electrode connected to the gate electrode of the third TFT (T3). this is connected In the second TFT T2, a gate electrode is connected to the first scan line GL1, a first electrode is connected to the reference line Ref, and a second electrode is connected to the B1 subpixel. The third TFT (T3) has a gate electrode connected to the second electrode of the first TFT (T1), a first electrode connected to the first power line EVDD, and a second electrode connected to the G1 subpixel. When the first scan signal SCAN1 is input to the first scan line GL1 in the B1 subpixel, the second data voltage Data2 input to the second data line DL2 is charged in the B1 subpixel.

An R2 subpixel, a G2 subpixel, and a B2 subpixel are arranged on an n+1th horizontal line (n+1 Line) of the pixel array.

In the R2 subpixel, the gate electrode of the first TFT T1 is connected to the third scan line GL3, the first electrode is connected to the first data line DL1, and the second electrode is connected to the gate electrode of the third TFT T3. this is connected In the second TFT T2, a gate electrode is connected to the third scan line GL3, a first electrode is connected to the reference line Ref, and a second electrode is connected to the R2 subpixel. The gate electrode of the third TFT (T3) is connected to the second electrode of the first TFT (T1), the first electrode is connected to the first power line (EVDD), and the second electrode is connected to the R2 subpixel. When the third scan signal SCAN3 is input to the third scan line GL3 in the R2 subpixel, the first data voltage Data1 input to the first data line DL1 is charged in the R2 subpixel.

In the G2 subpixel, the gate electrode of the first TFT (T1) is connected to the fourth scan line (GL4), the first electrode is connected to the second data line (DL2), and the gate electrode of the third TFT (T3) is connected to the second electrode. this is connected In the second TFT T2, a gate electrode is connected to the fourth scan line GL4, a first electrode is connected to the reference line Ref, and a second electrode is connected to the G2 subpixel. The third TFT (T3) has a gate electrode connected to the second electrode of the first TFT (T1), a first electrode connected to the first power line EVDD, and a second electrode connected to the G2 subpixel. When the fourth scan signal SCAN4 is input to the fourth scan line GL4 in the G2 subpixel, the second data voltage Data2 input to the second data line DL2 is charged in the G2 subpixel.

In subpixel B2, the first TFT (T1) has a gate electrode connected to the third scan line GL3, a first electrode connected to the second data line DL2, and a second electrode connected to the gate electrode of the third TFT (T3). this is connected In the second TFT T2, a gate electrode is connected to the third scan line GL3, a first electrode is connected to the reference line Ref, and a second electrode is connected to the B2 subpixel. The third TFT (T3) has a gate electrode connected to the second electrode of the first TFT (T1), a first electrode connected to the first power line EVDD, and a second electrode connected to the B2 subpixel. When the third scan signal SCAN3 is input to the third scan line GL3 in the B2 subpixel, the second data voltage Data2 input to the second data line DL2 is charged in the B2 subpixel.

As described above, the R1 subpixel and the G1 subpixel in the n-th horizontal line (n Line) share the first data line DL1 to drive the DRD. The B1 subpixel is normally driven by being connected to the second data line DL2. The first scan signal Scan1 and the second scan signals Scan1 and Scan2 are input to the nth horizontal line (n Line).

In the n+1th horizontal line (n+1 Line), the R1 subpixel is connected to the data line DL1 and driven normally. The G1 subpixel and the B1 subpixel are DRD-driven by sharing the second data line DL2. The third and fourth scan signals Scan1 and Scan2 are input to the n+1th horizontal line (n+1 Line).

Referring to FIG. 6, the pixel array of this embodiment uses the first to fourth scan signals (Scan1 to Scan4) during a two-line period (2 HT) in which data is input to two lines to generate nth and n+1th scan signals. Data can be entered in the horizontal line.

When the first scan signal Scan1 is input at a high level, the TFT connected to the R1 subpixel and the TFT connected to the B1 subpixel are turned on. Accordingly, the R1 subpixel is connected to the first data line DL1 to receive a data voltage, and the B1 subpixel is connected to the second data line DL2 to receive a data voltage.

When the second scan signal Scan2 is input at a high level, the TFT connected to the G1 subpixel is turned on. The G1 subpixel is connected to the first data line DL1 to receive a data voltage. Here, when the second scan signal Scan2 is input, the fourth scan signal Scna4 is also output at the same time. When the fourth scan signal Scan4 is input, the TFT connected to the G2 subpixel is turned on. The G2 subpixel is connected to the second data line DL2 to receive a data voltage.

When the third scan signal Scan3 is input at a high level, the TFT connected to the R2 subpixel and the TFT connected to the B2 subpixel are turned on. Accordingly, the R2 subpixel is connected to the first data line DL1 to receive the data voltage, and the B2 subpixel is connected to the second data line DL2 to receive the data voltage.

As described above, in the present invention, when the output period of the first scan signal (Scan1), the output period of the second and fourth scan signals (Scan2, Scan 4), and the output period of the third scan signal (Scan3) are completed, two lines are displayed. Data voltage can be supplied. In the past, it took four scan signals to be sequentially output four times in order to supply data voltages to two lines, but the present invention only takes three scan signal output times, so the number of driving frequencies can be improved by about 1.3 times. can In addition, since both the first data line DL1 and the second data line DL2 are used during all scan signal output periods, the scan signal Scan can be efficiently driven.

FIG. 7 is a diagram showing a pixel array of a display device according to a second exemplary embodiment of the present invention, and FIG. 8 is a driving waveform diagram of the pixel array of FIG. 7 .

In the second embodiment of the present invention, in the configuration of the pixel array of the first embodiment, scan signals simultaneously output from among scan signals of n lines and scan signals of n+1 lines are combined into one It is supplied through the scan line. That is, in the second embodiment, n Line and n+1 Line may have a structure in which a scan line is shared.

7 is a circuit diagram showing part of a pixel array as a second embodiment of the pixel array.

The pixel array includes data lines DL1 to DL2 and scan lines GL1 to GL3 crossing the data lines DL1 to DL2. The sub-pixels R1 to R2, G1 to G2, and B1 to B2 control the connection with the data lines DL1 to DL2 according to the scan signals Scan1 to Scan3 input to the scan lines GL1 to GL3. A first TFT (T1), a second TFT (T2) controlling the connection to the reference (Ref) line, and a third TFT (T3) controlling the connection to the first power line (EVDD) are respectively included.

An R1 subpixel, a G1 subpixel, and a B1 subpixel are arranged on an nth horizontal line (n Line) of the pixel array.

In the R1 sub-pixel, the first TFT T1 has a gate electrode connected to the first scan line GL1, a first electrode connected to the first data line DL1, and a second electrode connected to the gate electrode of the third TFT T3. this is connected In the second TFT T2, a gate electrode is connected to the second scan line GL2, a first electrode is connected to the reference line Ref, and a second electrode is connected to the R1 subpixel. The third TFT (T3) has a gate electrode connected to the second electrode of the first TFT (T1), a first electrode connected to the first power line EVDD, and a second electrode connected to the R1 subpixel. When the first scan signal SCAN1 is input to the first scan line GL1 in the R1 subpixel, the first data voltage Data1 input to the first data line DL is charged in the R1 subpixel.

In subpixel G1, the gate electrode of the first TFT (T1) is connected to the second scan line (GL2), the first electrode is connected to the first data line (DL1), and the gate electrode of the third TFT (T3) is connected to the second electrode. this is connected In the second TFT T2, a gate electrode is connected to the second scan line GL2, a first electrode is connected to the reference line Ref, and a second electrode is connected to the G1 subpixel. The third TFT (T3) has a gate electrode connected to the second electrode of the first TFT (T1), a first electrode connected to the first power line EVDD, and a second electrode connected to the G1 subpixel. When the second scan signal SCAN2 is input to the second scan line GL2 in the G1 subpixel, the first data voltage Data1 is charged in the G1 subpixel.

In subpixel B1, the first TFT (T1) has a gate electrode connected to the first scan line GL1, a first electrode connected to the second data line DL2, and a second electrode connected to the gate electrode of the third TFT (T3). this is connected In the second TFT T2, a gate electrode is connected to the first scan line GL1, a first electrode is connected to the reference line Ref, and a second electrode is connected to the B1 subpixel. The third TFT (T3) has a gate electrode connected to the second electrode of the first TFT (T1), a first electrode connected to the first power line EVDD, and a second electrode connected to the G1 subpixel. When the first scan signal SCAN1 is input to the first scan line GL1 in the B1 subpixel, the second data voltage Data2 input to the second data line DL2 is charged in the B1 subpixel.

An R2 subpixel, a G2 subpixel, and a B2 subpixel are arranged on an n+1th horizontal line (n+1 Line) of the pixel array.

In the R2 subpixel, the gate electrode of the first TFT T1 is connected to the third scan line GL3, the first electrode is connected to the first data line DL1, and the second electrode is connected to the gate electrode of the third TFT T3. this is connected In the second TFT T2, a gate electrode is connected to the third scan line GL3, a first electrode is connected to the reference line Ref, and a second electrode is connected to the R2 subpixel. The gate electrode of the third TFT (T3) is connected to the second electrode of the first TFT (T1), the first electrode is connected to the first power line (EVDD), and the second electrode is connected to the R2 subpixel. When the third scan signal SCAN3 is input to the third scan line GL3 in the R2 subpixel, the first data voltage Data1 input to the first data line DL1 is charged in the R2 subpixel.

The G2 subpixel shares the second scan line GL2 with the G1 subpixel. In the G2 subpixel, the gate electrode of the first TFT (T1) is connected to the second scan line (GL2), the first electrode is connected to the second data line (DL2), and the second electrode is connected to the gate electrode of the third TFT (T3). Connected. In the second TFT T2, a gate electrode is connected to the second scan line GL2, a first electrode is connected to the reference line Ref, and a second electrode is connected to the G2 subpixel. The third TFT (T3) has a gate electrode connected to the second electrode of the first TFT (T1), a first electrode connected to the first power line EVDD, and a second electrode connected to the G2 subpixel. In the G2 subpixel, the second scan signal SCAN2 from the second scan line GL2 is input to the second data line DL2, and the second data voltage Data2 is charged in the G2 subpixel.

In subpixel B2, the first TFT (T1) has a gate electrode connected to the third scan line GL3, a first electrode connected to the second data line DL2, and a second electrode connected to the gate electrode of the third TFT (T3). this is connected In the second TFT T2, a gate electrode is connected to the third scan line GL3, a first electrode is connected to the reference line Ref, and a second electrode is connected to the B2 subpixel. The third TFT (T3) has a gate electrode connected to the second electrode of the first TFT (T1), a first electrode connected to the first power line EVDD, and a second electrode connected to the B2 subpixel. When the third scan signal SCAN3 is input to the third scan line GL3 in the B2 subpixel, the second data voltage Data2 input to the second data line DL2 is charged in the B2 subpixel.

As described above, the R1 subpixel and the G1 subpixel in the n-th horizontal line (n Line) share the first data line DL1 to drive the DRD. The B1 subpixel is normally driven by being connected to the second data line DL2.

In the n+1th horizontal line (n+1 Line), the R1 subpixel is connected to the data line DL1 and driven normally. The G1 subpixel and the B1 subpixel are DRD-driven by sharing the second data line DL2.

The first scan signal Scan1 is input to the nth horizontal line (n Line), and the third scan signal Scan3 is input to the n+1th horizontal line (n+1 Line). In addition, the second scan signal Scan2 shared by the n-th horizontal line (n Line) and the n+1-th horizontal line (n+1 Line) is input.

Referring to FIG. 8 , in the pixel array of this embodiment, data may be input to the n-th and n+1-th horizontal lines using the first to third scan signals Scan1 to Scan3.

When the first scan signal Scan1 is input at a high level, the TFT connected to the R1 subpixel and the TFT connected to the B1 subpixel are turned on. Accordingly, the R1 subpixel is connected to the first data line DL1 to receive a data voltage, and the B1 subpixel is connected to the second data line DL2 to receive a data voltage.

When the third scan signal Scan3 is input at a high level, the TFT connected to the R2 subpixel and the TFT connected to the B2 subpixel are turned on. Accordingly, the R2 subpixel is connected to the first data line DL1 to receive the data voltage, and the B2 subpixel is connected to the second data line DL2 to receive the data voltage.

The second scan signal Scan2 is shared by the n-th and n+1-th horizontal lines. When the second scan signal Scan2 is input at a high level, the TFT connected to the G1 subpixel and the TFT connected to the G2 subpixel are turned on. The G1 subpixel is connected to the first data line DL1 to receive a data voltage, and the G2 subpixel is connected to the second data line DL2 to receive a data voltage.

As described above, according to the second embodiment of the present invention, data voltages can be supplied to two lines using three scan signals (Scan1 to Scan3). Therefore, the number of scan signal lines can be reduced. In addition, compared to the conventional supply of data voltages to two lines, which required four scan signals to be sequentially output four times, the present invention requires only three scan signal output times, so the number of driving frequencies is improved by about 1.3 times. It can be. In addition, since both the first data line DL1 and the second data line DL2 are used during all scan signal output periods, the scan signal Scan can be efficiently driven.

9 to 11 are simulation results of a method of driving a display device according to an exemplary embodiment of the present invention.

9 and 10 are graphs of simulation results of a driving frequency of a display device according to an embodiment of the present invention, and are simulation results obtained by applying the driving method of the present invention to a 31.5" UHD display panel to which 3T1C pixels are applied.

The graph of FIG. 9 is a graph obtained by simulating a driving frequency that satisfies a luminance achievement rate of 90% in the first frame when a scan signal is input. The horizontal axis represents the driving frequency and the vertical axis represents the ΔIoled value. Here, it can be calculated by the formula of ΔIoled = 1st frame current / 4th frame current x 100%.

According to an embodiment of the present invention, only three scan signal output times are required during a period of 2HT for supplying data voltages to two lines. Therefore, one color can be driven for 2/3HT, and as a result, the data charging time can be increased by 1.3 times. Accordingly, as shown in the graph of FIG. 9 , it was confirmed that the driving frequency increased by 1.3 times to 151 Hz, whereas conventionally it was about 115 Hz.

10 is a graph showing a result of simulating a driving frequency of a pixel array according to an embodiment of the present invention in a state optimized for high-speed driving by applying an IC option for high-speed driving.

In a state optimized for high-speed driving, the driving speed of an existing display device can be increased up to 161 Hz. On the other hand, according to the embodiment of the present invention it was confirmed that the driving speed is increased up to 208Hz.

11 and 12 are graphs as a result of simulating PPI and bezel size that can be implemented when a pixel array is configured according to the second embodiment of the present invention, and is a graph showing a 31.5" UHD display panel to which 3T1C pixels are applied. These are the results of applying the pixel structure of

The graph of FIG. 11 shows the maximum PPI that can be obtained when a pixel array is configured such that the number of scan lines is reduced according to the second embodiment of the present invention.

The second embodiment of the present invention has a structure in which n Line and n+1 Line share a scan line. Accordingly, in the past, 4 scan signal lines were required to input data to 2 horizontal lines, but when the present invention is applied, data can be input with 3 scan signal lines to 2 horizontal lines. In this way, as one scan signal per two horizontal lines decreases, the maximum PPI increases when designing a pixel according to a design rule. As shown in FIG. 11, about 10 PPI can be increased by reducing the scan line signal, which is about 5% increase of the total PPI.

When the number of scan lines is reduced, the GIP structure outputting scan signals is also changed. That is, the conventional GIP outputs the scan signal with 4 scan signal lines per 2 horizontal lines, but when the present invention is applied, the scan signal can be output with 3 scan signal lines. In this way, as one scan signal per two horizontal lines decreases, the size of the left/right bezel on which the GIP is formed can also be reduced. As shown in FIG. 12 , the size of the left/right bezels can be reduced by about 0.4 mm by changing the GIP structure, which is about 10% reduction based on the size of the entire bezel.

As described above, the present invention includes both DRD driving pixels and normal driving pixels in one panel, and the DRD driving pixels share different data lines in the nth line and the n+1th line. With this configuration, it is possible to prevent a luminance deviation from occurring between subpixels of the same color. Also, according to an embodiment of the present invention, one of the DRD driving pixels shares one scan line in the n-th line and the n+1-th line. With this configuration, whereas conventionally, 4 scan signals per 2 horizontal lines were required, when the present invention is applied, data can be supplied to 2 horizontal lines within 3 scan signal output periods, and scan signal lines can also be reduced. As a result, the driving frequency may increase, the PPI may increase, and the size of the bezel may decrease.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, the above-described technical configuration of the present invention can be changed into other specific forms by those skilled in the art without changing the technical spirit or essential features of the present invention. It will be appreciated that this can be implemented. Therefore, the embodiments described above should be understood as illustrative in all respects and not limiting. In addition, the scope of the present invention is indicated by the claims to be described later rather than the above detailed description. In addition, all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention.

110: image processing unit 120: timing control unit
130: scan driving unit 140: data driving unit
150: display panel 1 180: power supply unit

Claims (12)

a first sub-pixel group including a pair of sub-pixels disposed adjacent to each other in a horizontal direction and sharing a data line; and
A second sub-pixel group including sub-pixels not sharing a data line;
The first subpixel groups included in the nth (n>1) horizontal line and the first subpixel groups included in the n+1th horizontal line include display panels that share different data lines,
Among the subpixels included in the first subpixel group of the nth horizontal line and the subpixels included in the first subpixel group of the n+1th horizontal line, a subpixel of the same color is selected in the same scan signal period. A display device that receives data voltage from each corresponding data line. According to claim 1,
The second sub-pixel group,
A display device in which second sub-pixel groups included in the n-th horizontal line and second sub-pixel groups included in the n+1-th horizontal line share different data lines. According to claim 1,
In the horizontal line, subpixels are arranged in units of three subpixels including a red (R) subpixel, a green (G) subpixel, and a blue (B) subpixel, and one adjacent one of the three subpixels A display device in which a pair of subpixels is the first subpixel group and the other subpixel is the second subpixel group. According to claim 3,
In the n-th horizontal line, the red (R) subpixel and the green (G) subpixel share a first data line, and the blue (B) subpixel is connected to a second data line;
In the n+1th horizontal line, the red (R) subpixel is connected to the first data line, and the green (G) subpixel and blue (B) subpixel share the second data line. Device. According to claim 4,
a scan driver supplying a scan signal; and
A data driver supplying a data voltage to the data line;
When the scan signal is input, two subpixels among the three subpixels included in the nth horizontal line and the three subpixels included in the n+1th horizontal line are selected;
The data driver supplies corresponding data voltages to a first data line and a second data line respectively connected to the two subpixels to which the scan signal is input. delete a first sub-pixel group including a pair of sub-pixels disposed adjacent to each other in a horizontal direction and sharing a data line; and
A second sub-pixel group including sub-pixels not sharing a data line;
The first subpixel groups included in the nth (n>1) horizontal line and the first subpixel groups included in the n+1th horizontal line include display panels that share different data lines,
The subpixels included in the first subpixel group of the nth horizontal line and the subpixels of the same color among the subpixels included in the first subpixel group of the n+1th horizontal line receive the same scan signal. Device. According to claim 5,
When a first scan signal is input, a subpixel connected to the first data line and a subpixel connected to the second data line among the subpixels included in the nth horizontal line are selected and supplied with corresponding data voltages;
When a second scan signal is input, among the subpixels included in the n+1th horizontal line, a subpixel connected to the first data line and a subpixel connected to the second data line are selected and supplied with corresponding data voltages;
When the third scan signal is input, the subpixel included in the nth horizontal line to which the data voltage is not supplied and the subpixel included in the n+1th horizontal line to which the data voltage is not supplied are not supplied. A display device in which each sub-pixel is selected and supplied with a data voltage through the first data line and the second data line connected to the corresponding sub-pixel. According to claim 8,
The scan line to which the third scan signal is input is shared by subpixels included in the nth horizontal line and subpixels included in the n+1th horizontal line. A display device including a data driver for supplying data voltages to data lines, a scan driver for supplying scan signals to scan lines, and a display panel including subpixels arranged in a matrix type and connected to the data lines and scan lines. In the driving method of
When the first scan signal is input, among the red (R) sub-pixel, green (G) sub-pixel, and blue (B) sub-pixel included in the n (n>1)-th horizontal line of the display panel, the sub-pixel connected to the first data line selecting a pixel and a sub-pixel connected to a second data line and supplying data voltages to each of them;
When a second scan signal is input, a subpixel connected to the first data line among red (R) subpixels, green (G) subpixels, and blue (B) subpixels included in the n+1th horizontal line and the second data line selecting subpixels connected to the line and supplying data voltages to each of the subpixels; and
When the third scan signal is input, a subpixel included in the nth horizontal line to which data voltage is not supplied and a subpixel included in the n+1th horizontal line to which data voltage is not supplied are selected. and supplying respective data voltages through the first data line and the second data line,
Among the subpixels included in the first subpixel group of the nth horizontal line and the subpixels included in the first subpixel group of the n+1th horizontal line, a subpixel of the same color is selected in the same scan signal period. A method of driving a display device receiving data voltages from respective data lines. According to claim 10,
In the horizontal line, subpixels are arranged in units of three subpixels including a red (R) subpixel, a green (G) subpixel, and a blue (B) subpixel,
a first subpixel group including a pair of subpixels sharing a data line among the three subpixels; and a second subpixel group including subpixels not sharing a data line. According to claim 11,
and a display panel in which the first subpixel groups included in the nth horizontal line and the first subpixel groups included in the n+1th horizontal line share different data lines.

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