KR102569587B1 - Semiconductor device package - Google Patents

Abstract

An embodiment is a body having a cavity; a first electrode and a second electrode disposed on a bottom surface of the cavity, and a third electrode disposed between the first electrode and the second electrode; an alloy layer disposed on the third electrode; a semiconductor element disposed on the alloy layer and electrically connected to at least one of the first electrode and the second electrode; a light transmitting member disposed on the semiconductor device and covering the cavity; a plurality of pads disposed on the lower surface of the body; and a heat dissipation member disposed between a bottom surface of the cavity and a lower surface of the body, wherein the body includes a first ceramic layer disposed between the heat dissipation member and the third electrode, the heat dissipation member, and the plurality of pads. and a second ceramic layer disposed therebetween, wherein the heat dissipation member includes a first heat dissipation part disposed under the third electrode and a second heat dissipation part disposed under the first heat dissipation part, The width of the heat dissipation part is equal to or greater than the width of the third electrode, the width of the second heat dissipation part is smaller than the width of the third electrode, and the thickness of the first ceramic layer and the second ceramic layer is the thickness of the heat dissipation member. A semiconductor device package of 20% or less of is disclosed.

Description

Semiconductor device package {SEMICONDUCTOR DEVICE PACKAGE}

The embodiment relates to a semiconductor device package.

Semiconductor devices including compounds such as GaN and AlGaN have many advantages, such as having a wide and easily adjustable band gap energy, and can be used in various ways such as light emitting devices, light receiving devices, and various diodes.

In particular, light emitting devices such as light emitting diodes or laser diodes using group 3-5 or group 2-6 compound semiconductor materials of semiconductors are developed in thin film growth technology and device materials to produce red, green, Various colors such as blue and ultraviolet can be realized, and white light with high efficiency can be realized by using fluorescent materials or combining colors. , safety, and environmental friendliness.

In addition, when light receiving devices such as photodetectors or solar cells are manufactured using group 3-5 or group 2-6 compound semiconductor materials, photocurrent is generated by absorbing light in various wavelength ranges through the development of device materials. By doing so, it is possible to use light in a wide range of wavelengths from gamma rays to radio wavelengths. In addition, it has the advantages of fast response speed, safety, environmental friendliness, and easy control of element materials, so that it can be easily used in power control or ultra-high frequency circuits or communication modules.

Accordingly, the semiconductor device can replace a transmission module of an optical communication means, a light emitting diode backlight that replaces a Cold Cathode Fluorescence Lamp (CCFL) constituting a backlight of an LCD (Liquid Crystal Display) display device, and can replace a fluorescent lamp or an incandescent bulb. Applications are expanding to white light emitting diode lighting devices, automobile headlights and traffic lights, and sensors that detect gas or fire. In addition, applications of semiconductor devices can be expanded to high-frequency application circuits, other power control devices, and communication modules.

In particular, a light emitting element that emits light in the ultraviolet wavelength region can be used for curing, medical, and sterilization purposes by performing a curing or sterilizing action.

Recently, research on UV light emitting device packages has been actively conducted, but there is a problem in that internal heat cannot be effectively discharged to the outside. Although a heat dissipation member may be disposed inside the body to improve heat dissipation, there is a problem in that eutectic bonding between the electrode and the semiconductor element becomes poor due to a step caused by the heat dissipation member.

The embodiment provides a semiconductor device package in which bonding between an electrode and a semiconductor device is improved.

In addition, a semiconductor device package with excellent heat dissipation is provided.

The problem to be solved in the embodiment is not limited thereto, and it will be said that the solution to the problem described below or the purpose or effect that can be grasped from the embodiment is also included.

A semiconductor device package according to one aspect of the present invention includes a body having a cavity; a first electrode and a second electrode disposed on a bottom surface of the cavity, and a third electrode disposed between the first electrode and the second electrode; a semiconductor element disposed on the third electrode and electrically connected to at least one of the first electrode and the second electrode; a light transmitting member disposed on the semiconductor device and covering the cavity; a plurality of pads disposed on the lower surface of the body; and a heat dissipation member disposed between a bottom surface of the cavity and a lower surface of the body, wherein the body includes a first ceramic layer disposed between the heat dissipation member and the third electrode, the heat dissipation member, and the plurality of pads. and a second ceramic layer disposed therebetween, wherein the heat dissipation member includes a first heat dissipation part disposed under the third electrode and a second heat dissipation part disposed under the first heat dissipation part, The width of the heat dissipation part is equal to or greater than the width of the third electrode, the width of the second heat dissipation part is smaller than the width of the third electrode, and the thickness of the first ceramic layer and the second ceramic layer is the thickness of the heat dissipation member. is less than 20% of

A semiconductor device package according to another aspect of the present invention includes a body having a cavity; a first electrode and a second electrode disposed on a bottom surface of the cavity and spaced apart in a first direction, and a third electrode disposed between the first electrode and the second electrode; a semiconductor device disposed on the third electrode; a light transmitting member disposed on the cavity; a first pad and a second pad disposed on a lower surface of the body and spaced apart from each other in the first direction, and a third pad disposed between the first pad and the second pad; And a heat dissipation member disposed between the bottom surface of the cavity and the lower surface of the body, wherein the cavity includes a first side and a third side facing each other, and a second side and a fourth side facing each other, , The first electrode includes a first unit electrode disposed between the third side surface and the semiconductor element and a second unit electrode disposed between the fourth side surface and the semiconductor element, and the second electrode comprises the first unit electrode disposed between the third side surface and the semiconductor element. a third unit electrode disposed between a first side surface and the semiconductor element and a fourth unit electrode disposed between the second side surface and the semiconductor element, wherein the third electrode comprises the first side surface and the fourth side surface a first extension portion extending to an edge portion formed by the second side surface and a second extension portion extending to an edge portion formed by the third side surface; pad, and the first electrode and the second electrode are electrically connected to the second pad by a connection electrode.

According to the embodiment, bonding reliability between an electrode and a semiconductor device may be improved. Therefore, the problem of the operating voltage rising can be improved.

In addition, heat dissipation efficiency of the semiconductor device package may be improved.

Various advantageous advantages and effects of the present invention are not limited to the above description, and will be more easily understood in the process of describing specific embodiments of the present invention.

1 is a plan view of a semiconductor device package according to an embodiment of the present invention;
2 is a cross-sectional view of a semiconductor device package according to an embodiment of the present invention;
Figure 3 is an enlarged view of Figure 2,
4 is a plan view of a fourth ceramic layer of a body;
5 is a bottom view of a semiconductor device package according to an embodiment of the present invention;
6 is an exploded perspective view showing electrical connections between a plurality of electrodes and a plurality of pads;
7 is a conceptual diagram of a semiconductor device according to an embodiment of the present invention.

The present embodiments may be modified in other forms or combined with each other, and the scope of the present invention is not limited to each of the embodiments described below.

Even if a matter described in a specific embodiment is not described in another embodiment, it may be understood as a description related to another embodiment, unless there is a description contrary to or contradictory to the matter in another embodiment.

For example, if the characteristics of component A are described in a specific embodiment and the characteristics of component B are described in another embodiment, the opposite or contradictory description even if the embodiment in which components A and B are combined is not explicitly described. Unless there is, it should be understood as belonging to the scope of the present invention.

In the description of the embodiment, in the case where an element is described as being formed “on or under” of another element, on or under (on or under) or under) includes both elements formed by directly contacting each other or by indirectly placing one or more other elements between the two elements. In addition, when expressed as "on or under", it may include the meaning of not only the upward direction but also the downward direction based on one element.

Hereinafter, with reference to the accompanying drawings, embodiments of the present invention will be described in detail so that those skilled in the art can easily carry out the present invention.

1 is a plan view of a semiconductor device package according to an exemplary embodiment, FIG. 2 is a cross-sectional view of the semiconductor device package according to an exemplary embodiment, and FIG. 3 is an enlarged view of FIG. 2 .

Referring to FIGS. 1 and 2 , the semiconductor device package according to the embodiment includes a body 100 having cavities 101 and 102 and a plurality of electrodes 210 disposed on the bottom surface 103 of the cavities 101 and 102 . , 220, 230), the semiconductor element 400 electrically connected to the plurality of electrodes 210, 220, and 230, the light transmitting member 300 disposed on the cavity 101, 102, and the lower surface of the body 100 ( 110a), a plurality of pads 241, 242, 243, and a heat dissipation member 190 disposed between the bottom surface 103 of the cavity 101, 102 and the lower surface 110a of the body 100. do.

The body 100 may include a plurality of insulating layers 110-180. The plurality of insulating layers 110-180 include a ceramic material, and the ceramic material includes a co-fired low temperature co-fired ceramic (LTCC) or high temperature co-fired ceramic (HTCC). can include

The body 100 may include a metal pattern formed on at least one of upper and lower surfaces of an arbitrary insulating layer, and a connection electrode that is vertically penetrated and selectively connected to the metal pattern. The connection electrode includes a via or a via hole, but is not limited thereto.

As another example, the plurality of insulating layers 110 - 180 may include an insulating member such as a nitride or an oxide, and preferably may include an oxide or a metal nitride having higher thermal conductivity than that of the nitride. The material of the body 100 may be, for example, SiO ₂ , Si _x O _y , Si ₃ N ₄ , Si _x N _y , SiO _x N _y , Al ₂ O ₃ , or AlN, and the thermal conductivity is 140 W/mK It can be formed of more than one metal nitride, but is not necessarily limited thereto.

The thickness of each layer of the body 100 may be the same thickness or at least one may have a different thickness, but is not limited thereto. Each insulating layer of the body 100 is an individual layer laminated in a manufacturing process, and may be integrally formed after firing is completed.

Although the body 100 shows a structure in which eight layers are stacked, the number of layers is not limited. Illustratively, the insulating layer may be composed of 4 or 6 layers.

The body 100 may include a first cavity 101 therein. A semiconductor device 400 and a plurality of electrodes 210 , 220 , and 230 may be disposed inside the first cavity 101 . The first cavity 101 includes a polygonal shape, and may be formed in a shape in which corners are chamfered, for example, a curved shape.

The first cavity 101 may be defined as a region formed inside the fifth insulating layer 150 . Accordingly, the bottom surface 103 of the first cavity 101 may be the upper surface of the fourth insulating layer 140, and the side surfaces of the first cavity 101 may be inclined side surfaces of the fifth insulating layer 150. there is. Accordingly, the first cavity 101 may have a tapered shape that widens upward.

The fifth insulating layer 150 may determine the height of the first cavity 101 . Therefore, the fifth insulating layer 150 may be formed thicker than the other insulating layers. However, it is not necessarily limited thereto, and the first cavity 101 may be formed by stacking a plurality of insulating layers.

The second cavity 102 may be formed above the first cavity 101 . The second cavity 102 may be formed inside the seventh insulating layer 170 and the eighth insulating layer 180 . A bottom surface of the second cavity 102 may be a top surface of the sixth insulating layer 160 . Accordingly, the light transmitting member 300 may be disposed in the second cavity 102 and fixed to the upper surface of the sixth insulating layer 160 . The sixth insulating layer 160 may be made thinner than the seventh insulating layer 170 and the eighth insulating layer 180, but is not necessarily limited thereto.

A reflective layer (not shown) may be selectively disposed on sidewalls of the cavities 101 and 102 . The reflective layer may be a metal having a reflectance of 50% or more, or a metal having high thermal conductivity may be coated. The reflective layer may improve light extraction efficiency in the cavities 101 and 102 and improve heat dissipation characteristics. When the material of the body 100 is a material having excellent reflectivity and good thermal conductivity, such as AlN or Al ₂ O ₃ , the reflective layer may be omitted.

Molding members may be disposed in the first cavity 101 and the second cavity 102 . In addition, air or an inert gas may be filled in the first cavity 101 and the second cavity 102 . By filling the cavities 101 and 102 with gas, package damage caused by internal expansion of the cavity due to heat generation can be prevented.

The plurality of electrodes 210 , 220 , and 230 may be disposed on the bottom surface 103 of the first cavity 101 . The plurality of electrodes 210, 220, and 230 include a first electrode 220, a second electrode 230, and the first electrode 220 and the second electrode 230 disposed in a first direction (X-axis direction). A third electrode 210 disposed therebetween may be included. The semiconductor device 400 may be disposed on the third electrode 210 , and the first electrode 220 and the second electrode 230 may be disposed to surround side surfaces of the third electrode 210 .

The plurality of electrodes 210, 220, and 230 selectively include platinum (Pt), titanium (Ti), copper (Cu), nickel (Ni), gold (Au), tantalum (Ta), and aluminum (Al). can do. At least one of the plurality of electrodes 210, 220, and 230 may be formed as a single layer or multiple layers. Here, in the multi-layered electrode structure, a gold (Au) material with good bonding may be disposed on the uppermost layer, and titanium (Ti), chromium (Cr), and tantalum (Ta) with good adhesion to the body 100 may be disposed on the lowermost layer. A material may be disposed, and platinum (Pt), nickel (Ni), copper (Cu), or the like may be disposed in the intermediate layer. However, the stacked structure of these electrodes may be variously modified.

The semiconductor device 400 may be electrically connected to the third electrode 210 by eutectic bonding and electrically connected to the first electrode 220 or the second electrode 230 by a wire.

Specifically, an alloy layer may be disposed between the third electrodes 210 of the semiconductor device 400 . The alloy layer may include at least one of Au, In, Cu, Sn, and Ni. Illustratively, the alloy layer may include at least one of Au-In, Cu-Sn, In-Sn, Au-Cu, Au-Sn, and Ni-Sn.

The alloy layer may include eutectic metal. Eutetic bonding has the advantage of excellent heat dissipation. However, the electrical connection method is not necessarily limited thereto, and various methods of electrically connecting semiconductor devices such as solder paste may all be included.

In addition, wire bonding, die bonding, and flip bonding may be selectively used as a connection method of the semiconductor device 400 , and these bonding methods may be variously modified depending on the type of chip and the position of the electrode of the chip. The semiconductor device 400 may be any one of a horizontal type, a vertical type, and a flip chip. In addition, a sub-mount may be disposed between the semiconductor device 400 and the third electrode 210 .

The semiconductor device 400 may emit ultraviolet light. For example, the semiconductor device 400 may emit light (UV-A) in the near ultraviolet wavelength range having a peak wavelength in the range of 320 nm to 420 nm, and light in the far ultraviolet wavelength range having a peak wavelength in the range of 280 nm to 320 nm ( UV-B), or light (UV-C) in the deep ultraviolet wavelength range having a peak wavelength in the range of 100 nm to 280 nm.

The protection element 500 may be disposed on the extension 211 of the third electrode 210 and electrically connected to the first electrode 220 or the second electrode 230 by a wire. However, it is not necessarily limited thereto, and the protection element 500 may be disposed on the first electrode 220 or the second electrode 230 and connected to the third electrode 210 by a wire. The protection element 500 may be a Zener diode, but is not necessarily limited thereto.

The light transmitting member 300 may be disposed in the second cavity 102 . The light transmitting member 300 may be formed of a transparent material such as LiF, MgF ₂ , CaF ₂ , BaF ₂ , Al ₂ O ₃ , SiO ₂ or optical glass (N-BK7), and in the case of SiO ₂ , quartz crystal or UV It may be Fused Silica. However, the light transmitting member 300 is not particularly limited as long as it is made of a material capable of transmitting ultraviolet light.

An adhesive (not shown) may be applied between the light transmitting member 300 and the second cavity 102 . The adhesive may be, for example, Ag paste, UV adhesive, Pb-free low-temperature glass, acrylic adhesive or ceramic adhesive, but is not particularly limited.

The plurality of pads 241, 242, and 243 include a first pad 241, a second pad 243, and the first pad 241 and the second pad 243 disposed in a first direction (X-axis direction). A third pad 242 disposed therebetween may be included. The first pad 241 may be electrically connected to the third electrode 210 , and the second pad 243 may be electrically connected to the first electrode 220 and the second electrode 230 . The third pad 242 may be a non-polar pad not connected to the first to third electrodes 220, 230, and 210, but is not necessarily limited thereto, and any one of the first to third electrodes 220, 230, and 210 It can also be electrically connected to one.

The heat dissipation member 190 may be disposed inside the body 100 to emit heat from the semiconductor device 400 to the outside. When the body 100 is made of a ceramic material having relatively low thermal conductivity, such as Al ₂ O ₃ , a heat dissipation member having excellent thermal conductivity needs to be disposed to compensate for this.

The thickness of the heat dissipation member 190 may be thinner than the thickness between the bottom surfaces 103 of the cavities 101 and 102 and the lower surface 110a of the body 100 . The heat dissipation member 190 may be formed to a thickness of, for example, 150 μm or more and 400 μm or less, but is not necessarily limited thereto.

The material of the heat dissipation member 190 may be a metal, for example, an alloy, and one of the alloy materials may include a metal such as Cu having good thermal conductivity. The heat dissipation member 190 may include a CuW alloy, but is not necessarily limited thereto.

Referring to FIG. 3 , the semiconductor element 400 , the third electrode 210 , the heat dissipation member 190 and the third pad 242 may be overlapped in the thickness direction of the body 100 .

The heat dissipation member 190 may include a first heat dissipation part 191 disposed under the semiconductor device 400 and a second heat dissipation part 192 disposed under the first heat dissipation part 191 . At this time, the width W2 of the first heat dissipating part 191 is equal to or equal to the width W2 of the third electrode 210 disposed between the first electrode 220 and the second electrode 230 in the first direction. can be big When the width of the second heat dissipation part 192 is smaller than the width of the first heat dissipation part 191, it is possible to secure more space inside the body to connect the connection electrode, making it easy to selectively use the third pad 242. In addition, while reducing the size of the package body, it may be easy to place a light emitting device having a large area.

If the width W2 of the first heat dissipation part 191 is smaller than the width of the third electrode 210 and a step occurs due to bending or processing error of the first heat dissipation part 191, the third metal and the semiconductor Gaps may occur between the devices 400 so that only the edges of the semiconductor devices 400 may be bonded. However, if the width of the first heat dissipation part 191 is equal to or greater than the width of the third electrode 210, the third metal and the semiconductor element 400 may be bonded as a whole even if a step occurs. Accordingly, reliability of bonding between the semiconductor element 400 and the electrode may be improved. As a result, the operating voltage may be lowered.

A width W3 of the second heat dissipating portion 192 may be smaller than a width W2 of the third electrode 230 . Also, the width W3 of the second heat dissipation part 192 may be smaller than the width W1 of the semiconductor device 400 . The width W2 of the first heat dissipation part 191 is 100% to 120% of the width of the third electrode 210, and the width W3 of the second heat dissipation part 192 is the width of the third electrode 210. It may be 80% to 95% of. Also, the width W2 of the first heat dissipation part 191 may be smaller than the width of the bottom surface 103 of the first cavity 101 .

A width W4 of the third pad 242 may be greater than a width W2 of the first heat dissipating portion 191 . Accordingly, since the entire area of the semiconductor element 400, the third electrode 210, and the heat dissipation member 190 overlaps the second pad 243 in the vertical direction, the heat generated in the semiconductor element 400 is quickly released to the outside. can do.

The body 100 includes a first ceramic layer disposed between the plurality of electrodes 210, 220, and 230 and the heat dissipation member 190, and disposed between the heat dissipation member 190 and the plurality of pads 241, 242, and 243. A second ceramic layer may be included. The first ceramic layer may be the fourth insulating layer 140 , and the second ceramic layer may be the first insulating layer 110 .

According to the embodiment, the plurality of electrodes 210, 220, 230 and the heat dissipation member 190 may be electrically insulated from each other by the fourth insulating layer 140, and the heat dissipation member by the first insulating layer 110 ( 190) and the plurality of pads 241, 242, and 243 may be electrically insulated.

When the width W2 of the first heat dissipation part 191 is wider than the width of the third electrode 210, the first heat dissipation part 191 may be exposed to the outside due to a processing error or the like. Accordingly, the fourth insulating layer 140 may be disposed on the first heat dissipation portion to prevent the first heat dissipation portion 191 from being exposed.

The thickness d4 of the fourth insulating layer 140 and the thickness d1 of the first insulating layer 110 are greater than 0 and are 20% or less of the total thickness (D2+D3) of the heat dissipating member 20, or 18% or less. can When the thicknesses (d4, d1) of the fourth insulating layer 140 and the first insulating layer 110 are greater than 20% of the thickness of the heat dissipating member 20, the heat pass path becomes long, and the heat dissipation effect may be reduced. That is, since the heat dissipation member 190 according to the embodiment floats between the plurality of electrodes 210, 220, and 230 and the plurality of pads 241, 242, and 243, the fourth insulating layer 140 and the first insulating layer If the thickness of (110) is too thick, heat dissipation performance may deteriorate.

The thickness d4 of the fourth insulating layer 140 and the thickness d1 of the first insulating layer 110 may be the same, but are not necessarily limited thereto. The thickness d4 of the fourth insulating layer 140 and the thickness d1 of the first insulating layer 110 may be 100 μm or less. When the thickness is 100 μm or less, sufficient heat dissipation efficiency may not be obtained. In addition, when the thickness d4 of the fourth insulating layer 140 and the thickness d1 of the first insulating layer 110 are less than 60 μm, or greater than or equal to 30 μm and less than or equal to 50 μm, heat dissipation efficiency may be further improved. .

The vertical distance from the first heat dissipation part 191 to the semiconductor element 400 may be 10% to 30% of the vertical distance from the first heat dissipation part 191 to the lower surface 110a of the body 100 .

4 is a plan view of a fourth insulating layer of a body, FIG. 5 is a bottom view of a semiconductor device package according to an exemplary embodiment, and FIG. 6 is an exploded perspective view showing electrical connections between a plurality of electrodes and a plurality of pads. .

Referring to FIG. 4 , the first cavity 101 may include a first side surface S1 and a third side surface S3 facing each other, and a second side surface S2 and a fourth side surface S4 facing each other. can In addition, the first cavity 101 includes a first edge portion ED1 formed by the first side surface S1 and the second side surface S2 and a second edge formed by the second side surface S2 and the third side surface S3. ED2, a third edge portion ED3 formed by the third side surface S3 and the fourth side surface S4, and a fourth edge portion ED4 formed by the fourth side surface S4 and the first side surface S1. ) may be included. The first to fourth edge portions ED1 to ED4 may include a curvature, but are not necessarily limited thereto.

The first electrode 220 includes a first unit electrode 222 disposed between the third side surface S3 and the semiconductor element 400 and a second unit disposed between the fourth side surface S4 and the semiconductor element 400. An electrode 221 may be included. The first unit electrode 222 may extend in a first direction (X-axis direction) and the second unit electrode 221 may extend in a second direction (Y-axis direction).

The second electrode 230 includes a third unit electrode 232 disposed between the first side surface S1 and the semiconductor device 400 and a fourth unit disposed between the second side surface S2 and the semiconductor device 400. electrode 231, the third unit electrode 232 may extend in a first direction (X-axis direction) and the fourth unit electrode 231 may extend in a second direction (Y-axis direction) .

The third electrode 210 includes a first extension portion 211 extending to the fourth edge portion ED4 of the first cavity 101 and a second extension portion 212 extending to the second edge portion ED2 of the first cavity 101 . can include

The first extension part 211 overlaps the second unit electrode 221 in the second direction and the first region 211a and the first region 211a overlapping the third unit electrode 232 in the first direction. A second region 211b connected to the third electrode 210 may be included. The width of the second region 211b in the first direction may be greater than the width of the first region 211a in the first direction, but is not necessarily limited thereto.

The second extension part 212 overlaps the fourth unit electrode 231 in the second direction and the first region 212a and the first region 212a overlapping the first unit electrode 222 in the first direction. A second region 121b connected to the third electrode 210 may be included.

The first extension part 211 and the second extension part 212 may be formed symmetrically with respect to the semiconductor device 400 . Accordingly, heat generated in the semiconductor device 400 may be uniformly discharged from the cavities 101 and 102 , thereby improving thermal stability of the semiconductor device package.

The protection element 500 may be disposed on the first region 211a of the first extension 211 or the first region 212b of the second extension 212 . The first region where the protection element 500 is not disposed may be a dummy electrode.

The first cavity 101 has a first imaginary line L1 penetrating the center of the first side surface S1 and the center of the third side surface S3, and the center of the second side surface S2 and the fourth side surface S4. It may include a plurality of divided areas F1, F2, F3, F4 defined by the second imaginary line L2 penetrating the .

The plurality of divided regions F1, F2, F3, and F4 include a first divided region F1 including a fourth side surface S4 and a first side surface S1, and a first side surface S1 and a second side surface S2. ) The second partitioned area F2 including, the third partitioned area F3 including the second side S2 and the third side S3, and the third side S3 and the fourth side S4 It may include a fourth partition area (F4) including.

The first extension part 211 is disposed in the first divided area F1, and the second extension part 212 is disposed in the third divided area F3 disposed diagonally with the first divided area F1. can

The first electrode 220 and the second electrode 230 are connected to the second connection electrode P2 extending in the vertical direction, and the first extension 211 and the second extension of the third electrode 210 ( 212) may be electrically connected to the first connection electrode P1.

Referring to FIG. 5 , the plurality of pads 241, 242, and 243 include a first pad 241, a second pad 243, and a first pad 241 and a second pad ( 243) and a third pad 242 disposed between them. The third tile may be wider than the first pad 241 and the second pad 243 .

Referring to FIG. 6 , the first connection electrode P1 connected to the second extension 212 of the third electrode 210 penetrates the third insulation layer 130 and is on the second insulation layer 120. It may be electrically connected to the formed electrode pattern 121 . The electrode pattern 121 of the second insulating layer 120 may be connected to the sub connection electrode 121a. The sub connection electrode 121a may pass through the first insulating layer 110 and be electrically connected to the first pad 241 . That is, the third electrode 210 and the first pad 241 may be electrically connected by the first connection electrode P1, the electrode pattern 121, and the sub connection electrode 121a. The first connection electrode P1 connected to the first extension part 211 of the third electrode 210 may also be connected in the same way.

In addition, the second connection electrode P2 connected to the second electrode 230 penetrates the third insulating layer 130 and the second insulating layer 120 to form an electrode pattern on the first insulating layer 110 ( 111) and electrically connected. The electrode pattern 111 of the first insulating layer 110 may be connected to the sub connection electrode 113 . The sub connection electrode 113 may be electrically connected to the second pad 243 through the first insulating layer 110 . That is, the second electrode 230 and the second pad 243 may be electrically connected by the second connection electrode P2 , the electrode pattern 111 and the sub connection electrode 113 . The second connection electrode P2 connected to the first electrode 220 may also be connected in the same way.

7 is a conceptual diagram of a semiconductor device.

As described above, the semiconductor device according to the embodiment may have a horizontal structure, a vertical structure, and a flip chip structure, but may have a vertical structure.

The semiconductor device has a light emitting structure 420, first electrodes 442 and 465 electrically connected to the first conductive semiconductor layer 424 of the light emitting structure 420, and electrically connected to the second conductive semiconductor layer 427. It includes second electrodes 446 and 450 connected to.

The light emitting structure 420 is disposed between the first conductivity type semiconductor layer 424, the second conductivity type semiconductor layer 427, and the first conductivity type semiconductor layer 424 and the second conductivity type semiconductor layer 427. An active layer 426 may be included.

The first conductivity type semiconductor layer 424 may be implemented with a compound semiconductor such as group III-V or group II-VI, and may be doped with a first dopant. The first conductivity-type semiconductor layer 424 is a semiconductor material having a composition formula of In _x1 Al _y1 Ga _{1 -x1-y1} N (0≤x1≤1, 0≤y1≤1, 0≤x1+y1≤1), eg For example, it may be selected from GaN, AlGaN, InGaN, InAlGaN, and the like. Also, the first dopant may be an n-type dopant such as Si, Ge, Sn, Se, or Te. When the first dopant is an n-type dopant, the first conductivity-type semiconductor layer 424 doped with the first dopant may be an n-type semiconductor layer.

The active layer 426 is disposed between the first conductivity type semiconductor layer 424 and the second conductivity type semiconductor layer 427 . The active layer 426 is a layer where electrons (or holes) injected through the first conductive semiconductor layer 424 and holes (or electrons) injected through the second conductive semiconductor layer 427 meet. The active layer 426 transitions to a lower energy level as electrons and holes recombine, and may generate light having an ultraviolet wavelength.

The active layer 426 may have a structure of any one of a single well structure, a multi-well structure, a single quantum well structure, a multi-quantum well (MQW) structure, a quantum dot structure, or a quantum wire structure, and the active layer 426 ) The structure of is not limited to this.

The second conductivity type semiconductor layer 427 is formed on the active layer 426 and may be implemented with a compound semiconductor such as group III-V or group II-VI. Dopants may be doped. The second conductive semiconductor layer 427 is a semiconductor material having a composition formula of In _x5 Al _y2 Ga _{1 -x5- y2} N (0≤x5≤1, 0≤y2≤1, 0≤x5+y2≤1) or AlInN. , AlGaAs, GaP, GaAs, GaAsP, may be formed of a material selected from AlGaInP. When the second dopant is a p-type dopant such as Mg, Zn, Ca, Sr, or Ba, the second conductivity-type semiconductor layer 427 doped with the second dopant may be a p-type semiconductor layer.

A light emitting structure according to an embodiment may include a plurality of recesses 428 .

The plurality of recesses 428 may be disposed from the lower surface 427G of the second conductive semiconductor layer 427 to a partial region of the first conductive semiconductor layer 424 through the active layer 426 . A first insulating layer 431 may be disposed inside the recess 428 to electrically insulate the first conductive layer 465 from the second conductive semiconductor layer 427 and the active layer 426 .

The first electrodes 442 and 465 may include a first contact electrode 442 and a first conductive layer 465 . The first contact electrode 442 may be disposed on an upper surface of the recess 428 and electrically connected to the first conductive type semiconductor layer 424 .

When the aluminum composition of the light emitting structure 420 increases, current dissipation characteristics within the light emitting structure 420 may deteriorate. In addition, the active layer increases the amount of light emitted to the side compared to the GaN-based blue light emitting device (TM mode). This TM mode may mainly occur in an ultraviolet semiconductor device.

The UV semiconductor device has poor current dissipation characteristics compared to the blue GaN semiconductor device. Accordingly, the UV semiconductor device needs to have relatively more first contact electrodes 442 than the blue GaN semiconductor device.

A second electrode pad 466 may be disposed at a corner region of one side of the semiconductor device.

The first insulating layer 431 is partially opened under the second electrode pad 466 so that the second conductive layer 450 and the second contact electrode 446 can be electrically connected.

The passivation layer 480 may be formed on top and side surfaces of the light emitting structure 420 . The passivation layer 480 may contact the first insulating layer 431 at a region adjacent to the second contact electrode 446 or at a lower portion of the second contact electrode 446 .

The first insulating layer 431 may electrically insulate the first contact electrode 442 from the active layer 426 and the second conductive semiconductor layer 427 . Also, the first insulating layer 431 may electrically insulate the second conductive layer 450 from the first conductive layer 465 .

The first insulating layer 431 may be formed by selecting at least one from the group consisting of SiO ₂ , SixOy, Si ₃ N ₄ , Si _x N _y , SiO _x N _y , Al ₂ O ₃ , TiO ₂ , AlN, and the like. However, it is not limited thereto. The first insulating layer 431 may be formed as a single layer or multiple layers. For example, the first insulating layer 431 may be a multi-layer distributed Bragg reflector (DBR) including silver Si oxide or a Ti compound. However, the first insulating layer 431 is not necessarily limited thereto and may include various reflective structures.

When the first insulating layer 431 performs a reflective function, light emitted from the active layer 426 toward the side surface is upwardly reflected to improve light extraction efficiency. Compared to a semiconductor device emitting blue light, the UV semiconductor device may have more effective light extraction efficiency as the number of recesses 428 increases.

The second electrodes 446 and 450 may include a second contact electrode 446 and a second conductive layer 450 .

The second contact electrode 446 may contact the lower surface of the second conductivity type semiconductor layer 427 . The second contact electrode 446 may include a conductive oxide electrode having relatively little absorption of ultraviolet light. Illustratively, the conductive anode may be ITO, but is not necessarily limited thereto.

The second conductive layer 450 may inject current into the second conductive semiconductor layer 427 . Also, the second conductive layer 450 may reflect light emitted from the active layer 426 .

The second conductive layer 450 may cover the second contact electrode 446 . Accordingly, the second electrode pad 466, the second conductive layer 450, and the second contact electrode 446 may form one electrical channel.

The second conductive layer 450 may surround the second contact electrode 446 and contact the side surface and the bottom surface of the first insulating layer 431 . The second conductive layer 450 is made of a material having good adhesion to the first insulating layer 431, and includes at least one material selected from the group consisting of materials such as Cr, Al, Ti, Ni, Au, and the like. It may be made of an alloy of, and may be made of a single layer or a plurality of layers.

When the second conductive layer 450 contacts the side and bottom surfaces of the first insulating layer 431, the thermal and electrical reliability of the second contact electrode 446 can be improved. In addition, it may have a reflective function of reflecting light emitted between the first insulating layer 431 and the second contact electrode 446 upward.

The second insulating layer 432 may electrically insulate the second conductive layer 450 from the first conductive layer 465 . The first conductive layer 465 may pass through the second insulating layer 432 and be electrically connected to the first contact electrode 442 .

The first conductive layer 465 and the bonding layer 460 may be disposed along the lower surface of the light emitting structure 420 and the shape of the recess 428 . The first conductive layer 465 may be made of a material having excellent reflectivity. For example, the first conductive layer 465 may include aluminum. When the first conductive layer 465 includes aluminum, it serves to reflect light emitted from the active layer 426 upward, thereby improving light extraction efficiency.

The bonding layer 460 may include a conductive material. For example, the bonding layer 460 may include a material selected from the group consisting of gold, tin, indium, aluminum, silicon, silver, nickel, and copper, or an alloy thereof.

The conductive substrate 470 may be made of a conductive material to inject current into the first conductive semiconductor layer 424 . For example, the conductive substrate 470 may include a metal or semiconductor material. The conductive substrate 470 may be a metal having excellent electrical conductivity and/or thermal conductivity. In this case, the heat generated during operation of the semiconductor device can be quickly dissipated to the outside.

The conductive substrate 470 may include a material selected from the group consisting of silicon, molybdenum, silicon, tungsten, copper, and aluminum, or an alloy thereof.

An upper surface of the light emitting structure 420 may have irregularities. Such irregularities may improve extraction efficiency of light emitted from the light emitting structure 420 . The irregularities may have different average heights depending on the wavelength of the ultraviolet light. In the case of UV-C, the light extraction efficiency may be improved when the irregularities have a height of about 300 nm to about 800 nm and an average height of about 500 nm to about 600 nm.

Semiconductor device packages may be applied to various types of light source devices. For example, the light source device may include a sterilization device, a curing device, a lighting device, a display device, and a vehicle lamp. That is, the semiconductor element may be applied to various electronic devices disposed in a case to provide light.

The sterilization device may sterilize a desired area by including the semiconductor device according to the embodiment. The sterilization device may be applied to household appliances such as water purifiers, air conditioners, and refrigerators, but is not necessarily limited thereto. That is, the sterilization device can be applied to various products (eg, medical devices) requiring sterilization.

Illustratively, the water purifier may include a sterilization device according to the embodiment to sterilize circulating water. The sterilization device may be disposed at a nozzle through which water circulates or an outlet to irradiate ultraviolet rays. In this case, the sterilization device may include a waterproof structure.

The curing device may be provided with a semiconductor device according to an embodiment to cure various types of liquids. Liquid may be the lightest concept that includes all various materials that are hardened when irradiated with ultraviolet rays. Illustratively, the curing device may cure various types of resins. Alternatively, the curing device may be applied to curing cosmetic products such as nail polish.

The lighting device may include a light source module including a substrate and the semiconductor device of the embodiment, a heat dissipation unit dissipating heat from the light source module, and a power supply unit that processes or converts an electrical signal received from the outside and provides it to the light source module. Also, the lighting device may include a lamp, a head lamp, or a street lamp.

Although the above has been described with reference to the embodiments, this is only an example and does not limit the present invention, and those skilled in the art to which the present invention belongs will not deviate from the essential characteristics of the present embodiment. It will be appreciated that various variations and applications are possible. For example, each component specifically shown in the embodiment can be modified and implemented. And differences related to these modifications and applications should be construed as being included in the scope of the present invention as defined in the appended claims.

Claims (12)

a body with a cavity;
a first electrode and a second electrode disposed on a bottom surface of the cavity, and a third electrode disposed between the first electrode and the second electrode;
a semiconductor element disposed on the third electrode and electrically connected to at least one of the first electrode and the second electrode;
a light transmitting member disposed on the semiconductor device and covering the cavity;
a plurality of pads disposed on a lower surface of the body; and
A heat dissipation member disposed between the bottom surface of the cavity and the lower surface of the body,
The body includes a first ceramic layer disposed between the heat dissipating member and the third electrode and a second ceramic layer disposed between the heat dissipating member and the plurality of pads,
The heat dissipation member includes a first heat dissipation part disposed under the third electrode and a second heat dissipation part disposed under the first heat dissipation part,
A width of the first heat dissipation part is equal to or greater than a width of the third electrode, and a width of the second heat dissipation part is smaller than a width of the third electrode;
The semiconductor device package of claim 1 , wherein a thickness of the first ceramic layer and the second ceramic layer is 20% or less of a thickness of the heat dissipation member.
According to claim 1,
The semiconductor device package of claim 1 , wherein a vertical distance from the first heat dissipation part to the semiconductor element is 10% to 30% of a vertical distance from the first heat dissipation part to the lower surface of the body.
According to claim 1,
The width of the first heat dissipation part is 100% to 120% of the width of the third electrode,
The semiconductor device package of claim 1 , wherein a width of the second heat dissipation part is 80% to 95% of a width of the third electrode.
According to claim 1,
The semiconductor device package of claim 1 , wherein a width of the first heat dissipating portion is smaller than a width of a bottom surface of the cavity.
According to claim 1,
The cavity includes a first side and a third side facing each other, and a second side and a fourth side facing each other,
The first electrode includes a first unit electrode disposed between the third side surface and the semiconductor element and a second unit electrode disposed between the fourth side surface and the semiconductor element,
The second electrode includes a third unit electrode disposed between the first side surface and the semiconductor element and a fourth unit electrode disposed between the second side surface and the semiconductor element,
The third electrode includes a first extension portion extending to an edge portion formed by the first side surface and the fourth side surface, and a second extension portion extending to an edge portion formed by the second side surface and the third side surface.
According to claim 5,
The first extension part includes a first region and a second region,
The first region overlaps the second unit electrode in a second direction perpendicular to the first direction and overlaps the third unit electrode in the first direction;
The second area is connected to the first area in the second direction,
The width of the second area in the first direction is greater than the width of the first area in the first direction;
The first direction is a direction in which the second unit electrode and the fourth unit electrode are separated.
According to claim 6,
A semiconductor device package including a protection device disposed on the first region.
According to claim 1,
The semiconductor device includes a semiconductor structure including a first conductivity-type semiconductor layer, a second conductivity-type semiconductor layer, and an active layer disposed between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer, and a lower portion of the semiconductor structure. A semiconductor device package including a conductive substrate disposed on and electrically connected to the first conductivity-type semiconductor layer, and an electrode pad electrically connected to the second conductivity-type semiconductor layer.
According to claim 1,
The plurality of pads
It includes a first pad, a second pad, and a third pad disposed between the first pad and the second pad,
The semiconductor device package, wherein the semiconductor device, the third electrode, the heat dissipation member, and the third pad overlap in a vertical direction.
According to claim 9,
The semiconductor device package of claim 1 , wherein a width of the third pad is greater than widths of the semiconductor element, the third electrode, and the heat dissipation member.
According to claim 1,
The body is a semiconductor device package including Al ₂ O ₃ .
According to claim 1,
The semiconductor device package of claim 1 , wherein the first ceramic layer and the second ceramic layer have a thickness of 60 μm or less.

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