KR102520027B1 - Organic light emitting display panel, organic light emitting display device, line driving circuit, image driving method, and sensing method - Google Patents

Abstract

The present embodiments relate to an organic light emitting display panel, an organic light emitting display device, a line driving circuit, an image driving method, and a sensing method, and more particularly, a custom of supplying an image signal to a corresponding subpixel through one data line. A new concept subpixel structure and its driving method that supply two column voltages to one subpixel through two column lines to express a desired image by breaking away from the conventional method, and alternating two column lines However, through a new signal line connection structure designed in such a way that each column line is shared by two adjacent subpixels, the number of signal lines in the column direction is reduced and effective image driving and sensing driving are possible. It relates to a light emitting display device, a line driving circuit, an image driving method, and a sensing method.

Description

Organic light emitting display panel, organic light emitting display device, line driving circuit, image driving method and sensing method

The present embodiments relate to an organic light emitting display panel, an organic light emitting display device, a line driving circuit, an image driving method, and a sensing method.

Recently, an organic light emitting display device that has been in the limelight as a display device uses an organic light emitting diode (OLED) that emits light by itself, and has advantages such as fast response speed, luminous efficiency, luminance, and viewing angle.

An organic light emitting display panel of such an organic light emitting display device includes an organic light emitting diode, a driving transistor for driving the diode, and two or more transistors for controlling voltages of a gate node and a source node (drain node) of the driving transistor, respectively. Subpixels are arranged in a matrix form.

In order to drive each subpixel according to such a subpixel structure, many signal lines must be arranged in an organic light emitting display panel.

For this reason, not only is it difficult to manufacture the organic light emitting display panel, but also the possibility of occurrence of signal line defects may increase accordingly.

In addition, in order to reduce the number of signal lines, if a structure is made in which several subpixels share one specific signal line, sensing driving for several subpixels sharing a specific signal line cannot be performed simultaneously, so that each subpixel A problem that takes too much time to sense a characteristic value (eg, threshold voltage, mobility) of the driving transistor or a characteristic value (eg, threshold voltage) of an organic light emitting diode may also occur.

As described above, various problems that may occur due to an increase in the number of signal lines due to a sub-pixel structure in an organic light emitting display panel may become more severe as a high-resolution, large-sized panel is used.

An object of the present embodiments is an organic light emitting display panel designed with a new concept subpixel structure (signal line connection structure for subpixels) capable of reducing the number of signal lines, and a subpixel having this new concept subpixel structure. An object of the present invention is to provide a line driving circuit for driving, an organic light emitting display device including the same, an image driving method, and a sensing method.

Another object of the present embodiments is to provide an organic light emitting display panel, an organic light emitting display device, a line driving circuit, an image driving method, and a sensing method capable of reducing the number of signal lines and reducing the sensing time.

Another object of the present embodiments is to provide an organic light emitting display panel having a high aperture ratio, an organic light emitting display device, a line driving circuit, an image driving method, and a sensing method.

In one aspect, in the present embodiments, a plurality of column lines including a plurality of first column lines and a plurality of second column lines are disposed in a column direction, and a plurality of row lines are disposed in a row direction. an organic light emitting display panel in which a plurality of subpixels are arranged in a matrix type, a column line driving circuit for driving a plurality of first column lines and a plurality of second column lines, and a row line for driving a plurality of row lines An organic light emitting display device including a driving circuit may be provided.

In such an organic light emitting display device, each subpixel includes an organic light emitting diode, a driving transistor for driving the organic light emitting diode, a first transistor electrically connected between a first node of the driving transistor and a first column line, and a driving transistor. It may include a second transistor electrically connected between the second node of the transistor and the second column line, and a storage capacitor electrically connected between the first node and the second node of the driving transistor.

Also, in such an organic light emitting display device, the first column line and the second column line are alternately positioned, the first column line is positioned between the ith subpixel column and the i+1th subpixel column, and the second column line is It may be positioned between the i+1 th subpixel column and the i+2 th subpixel column.

In another aspect, the present embodiments include a plurality of first column lines disposed in a column direction, a plurality of second column lines disposed in a column direction, and a plurality of row lines disposed in a row direction and an organic light emitting display panel including a plurality of subpixels arranged in a matrix type.

In such an organic light emitting display panel, each of a plurality of subpixels is electrically connected between an organic light emitting diode, a driving transistor for driving the organic light emitting diode, and a first node of the driving transistor and a first column line. It may include a connected first transistor, a second transistor electrically connected between a second node of the driving transistor and a second column line, and a storage capacitor electrically connected between the first node and the second node of the driving transistor.

In this organic light emitting display panel, the first column line and the second column line are alternately positioned, the first column line is positioned between the ith subpixel column and the i+1th subpixel column, and the second column line is positioned between the i+1th subpixel column. It may be positioned between the 1st subpixel column and the i+2th subpixel column.

In another aspect, the present embodiments, K digital-analog converters, K output buffers connected corresponding to the K digital-analog converters, and M + N switching connections between the K output buffers and the K column lines ( M+N=K, M, N are natural numbers greater than or equal to 1) column voltage switches, analog-to-digital converters, M first column lines included in the K column lines, and N second column lines among the N second column lines A line driving circuit may include N sampling switches for switching connections between the column lines and analog-to-digital converters, and at least one initialization switch for switching connections between the N second column lines and an initialization voltage supply node.

In another aspect, according to the present embodiments, a method for driving an image of an organic light emitting display device includes applying a first column voltage to a first node of a driving transistor in an i th subpixel through a first column line, and applying a first column voltage to a second column line A first step of applying a second column voltage to the second node of the driving transistor in the i-th subpixel through , a second step of floating the first node and the second node of the driving transistor in the i-th subpixel, and i A third step of emitting light from the organic light emitting diode in the th sub-pixel may be included.

In this image driving method, the first step is to apply the first column voltage to the first node of the driving transistor in the i-th sub-pixel through the first column line, in the i+1-th sub-pixel through the first column line. When the first column voltage is simultaneously applied to the first node of the driving transistor and the second column voltage is applied to the second node of the driving transistor in the i-th subpixel through the second column line, i through the second column line. The second column voltage may be simultaneously applied to the second node of the driving transistor in the -1st subpixel.

In another aspect, according to the present embodiments, the sensing method of the organic light emitting display device includes a first node of a driving transistor in an ith subpixel and a first node of a driving transistor in an i+1th subpixel through a first column line. The first column voltage for sensing is simultaneously applied to the node, the initialization voltage is applied to the second node of the driving transistor in the i-th sub-pixel through a second column line, and the i+1-th sub-pixel is applied through another second column line. A first step of applying an initialization voltage to the second node of the driving transistor, a second step of simultaneously floating the second node of the driving transistor in the ith subpixel and the second node of the driving transistor in the i+1th subpixel; , sensing the voltage of the second node of the driving transistor in the i-th sub-pixel through a second column line, and sensing the voltage of the second node of the driving transistor in the i+1-th sub-pixel through another second column line. It can include 3 steps.

In another aspect, in the present embodiments, a plurality of column lines including a plurality of first column lines and a plurality of second column lines are disposed in a column direction, and a plurality of row lines in a row direction an organic light emitting display panel in which subpixels including an organic light emitting diode, a driving transistor driving the organic light emitting diode, and a storage capacitor electrically connected between a first node and a second node of the driving transistor are arranged in a matrix type; a column line driving circuit for driving a plurality of first column lines and a plurality of second column lines; and a row line driving circuit for driving a plurality of row lines.

In such an organic light emitting display device, the first column line and the second column line may be alternately positioned.

In addition, in the organic light emitting display device, in the i-th sub-pixel column, the i+1-th sub-pixel column, and the i+2-th sub-pixel column, the first node of the driving transistor of the sub-pixel located in the i-th sub-pixel column and A first node of a driving transistor of a subpixel located in an i+1th subpixel column is electrically connected at a first connection point, and a first transistor is electrically connected between the first connection point and a first column line, i The second node of the driving transistor of the subpixel located in the +1st subpixel column is electrically connected to the second node of the driving transistor of the subpixel located in the i+2th subpixel column at a second connection point, and A second transistor may be electrically connected between the point and the second column line.

According to the present embodiments as described above, an organic light emitting display panel designed with a new concept subpixel structure (signal line connection structure for subpixels) capable of reducing the number of signal lines, and this new concept subpixel structure It is possible to provide a line driving circuit for driving a subpixel having , an organic light emitting display device including the line driving circuit, and an image driving method and sensing method thereof.

In addition, according to the present embodiments, it is possible to provide an organic light emitting display panel, an organic light emitting display device, a line driving circuit, an image driving method, and a sensing method capable of reducing the number of signal lines and reducing the sensing time.

According to the present embodiments, an organic light emitting display panel having a high aperture ratio, an organic light emitting display device, a line driving circuit, an image driving method, and a sensing method may be provided.

1 is a system configuration diagram of an organic light emitting display device according to the present embodiments.
2 is an exemplary view of the arrangement of column lines of an organic light emitting display panel according to example embodiments.
3 is an exemplary diagram of a sub-pixel structure of an organic light emitting display panel according to the present embodiments.
FIG. 4 is a diagram illustrating eight subpixels having the subpixel structure of FIG. 3 in the organic light emitting display panel according to the present embodiments.
5 is a diagram showing configurations of eight sub-pixels and column line driving circuits in an organic light emitting display panel according to the present embodiments.
6 to 8 are diagrams for explaining the image driving principle of the organic light emitting display device according to the present embodiments.
9 is a diagram illustrating a column line driving circuit according to the present embodiments.
10 is a flowchart of a method for driving an image of an organic light emitting display device according to example embodiments.
11 to 13 are diagrams illustrating an image driving procedure of an organic light emitting display device according to the present exemplary embodiments.
14 is a flowchart of a sensing method of an organic light emitting display device according to example embodiments.
15 is a timing diagram of sensing a threshold voltage of an organic light emitting display device according to example embodiments.
16 to 18 are diagrams illustrating a threshold voltage sensing procedure in a first threshold voltage sensing section.
19 to 21 are diagrams illustrating a threshold voltage sensing procedure in a second threshold voltage sensing section.
22 is a timing diagram for sensing mobility of an organic light emitting display device according to the present embodiments.
23 to 25 are diagrams illustrating a mobility sensing procedure in a first mobility sensing section.
26 to 28 are diagrams illustrating a mobility sensing procedure in a second mobility sensing section.
29 is a diagram illustrating functional redundancy of the first transistor and the second transistor in the organic light emitting display device according to the present embodiments.
30 and 31 are diagrams illustrating a structure for reducing the number of transistors in an organic light emitting display device according to the present embodiments.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Some embodiments of the present invention are described in detail below with reference to exemplary drawings. In adding reference numerals to components of each drawing, the same components may have the same numerals as much as possible even if they are displayed on different drawings. In addition, in describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

Also, terms such as first, second, A, B, (a), and (b) may be used in describing the components of the present invention. These terms are only used to distinguish the component from other components, and the nature, sequence, order, or number of the corresponding component is not limited by the term. When an element is described as being “connected,” “coupled to,” or “connected” to another element, that element is or may be directly connected to that other element, but intervenes between each element. It will be understood that may be "interposed", or each component may be "connected", "coupled" or "connected" through other components.

1 is a system configuration diagram of an organic light emitting display device 100 according to the present embodiments, FIG. 2 is an example of column line arrangement of the organic light emitting display panel 110 according to the present embodiments, and FIG. It is an exemplary diagram of a sub-pixel structure of the organic light emitting display panel 110 according to the exemplary embodiments.

Referring to FIG. 1 , an organic light emitting display device 100 according to the present embodiments includes a plurality of column lines (CL) disposed in a column direction and a plurality of row lines (RL) in a row direction. ) are disposed and a plurality of subpixels (SP) are arranged in a matrix type, an organic light emitting display panel 110, a column line driving circuit 120 for driving a plurality of column lines CL, and a plurality of row lines. and a row line driving circuit 130 that drives (RL), a controller 140 that controls the column line driving circuit 120 and the row line driving circuit 130, and the like. However, in this specification, a column direction and a row direction are relative concepts determined according to a viewing direction, and in some models, a column line may be a row line, and a row line may be a column line.

Referring to FIG. 2 , the plurality of column lines CL includes a plurality of first column lines CL1 and a plurality of second column lines CL2 .

Since a plurality of subpixels SP are arranged in a matrix type in the organic light emitting display panel 110, as shown in FIG. -1), i-th sub-pixel column (SPC #i), i+1-th sub-pixel column (SPC #i+1), i+2-th sub-pixel column (SPC #i+2), i+3-th sub-pixel column Pixel column (SPC #i+3), i+4th sub-pixel column (SPC #i+4), i+5th sub-pixel column (SPC #i+5), i+6th sub-pixel column (SPC # i+6) and the like exist. Here, i is an index representing a subpixel column.

Referring to FIG. 2 , the first column line CL1 and the second column line CL2 are alternately positioned.

The first column line CL1 is between the i-th sub-pixel column SPC #i and the i+1-th sub-pixel column SPC #i+1, and the i+2-th sub-pixel column SPC #i+2. ) and the i+3 sub-pixel column (SPC #i+3), and between the i+4-th sub-pixel column (SPC #i+4) and the i+5-th sub-pixel column (SPC #i+5) Located.

The second column line CL2 is between the i−1 th subpixel column SPC #i−1 and the i th subpixel column SPC #i, and the i+1 th subpixel column SPC #i+1 ) and the i+2-th sub-pixel column (SPC #i+2), between the i+3-th sub-pixel column (SPC #i+3) and the i+4-th sub-pixel column (SPC #i+4), , It is located between the i+5th subpixel column (SPC #i+5) and the i+6th subpixel column (SPC #i+6).

Referring to FIG. 3 , each subpixel SP includes an organic light emitting diode OLED, a driving transistor DRT for driving the organic light emitting diode OLED, and a first node N1 of the driving transistor DRT. ) and the first column line CL1, and a second transistor electrically connected between the second node N2 of the driving transistor DRT and the second column line CL2. (T2) and a storage capacitor (Cst) electrically connected between the first node (N1) and the second node (N2) of the driving transistor (DRT).

An organic light emitting diode (OLED) may include a first electrode (eg, an anode electrode), an organic layer, and a second electrode (eg, a cathode electrode).

The driving transistor DRT drives the organic light emitting diode (OLED) by supplying a driving current to the organic light emitting diode (OLED).

In the driving transistor DRT, the first node N1 may be electrically connected to a source node or a drain node of the switching transistor SWT and may be a gate node. The second node N2 may be electrically connected to the first electrode of the organic light emitting diode OLED, and may be a source node or a drain node. The third node N3 may be electrically connected to a driving voltage line (DVL) that supplies the driving voltage EVDD, and may be a drain node or a source node.

The first transistor T1 may be controlled by receiving the scan signal SCAN to a gate node.

The first transistor T1 is turned on by the scan signal SCAN and supplies the first column voltage CV1 supplied from the first column line CL1 to the first node N1 of the driving transistor DRT. can deliver

The second transistor T2 may be controlled by receiving a sensing signal SENSE, which is a kind of scan signal, as a gate node.

The second transistor T2 is turned on by the sensing signal SENSE and transmits the second column voltage CV2 supplied through the first column line CL2 to the second node N2 of the driving transistor DRT. authorize it to

The storage capacitor Cst may be electrically connected between the first node N1 and the second node N2 of the driving transistor DRT.

The storage capacitor Cst is not a parasitic capacitor (eg, Cgs or Cgd) that is an internal capacitor existing between the first node N1 and the second node N2 of the driving transistor DRT, but It is an external capacitor intentionally designed outside the driving transistor (DRT).

Meanwhile, the driving transistor DRT, the first transistor T1 and the second transistor T3 may be implemented as n-type or p-type as in the example of FIG. 3 .

Meanwhile, the scan signal SCAN and the sensing signal SENSE may be separate gate signals. In this case, the scan signal SCAN and the sensing signal SENSE may be respectively applied to the gate node of the first transistor T1 and the gate node of the second transistor T3 through different gate lines.

In some cases, the scan signal SCAN and the sensing signal SENSE may be the same gate signal. In this case, the scan signal SCAN and the sensing signal SENSE may be commonly applied to the gate node of the first transistor T1 and the gate node of the second transistor T3 through the same gate line.

As described above, the number of column lines CL disposed in the column direction of the organic light emitting display panel 110 may be reduced.

As such, as the number of column lines CL disposed on the organic light emitting display panel 110 is reduced, the number of voltage outputs of the column line driving circuit 120 driving the plurality of column lines CL is reduced. Therefore, the simple and small design of the column line driving circuit 120 can be achieved.

Meanwhile, the controller 140 controls the column line driving circuit 120 and the row line driving circuit 130 by supplying various control signals to the column line driving circuit 120 and the row line driving circuit 130 .

The controller 140 starts scanning according to the timing implemented in each frame, converts input image data input from the outside to match the signal format used by the column line driving circuit 120, and outputs the converted data. , data drive is controlled at an appropriate time according to the scan.

The controller 140 may be a timing controller used in a typical display technology or a control device that further performs other control functions including a timing controller.

The column line driving circuit 120 supplies a first column voltage CV1 and a second column voltage CV2 to a plurality of first column lines CL and a plurality of second column lines CL2, thereby providing a plurality of The first column line CL and the plurality of second column lines CL2 are driven. Here, the column line driving circuit 120 is also referred to as a 'data driver' or a 'source driver'.

The column line driving circuit 120 may include at least one column line driving integrated circuit to drive a plurality of first column lines CL and a plurality of second column lines CL2 .

The column line driving integrated circuit is also referred to as a source driver integrated circuit (SDIC).

The row line driving circuit 130 sequentially drives the plurality of row lines RL by sequentially supplying a row signal to the plurality of row lines RL. Here, the low line driving circuit 130 is also referred to as a 'scan driver' or a 'gate driver'.

The low line driving circuit 130 may include at least one low line driving integrated circuit.

The plurality of row lines RL are also referred to as gate lines, and the low signal is also referred to as a scan signal. Also, the low line driver integrated circuit is also referred to as a gate driver integrated circuit (GDIC).

The low line driving circuit 130 sequentially supplies a low signal (scan signal) of an on voltage or an off voltage to a plurality of row lines RL under the control of the controller 140 .

When a specific row line is opened by the row line driving circuit 130, the column line driving circuit 120 converts the data received from the controller 140 into an analog voltage to output the plurality of first column lines CL1 and the plurality of column lines CL1. It is supplied to the column line (CL2).

The column line driving circuit 120 is located on only one side (eg, upper or lower side) of the organic light emitting display panel 110 in FIG. (e.g., upper and lower sides) may be located both.

Although the row line driving circuit 130 is located only on one side (eg, the left or right side) of the organic light emitting display panel 110 in FIG. It may be located on both sides (eg, left and right).

FIG. 4 shows eight subpixels (SPi−1, SPi, SPi+1, …, SPi+6) having the same subpixel structure as shown in FIG. 3 in the organic light emitting display panel 110 according to the present embodiments. it is a drawing

Referring to FIG. 4 , in a region where eight subpixels (SPi-1, SPi, SPi+1, ..., SPi+6) exist, nine column lines (CL1A, CL2B, CL1C, CL2D, CL1E, CL2F, CL1G, CL2H, CL1I) are present.

Referring to FIG. 4 , nine column lines (CL1A, CL2B, CL1C, CL2D, CL1E, CL2F, CL1G, CL2H, and CL1I) include five first column lines (CL1A, CL1C, CL1E, CL1G, and CL1I) and four column lines (CL1A, CL1C, CL1E, CL1G, and CL1I). It includes second column lines CL2B, CL2D, CL2F, and CL2H.

Each of the five first column lines CL1A, CL1C, CL1E, CL1G, and CL1I delivering the first column voltages CV1A, CV1C, CV1E, CV1G, and CV1I is connected to the first transistor T1 of two adjacent subpixels. connected in common

In addition, each of the four second column lines CL2B, CL2D, CL2F, and CL2H transmitting the second column voltages CV2B, CV2D, CV2F, and CV2H is common to the second transistor T2 of the two adjacent subpixels. Connected.

For example, the first column line CL1C is connected to the drain node or the source node of the first transistor T1 of the subpixel SPi located in the ith subpixel column SPC #i and the i+1th subpixel column. It may be commonly connected to a drain node or a source node of the first transistor T1 of the subpixel SPi+1 located at (SPC #i+1). Here, the first column line CL1C is located between the ith subpixel column SPC #i and the i+1th subpixel column SPC #i+1.

The second column line CL2 is connected to the drain node or source node of the second transistor T2 of the sub-pixel SPi+1 located in the i+1-th sub-pixel column SPC #i+1 and the i+2-th sub-pixel column SPC #i+1. A drain node or a source node of the second transistor T2 of the subpixel SPi+2 located in the pixel column SPC #i+2 may be connected in common. Here, the second column line CL2 is positioned between the i+1 th subpixel column SPC #i+1 and the i+2 th subpixel column SPC #i+2.

As described above, the first column voltage (eg, CV1C) output from the column line driving circuit 120 is transmitted through one first column line (eg, CV1C) to two subpixels (eg, SPi and SPi). +1) to the first node N1 of the driving transistor DRT of the two subpixels (eg, SPi and SPi+1) through the first transistor T1.

In addition, the second column voltage (eg, CV2B) output from the column line driving circuit 120 is applied to two subpixels (eg, SPi-1, SPi+) through one second column line (eg, CL2B). Through the second transistor T2 of 1), the second node N2 of the driving transistor DRT of the two subpixels (eg, SPi-1 and SPi+1) may be transmitted together.

Accordingly, a column-direction signal line for applying the first column voltage CV1 and the second column voltage CV2 to the first node N1 and the second node N2 of the driving transistor DRT of each subpixel. number can be reduced.

5 is a diagram showing eight sub-pixels (SPi-1, SPi, SPi+1, ..., SPi+6) and a column line driving circuit configuration in the organic light emitting display panel 110 according to the present exemplary embodiments.

According to the above-described column line structure, a desired luminance is expressed in a corresponding subpixel by the first column voltage CV1 and the second column voltage CV2 applied to both ends of the storage capacitor Cst.

Accordingly, the controller 140 divides the image data corresponding to the corresponding subpixel into first column data and second column data and provides the divided image data to the column line driving circuit 120, which then divides the first column data into second column data. is converted into a first column voltage CV1 and second column data is converted into a second column voltage CV2 and output to the corresponding first column line CL1 and second column line CL2.

Accordingly, as shown in FIG. 5 , each of the five first column lines CL1A, CL1C, CL1E, CL1G, and CL1I and the four second column lines CL2B, CL2D, CL2F, and CL2H is a digital-to-analog converter (DAC). ) and electrically connected.

Accordingly, the first column voltage CV1 and the second column voltage CV2 may be used as image signals under the subpixel structure according to the present exemplary embodiments.

Meanwhile, referring to FIG. 5 , the organic light emitting display device 100 according to the present exemplary embodiments includes five first column lines CL1A, CL1C, CL1E, CL1G, and CL1I and four second column lines CL2B, A column voltage switch (SCV) for switching a connection with a digital-to-analog converter (DAC) may be included for each of CL2D, CL2F, and CL2H.

Using the column voltage switch (SCV), five first column lines (CL1A, CL1C, CL1E, CL1G, and CL1I) and four second column lines (CL2B, CL2D) are connected according to driving conditions such as image driving or sensing driving. , CL2F, CL2H), whether to supply column voltage to each of them can be controlled.

The aforementioned column voltage switch SCV may be included inside the column line driving circuit 120 , for example.

Meanwhile, as shown in FIG. 5 , the four second column lines CL2B, CL2D, CL2F, and CL2H may be electrically connected to one or more analog-to-digital converters ADC.

Here, the analog-to-digital converter ADC may convert at least one voltage (analog voltage) of the four second column lines CL2B, CL2D, CL2F, and CL2H into a digital value.

Such an analog-to-digital converter (ADC) is for sensing (determining) the characteristic value (eg, threshold voltage, mobility) of the driving transistor (DRT) or the characteristic value (eg, threshold voltage) of the organic light emitting diode (OLED) in the subpixel. It may be a sensing configuration.

Therefore, the characteristics of circuit elements (driving transistors, organic light emitting diodes) in two sub-pixels (eg SPi, SPi+1) commonly connected to one first column line (eg CL1C) : CL2B, CL2D), they can be distinguished from each other and sensed simultaneously. Accordingly, the time required to sense characteristic values of all the driving transistors (or organic light emitting diodes) disposed on the organic light emitting display panel 110 may be shortened.

Meanwhile, referring to FIG. 5 , in the organic light emitting display device 100 according to the present exemplary embodiments, each of the four second column lines CL2B, CL2D, CL2F, and CL2H is connected to the initialization voltage supply node Npre. A switching initialization voltage switch (SPRE) may be included.

For example, when the initialization voltage switch SPRE connected to the second column line CL2D is turned on, the initialization voltage Vpre is supplied to the second column line CL2D.

At this time, when the second transistors T2 of each of the subpixels SPi+1 and SPi+2 simultaneously connected to the second column line CL2D are turned on, the subpixels SPi+1 simultaneously connected to the second column line CL2D , SPi+2) The initialization voltage Vpre is also applied to the second node N2 of each driving transistor DRT.

Here, the initialization voltage Vpre may be an initialization voltage for sensing driving applied to the second node N2 of the driving transistor DRT in an initialization phase (also referred to as a sensing initialization phase or a program phase) during sensing driving. .

Also, referring to FIG. 5 , the organic light emitting display device 100 according to the present exemplary embodiments switches the connection between each of the four second column lines CL2B, CL2D, CL2F, and CL2H and the analog-to-digital converter ADC. A sampling switch (SAM) may be further included.

The sampling switch SAM is a switch that allows the analog-to-digital converter (ADC) to sense the voltage of the corresponding second column line in a sampling step (also referred to as a sensing step) during sensing operation.

Here, the voltage sensed by the analog-to-digital converter ADC is the voltage of the second column line, and may be the voltage of the second node N2 of the driving transistor DRT in the subpixel connected to the second column line. It may be the voltage charged in the line capacitor on the column line.

The voltage sensed by the analog-to-digital converter (ADC) may be a voltage reflecting characteristic values of circuit elements (driving transistors or organic light emitting diodes) within subpixels connected to the second column line.

Using the aforementioned initialization voltage switch SPRE, the voltage state of the second node N2 of the driving transistor DRT can be effectively controlled according to the sensing driving step.

In addition, by using the sampling switch (SAM), the analog-to-digital converter (ADC) can perform voltage sensing at a necessary time according to the sensing drive.

As such, the initialization voltage switch SPRE and the sampling switch SAM required for sensing driving may be included inside the column line driving circuit 120 , for example.

Hereinafter, image driving and sensing driving of the organic light emitting display device 100 having the aforementioned subpixel structure and column line arrangement structure and the column line driving circuit 120 will be described.

6 to 8 are diagrams for explaining the image driving principle of the organic light emitting display device 100 according to the present embodiments.

First, the column line driving circuit 120 outputs the first column voltage CV1 through the first column line CL1 and outputs the second column voltage CV2 through the second column line CL2.

In this case, the difference ΔV between the first column voltage CV1 and the second column voltage CV2 is the first transistor T1 connected to the first column line CL1 and the second column connected to the second column line CL2. 2 Corresponds to the data voltage corresponding to the luminance to be expressed in the subpixel including the transistor T2.

In the past, an image was expressed using an image data voltage applied to the first node N1 corresponding to the gate node of the driving transistor DRT, but in the organic light emitting display device 100 according to the present embodiments, the driving transistor DRT ) using a difference (ΔV) between the first column voltage CV1 applied to the first node N1 and the second column voltage CV2 applied to the second node N2 of the driving transistor DRT. There is a difference in terms of expression.

Due to this difference, conventionally, one column-direction data line is required for each sub-pixel column to transfer the image data voltage to the first node N1 of the driving transistor DRT of each sub-pixel.

However, according to the present exemplary embodiments, the first column voltage CV1 is applied to the first node N1 of the driving transistor DRT of two adjacent subpixels by using one first column line CL1. and transfers the second column voltage CV2 to the second node N2 of the driving transistor DRT of the two adjacent subpixels using one second column line CL2 to express a desired image. It is only necessary to create a potential difference ΔV between the first node N1 and the second node N2 of the driving transistor DRT. Accordingly, it is possible to reduce the number of signal lines in the column direction while enabling the same image representation compared to the conventional method.

In order to explain the above description as an example, as shown in FIG. 6, the i−1 th subpixel (SPi−1), the ith subpixel (SPi), the i+1 th subpixel (SPi+1), i The +2 th subpixel (SPi+2) is taken as an example.

Here, the i-1th subpixel (SPi-1) means an arbitrary subpixel located in the i-1th subpixel column (SPC #i-1). The i-th subpixel SPi refers to an arbitrary subpixel located in the i-th subpixel column SPC #i. The i+1th subpixel (SPi+1) means an arbitrary subpixel located in the i+1th subpixel column (SPC #i+1). The i+2th subpixel (SPi+2) means an arbitrary subpixel located in the i+2th subpixel column (SPC #i+2).

Referring to FIG. 6 , the i−1 th subpixel SPi−1, the i th subpixel SPi, the i+1 th subpixel SPi+1, and the i+2 th subpixel SPi+2, respectively. assumes that image data voltages of 2V, 3V, 1V, and 3V are required for desired image expression.

Here, the image data voltages of 2V, 3V, 1V, and 3V may refer to image data voltages applied to the first node N1 of the driving transistor DRT when the existing subpixel structure and the existing data line are used. .

Referring to FIG. 7 , the i−1 th subpixel SPi−1, the i th subpixel SPi, the i+1 th subpixel SPi+1, and the i+2 th subpixel SPi+2, respectively. For the desired image expression (luminance expression) of , the column line driving circuit 120 outputs a first column voltage CV1A of 3V to the first column line CL1A and a second column voltage of 1V to the second column line CL2B. outputs the voltage CV2B, outputs the first column voltage CV1C of 4V to the first column line CL1C, outputs the second column voltage CV2D of 3V to the second column line CL2D, and outputs the first column voltage CV2D to the first column line CL2D. A first column voltage CV1E of 6V may be output to CL1E.

Accordingly, the potential difference between the first node N1 and the second node N2 of the driving transistor DRT of the i−1 th subpixel SPi−1 (that is, the potential difference between both ends of the storage capacitor Cst) is It becomes 2V corresponding to the image expression to be expressed in the i-1th subpixel (SPi-1).

The potential difference between the first node N1 and the second node N2 of the driving transistor DRT of the i-th sub-pixel SPi (ie, the potential difference between both ends of the storage capacitor Cst) is the i-th sub-pixel SPi 3V corresponding to the image expression to be expressed in .

The potential difference between the first node N1 and the second node N2 of the driving transistor DRT of the i+1th sub-pixel SPi+1 (that is, the potential difference between both ends of the storage capacitor Cst) is i+1. It becomes 1V corresponding to the image expression to be expressed in the th sub-pixel (SPi+1).

The potential difference between the first node N1 and the second node N2 of the driving transistor DRT of the i+2-th sub-pixel SPi+2 (that is, the potential difference between both ends of the storage capacitor Cst) is i+2. It becomes 3V corresponding to the image expression to be expressed in the th sub-pixel (SPi+2).

Referring to FIG. 8 , the controller 140 includes an i−1 th subpixel SPi−1, an i th subpixel SPi, an i+1 th subpixel SPi+1, and an i+2 th subpixel. For each (SPi+2), the first node N1 and the second node of the driving transistor DRT are reflected by sensing and compensating the threshold voltage, mobility, panel luminance, etc. of the driving transistor DRT. A potential difference to be applied between (N2) is generated as a table 810.

Based on the table 810 thus generated, the i−1 th subpixel SPi−1, the i th subpixel SPi, the i+1 th subpixel SPi+1, and the i+2 th subpixel SPi A voltage table 820 is generated by calculating voltages to be supplied to the column lines CL1A, CL2B, CL1C, CL2D, and CL1E related to +2).

In this case, the voltage to be supplied to the other column lines (eg, CL1A, CL2B, CL2D, and CL1E) may be calculated by calculating the voltage to be supplied to a specific column line (eg, CL1C) as 1V.

The final column voltage table 830 is obtained by checking the minimum voltage in the voltage table 820 generated in this way and performing offset processing so that the checked minimum voltage (-2V) becomes a desired voltage (eg, 1V). can create

For example, when +3V offset is applied, the final column voltage table 830 in which 0V, -2V, 1V, 0V, and 3V in the voltage table 820 is changed to 3V, 1V, 4V, 3V, and 6V is is created

In the column voltage table 830, the i−1 th subpixel SPi−1, the i th subpixel SPi, the i+1 th subpixel SPi+1, and the i+2 th subpixel SPi+ 2) column data corresponding to the column voltages 3V, 1V, 4V, 3V, and 6V to be supplied to the column lines CL1A, CL2B, CL1C, CL2D, and CL1E to the column line driving circuit 120 to provide.

Meanwhile, referring to FIGS. 7 and 8 , the column voltage may tend to gradually increase due to column line sharing. Accordingly, a higher driving voltage EVDD is required. This can be improved by applying a specific voltage (eg, 0.2V) to the black data by taking advantage of the fact that a black image is obtained even when a negative (-) voltage is applied to the storage capacitor Cst.

9 is a diagram showing a column line driving circuit 120 according to the present embodiments.

The column line driving circuit 120 according to the present embodiments includes M channels corresponding to the M first column lines and N channels corresponding to the N second column lines, K (K=M+ N, M, N is a natural number greater than or equal to 1, and K is a natural number greater than or equal to 2) channels.

As shown in FIG. 9 , when K=5, M=3, and N=2, the column line driving circuit 120 has three channels corresponding to the three first column lines CL1A, CL1C, and CL1E. 5 channels (CH A, CH B, CH including CH A, CH C, CH E) and two channels (CH B, CH D) corresponding to the two second column lines (CL2B, CL2D) C, CH D, CH E).

Referring to FIG. 9 , the column line driving circuit 120 includes 5 (K=5) first latches L1 and 5 (K=5) second latches L2, and 5 (K=5) second latches L2. It includes two digital-to-analog converters (DACs) and five (K=5) output buffers (AMPs).

5 (K = 5) first latches (L1) and 5 (K = 5) second latches (L2), 5 (K = 5) digital-to-analog converters (DACs), 5 (K = 5) The number of output buffers AMP corresponds to 5 (K=5) channels.

5 (K=5) first latches L1 and 5 (K=5) second latches L2 store column data, and according to the example of FIG. 8 , the column voltages 3V and 1V , 4V, 3V, 6V) are stored.

Referring to FIG. 9 , the column line driving circuit 120 includes five output buffers AMP and five (K=5) column lines CL1A, CL2B, and CL1C connected to the five digital-to-analog converters (DACs). , CL2D, and CL1E) may include 5 (M+N=3+2) column voltage switches (SCVs) for switching connections.

In addition, the column line driving circuit 120 may include a sample and holder circuit (S/H) and at least one analog-to-digital converter (ADC), and may include five column lines CL1A, CL2B, CL1C, CL2D, Two second column lines (CL2B, CL2D) and an analog-to-digital converter (ADC) may further include N sampling switches (SAM) for switching.

In addition, the column line driving circuit 120 may include at least one initialization switch SPRE for switching a connection between the two second column lines CL2B and CL2D and the initialization voltage supply node Npre.

Referring to FIG. 9 , three first column lines CL1A, CL1C, and CL1E and two second column lines CL2B and CL2D are alternately positioned. That is, the first column line CL1A, the second column line CL2B, the first column line CL1C, the second column line CL2D, and the first column line CL1E are located in this order.

Using the aforementioned column line driving circuit 120, data driving for subpixels having a unique subpixel structure capable of reducing the number of signal lines in a column direction can be provided, as in the present embodiments.

10 is a flowchart of an image driving method of the organic light emitting display device 100 according to the present embodiments, and FIGS. 11 to 13 illustrate image driving procedures of the organic light emitting display device 100 according to the present embodiments. it is a drawing

Referring to FIG. 10 , in the image driving method of the organic light emitting display device 100 according to the present embodiments, a first step (S1010), also called a programming step or emission initialization step, and a second step, also called a sensing step or a plotting step, are performed. (S1020), and proceeds to a third step (S1030) corresponding to the light emitting step.

Below, three steps (S1010, S1020, and S1030) for image driving will be described with reference to FIGS. 11 to 13.

However, it will be exemplarily described in terms of image driving for the i-th sub-pixel SPi.

Also, it is assumed that two row lines RL1 and RL2 are disposed in four subpixels SPi−1, SPi, SPi+1, and SPi+2. Accordingly, the scan signal SCAN is applied to the gate node of the first transistor T1 through the row line RL1, and the sensing signal SENSE is applied to the gate node of the second transistor T2 through the row line RL2. .

Referring to FIG. 11 , in the first step S1010, the scan signal SCAN capable of turning on the first transistor T1 and the second transistor T3 through two row lines RL1 and RL2 and when the sensing signal SENSE is applied, the column line driving circuit 120 connects to the first node N1 of the driving transistor DRT in the ith subpixel SPi through the first column line CL1C. The first column voltage CV1C is applied, and the second column voltage CV2B is applied to the second node N2 of the driving transistor DRT in the ith subpixel SPi through the second column line CL2B. do.

At this time, the column voltage switches SCV between the first column line CL1C and the digital-to-analog converter DAC and between the second column line CL2B and the digital-to-analog converter DAC are turned on.

Referring to FIG. 12 , in a second step S1020, the first node N1 and the second node N2 of the driving transistor DRT in the i-th sub-pixel SPi are floated.

Accordingly, while maintaining the potential difference (CV1C-CV2B) between the first node N1 and the second node N2 of the driving transistor DRT, the voltage of the first node N1 of the driving transistor DRT increases at CV1C. This is done, and the voltage of the second node N2 of the driving transistor DRT rises at CV2B.

At this time, the column voltage switches SCV between the first column line CL1C and the digital-to-analog converter DAC and between the second column line CL2B and the digital-to-analog converter DAC are turned off.

Referring to FIG. 12 , in the second step S1020, while maintaining the potential difference ΔVi between the first node N1 and the second node N2 of the driving transistor DRT in the ith subpixel SPi, While the voltages of the first node N1 and the second node N2 of the driving transistor DRT in the i-th sub-pixel SPi increase, the first electrode (eg, the anode electrode) and When the voltage of the second node N2 of the connected driving transistor DRT increases by a voltage capable of supplying current to the organic light emitting diode OLED, current starts to flow to the organic light emitting diode OLED.

Accordingly, as shown in FIG. 13 , a third step ( S1030 ) of emitting light from the organic light emitting diode (OLED) in the i-th sub-pixel (SPi) proceeds.

Meanwhile, referring to FIG. 11 , in a first step S1010, a first column voltage is applied to the first node N1 of the driving transistor DRT in the ith subpixel SPi through the first column line CL1C. When (CV1C) is applied, the same first column voltage CV1C is applied to the first node N1 of the driving transistor DRT in the i+1 th subpixel SPi+1 through the same first column line CL1C. ) are applied simultaneously.

In addition, in a first step S1010, the second column voltage CV2B is applied to the second node N2 of the driving transistor DRT in the ith sub-pixel SPi through the second column line CL2B. In this case, the same second column voltage CV2B is simultaneously applied to the second node N2 of the driving transistor DRT in the i−1 th subpixel SPi−1 through the same second column line CL2.

Accordingly, the second step (S1020) and the third step (S1030) are performed in the i-1 th subpixel SPi-1, the i th subpixel SPi, and the i+1 th subpixel SPi+1. goes on together

According to the above-described image driving method, it is possible to reduce the number of signal lines in a column direction while enabling desired image expression.

14 is a flowchart of a sensing method of the organic light emitting display device 100 according to the present embodiments.

Referring to FIG. 14 , in the sensing method of the organic light emitting display device 100 according to the present embodiments, a first step (S1410), also referred to as a sensing initialization step or a program step, information to be grasped (threshold voltage, mobility, etc.) ), the sensing step or the floating step in the sense that the voltage of a specific node is floated for this purpose (S1420), the sampling step and the third step (S1430) in which voltage sensing is actually performed, sensing voltage A fourth step (S1440) of identifying information (threshold voltage, mobility, etc.) to be identified based on is performed.

Below, it will be described in terms of sensing the i-th sub-pixel SPi.

In the first step S1410, the first node N1 of the driving transistor DRT in the ith subpixel SPi and the i+1th subpixel SPi+1 are connected through the first column line CL1C. The sensing first column voltage CV1C is simultaneously applied to the first node N1 of the driving transistor DRT.

To this end, the column voltage switch SCV connected to the first column line CL1C is turned on.

In addition, in the first step S1410, the initialization voltage Vpre is applied to the second node N2 of the driving transistor DRT in the i-th sub-pixel SPi through the second column line CL2B, and The initialization voltage Vpre is applied to the second node N2 of the driving transistor DRT in the i+1 th sub-pixel SPi+1 through the second column line CL2D.

To this end, the initialization switch SPRE connected to the second column lines CL2B and CL2D is turned on.

In the second step S1420, the second node N2 of the driving transistor DRT in the i-th sub-pixel SPi and the second node of the driving transistor DRT in the i+1-th sub-pixel SPi+1 Plot (N2) at the same time.

To this end, the initialization switch SPRE connected to the second column lines CL2B and CL2D is turned off.

Accordingly, the second node N2 of the driving transistor DRT in the i-th sub-pixel SPi and the second node N2 of the driving transistor DRT in the i+1-th sub-pixel SPi+1 are voltage rise takes place

In a third step S1430, the voltage of the second node N2 of the driving transistor DRT in the i-th sub-pixel SPi is sensed through the second column line CL2B, and the i+1-th sub-pixel ( The voltage of the second node N2 of the driving transistor DRT in SPi+1 is sensed through the other second column line CL2D.

To this end, the sampling switch SAM connected to the second column lines CL2B and CL2D is turned on so that the second column lines CL2B and CL2D are electrically connected to the analog-to-digital converter ADC.

As described above, two adjacent subpixels SPi and SPi+1 may be simultaneously sensed through one-time sensing drive. Accordingly, the total time required to sense and drive all subpixels disposed on the organic light emitting display panel 110 can be greatly reduced.

Hereinafter, the sensing method will be described in more detail by dividing the information to be grasped through the sensing method into a case of a threshold voltage of the driving transistor DRT and a case of mobility of the driving transistor DRT.

15 is a timing diagram of sensing a threshold voltage of the organic light emitting display device 100 according to the present embodiments. 16 to 18 are diagrams illustrating a threshold voltage sensing procedure in a first threshold voltage sensing interval, and FIGS. 19 to 21 are diagrams illustrating a threshold voltage sensing procedure in a second threshold voltage sensing interval.

Here, the first threshold voltage sensing period is the threshold of each driving transistor (DRT) of two subpixels SPi-1 and SPi+2 among four subpixels (SPi-1, SPi, SPi+1, SPi+2). This is the section where the voltage is sensed. In addition, the second threshold voltage sensing period is the threshold voltage of the driving transistor DRT of the remaining two sub-pixels SPi and SPi+1 among the four sub-pixels (SPi-1, SPi, SPi+1, SPi+2). is a section that senses

Referring to FIGS. 15 and 16 , in the first step S1410 in the first threshold voltage sensing period, the column voltage switch SCV connected to the first column lines CL1A and CL1E is turned on. A scan signal SCAN and a sensing signal SENSE having a turn-on voltage level are applied to gate nodes of each of the first and second transistors T1 and T2 .

In the first step S1410, the first column voltage for sensing is applied to the first node N1 of the driving transistor DRT in the i−1 th subpixel SPi−1 through the first column line CL1A. (CV1A_SEN) is applied. The sensing first column voltage CV1E_SEN is applied to the first node N1 of the driving transistor DRT in the i+2 th sub-pixel SPi+2 through another first column line CL1E.

Also, in the first step S1410, the initialization voltage Vpre is applied to the second node N2 of the driving transistor DRT in the i−1 th subpixel SPi−1 through the second column line CL2B. and the initialization voltage Vpre is applied to the second node N2 of the driving transistor DRT in the i+2 th sub-pixel SPi+2 through another second column line CL2D.

Referring to FIGS. 15 and 17 , in the second step S1420 in the first threshold voltage sensing period, the initialization switch SPRE connected to the second column lines CL2B and CL2D is turned off.

Accordingly, in the second step S1420, the second node N2 of the driving transistor DRT in the i−1 th subpixel SPi−1 and the driving transistor in the i+2 th subpixel SPi+2 are connected. The second node N2 of (DRT) is simultaneously floated.

Accordingly, the second node N2 of the driving transistor DRT in the i−1 th subpixel SPi−1 and the second node N2 of the driving transistor DRT in the i+2 th subpixel SPi+2 ( N2) is a voltage rise.

15 and 18, in the third step S1430 in the first threshold voltage sensing period, a sensing signal SENSE having a turn-off voltage level is applied to the gate node of the second transistor T2, The second transistor T2 is turned off. Also, the sampling switch SAM connected to the second column lines CL2B and CL2D is turned on so that the second column lines CL2B and CL2D are electrically connected to the analog-to-digital converter ADC.

Accordingly, the analog-to-digital converter ADC senses the voltage of the second node N2 of the driving transistor DRT in the i−1 th subpixel SPi−1 through the second column line CL2B, The voltage of the second node N2 of the driving transistor DRT in the i+2th sub-pixel SPi+2 is sensed through another second column line CL2D.

At this time, the voltage sensed through the second column line CL2B is the difference between the sensing first column voltage CV1A_SEN and the threshold voltage Vth of the driving transistor DRT in the i−1 th subpixel SPi−1. Corresponds to the difference (CV1A_SEN - Vth).

The voltage sensed through the other second column line CL2D is the difference between the sensing first column voltage CV1E_SEN and the threshold voltage Vth of the driving transistor DRT in the i+2 th subpixel SPi+2. Corresponds to (CV1E_SEN - Vth).

After the third step ( S1430 ) and the fourth step ( S1440 ), the controller 140 receives a digital value for the sensing voltage from the analog-to-digital converter (ADC), and converts the i−1 th subpixel (SPi−1) The threshold voltage of the driving transistor DRT within the driving transistor DRT may be identified, and the threshold voltage of the driving transistor DRT within the i+2th subpixel SPi+2 may be identified.

Thereafter, the controller 140 calculates a compensation value for compensating for the threshold voltage deviation using the identified threshold voltage, and calculates the i−1 th subpixel (SPi−1) and the i+2 th subpixel (SPi+2). It can be used to change data when generating the next first and second column data corresponding to .

Below, a second threshold voltage sensing section performed after the first threshold voltage sensing section will be described.

Referring to FIGS. 15 and 19 , in the first step S1410 in the second threshold voltage sensing period, the column voltage switch SCV connected to the first column line CL1C is turned on. A scan signal SCAN and a sensing signal SENSE having a turn-on voltage level are applied to gate nodes of each of the first and second transistors T1 and T2 .

In this first step S1410, the first node N1 of the driving transistor DRT in the ith subpixel SPi and the i+1th subpixel SPi+1 are connected through the first column line CL1C. ), the sensing first column voltage CV1C_SEN is simultaneously applied to the first node N1 of the driving transistor DRT.

In addition, in the first step S1410, the initialization voltage Vpre is applied to the second node N2 of the driving transistor DRT in the i-th sub-pixel SPi through the second column line CL2B, and The initialization voltage Vpre is applied to the second node N2 of the driving transistor DRT in the i+1 th sub-pixel SPi+1 through the second column line CL2D.

Referring to FIGS. 15 and 20 , in the second step S1420 in the second threshold voltage sensing period, the initialization switch SPRE connected to the second column lines CL2B and CL2D is turned off.

Accordingly, in the second step S1420, the second node N2 of the driving transistor DRT in the i-th sub-pixel SPi and the driving transistor DRT in the i+1-th sub-pixel SPi+1 The second node N2 is simultaneously floated.

Accordingly, the second node N2 of the driving transistor DRT in the i-th sub-pixel SPi and the second node N2 of the driving transistor DRT in the i+1-th sub-pixel SPi+1 are voltage rise takes place

15 and 21, in the third step (S1430) in the second threshold voltage sensing period, a sensing signal SENSE having a turn-off voltage level is applied to the gate node of the second transistor T2, The second transistor T2 is turned off. Also, the sampling switch SAM connected to the second column lines CL2B and CL2D is turned on so that the second column lines CL2B and CL2D are electrically connected to the analog-to-digital converter ADC.

Accordingly, the analog-to-digital converter ADC senses the voltage of the second node N2 of the driving transistor DRT in the i-th sub-pixel SPi through the second column line CL2B, and senses the i+1-th voltage. The voltage of the second node N2 of the driving transistor DRT in the sub-pixel SPi+1 is sensed through another second column line CL2D.

At this time, the voltage sensed through the second column line CL2B is the difference between the sensing first column voltage CV1C_SEN and the threshold voltage Vth of the driving transistor DRT in the ith subpixel SPi (CV1C_SEN - corresponds to Vth).

The voltage sensed through the other second column line CL2D is the difference between the sensing first column voltage CV1C_SEN and the threshold voltage Vth of the driving transistor DRT in the i+1th subpixel SPi+1. Corresponds to (CV1C_SEN - Vth).

After the third step (S1430) and the fourth step (S1440), the controller 140 receives a digital value for the sensing voltage from the analog-to-digital converter (ADC), and the driving transistor ( The threshold voltage of the DRT may be identified, and the threshold voltage of the driving transistor DRT in the i+1 th sub-pixel SPi+1 may be identified.

Thereafter, the controller 140 calculates a compensation value for compensating for the threshold voltage deviation using the identified threshold voltage, and the next When first and second column data is created, it can be used to change data.

According to the threshold voltage sensing method described above, a driving transistor for two adjacent subpixels ( DRT) threshold voltage can be simultaneously sensed. Accordingly, the total time required to sense threshold voltages of all subpixels disposed on the organic light emitting display panel 110 can be greatly reduced.

22 is a timing diagram for sensing mobility of the organic light emitting display device 100 according to the present embodiments. Further, FIGS. 23 to 25 are diagrams illustrating a mobility sensing procedure in a first mobility sensing interval, and FIGS. 26 to 28 are diagrams illustrating a mobility sensing procedure in a second mobility sensing interval.

Here, in the first mobility sensing period, among the four subpixels (SPi-1, SPi, SPi+1, and SPi+2), the driving transistors (DRT) of two subpixels SPi-1 and SPi+2 move. This is the section where the degree is sensed. In addition, the second mobility sensing period is the mobility of each of the driving transistors (DRT) of the remaining two subpixels SPi and SPi+1 among the four subpixels (SPi-1, SPi, SPi+1, SPi+2). This is the section for sensing .

Referring to FIGS. 22 and 23 , in the first step S1410 in the first mobility sensing period, the column voltage switch SCV connected to the first column lines CL1A and CL1E is turned on. A scan signal SCAN and a sensing signal SENSE having a turn-on voltage level are applied to gate nodes of each of the first and second transistors T1 and T2 .

In the first step S1410, the first column voltage for sensing is applied to the first node N1 of the driving transistor DRT in the i−1 th subpixel SPi−1 through the first column line CL1A. (CV1A_SEN) is applied. The sensing first column voltage CV1E_SEN is applied to the first node N1 of the driving transistor DRT in the i+2 th sub-pixel SPi+2 through another first column line CL1E.

Also, in the first step S1410, the initialization voltage Vpre is applied to the second node N2 of the driving transistor DRT in the i−1 th subpixel SPi−1 through the second column line CL2B. and the initialization voltage Vpre is applied to the second node N2 of the driving transistor DRT in the i+2 th sub-pixel SPi+2 through another second column line CL2D.

Referring to FIGS. 22 and 24 , in the second step S1420 in the first mobility sensing period, the initialization switch SPRE connected to the second column lines CL2B and CL2D is turned off. Also, the column voltage switch SCV connected to the first column lines CL1A and CL1E is turned off, and the scan signal SCAN having the turn-off voltage level is applied to the gate node of the first transistor T1.

Accordingly, in the second step S1420, the first node N1 and the second node N2 of the driving transistor DRT in the i−1 th subpixel SPi−1 and the i+2 th subpixel Both the first node N1 and the second node N2 of the driving transistor DRT within (SPi+2) are floated.

Accordingly, the first node N1 and the second node N2 of the driving transistor DRT in the i−1 th subpixel SPi−1 and the driving transistor in the i+2 th subpixel SPi+2 ( The voltage is increased while maintaining the potential difference between the first node N1 and the second node N2 of the DRT.

After this voltage rise occurs for a certain period of time, a third step (S1430) in the first mobility sensing section may proceed.

Referring to FIGS. 22 and 25 , in the third step S1430 in the first mobility sensing period, the sampling switch SAM connected to the second column lines CL2B and CL2D is turned on, The column lines CL2B and CL2D are electrically connected to the analog-to-digital converter ADC.

Accordingly, the analog-to-digital converter ADC senses the voltage of the second node N2 of the driving transistor DRT in the i−1 th subpixel SPi−1 through the second column line CL2B, The voltage of the second node N2 of the driving transistor DRT in the i+2th sub-pixel SPi+2 is sensed through another second column line CL2D.

In this case, the voltage sensed through the second column line CL2B increases as the current capability (IDS, that is, mobility) of the driving transistor DRT in the i−1 th subpixel SPi−1 increases.

The voltage sensed through the second column line CL2D increases as the current capability (IDS, that is, mobility) of the driving transistor DRT in the i+2-th sub-pixel SPi+2 increases.

After the third step ( S1430 ) and the fourth step ( S1440 ), the controller 140 receives a digital value for the sensing voltage from the analog-to-digital converter (ADC), and converts the i−1 th subpixel (SPi−1) Mobility of the driving transistor DRT within the i+2 th sub-pixel SPi+2 may be identified.

Thereafter, the controller 140 calculates a compensation value (gain, etc.) for compensating for the mobility deviation using the identified mobility, and calculates the i−1 th subpixel SPi−1 and the i+2 th subpixel ( It can be used to change data when generating the next first and second column data corresponding to SPi+2).

Below, a second mobility sensing section performed after the first mobility sensing section will be described.

Referring to FIGS. 22 and 26 , in the first step S1410 in the second mobility sensing period, the column voltage switch SCV connected to the first column line CL1C is turned on. A scan signal SCAN and a sensing signal SENSE having a turn-on voltage level are applied to gate nodes of each of the first and second transistors T1 and T2 .

In this first step S1410, the first node N1 of the driving transistor DRT in the ith subpixel SPi and the i+1th subpixel SPi+1 are connected through the first column line CL1C. ), the sensing first column voltage CV1C_SEN is simultaneously applied to the first node N1 of the driving transistor DRT.

In addition, in the first step S1410, the initialization voltage Vpre is applied to the second node N2 of the driving transistor DRT in the i-th sub-pixel SPi through the second column line CL2B, and The initialization voltage Vpre is applied to the second node N2 of the driving transistor DRT in the i+1 th sub-pixel SPi+1 through the second column line CL2D.

Referring to FIGS. 22 and 27 , in the second step S1420 in the second mobility sensing period, the initialization switch SPRE connected to the second column lines CL2B and CL2D is turned off. Also, the column voltage switch SCV connected to the first column line CL1C is turned off, and the scan signal SCAN having the turn-off voltage level is applied to the gate node of the first transistor T1.

Accordingly, in the second step S1420, the first node N1 and the second node N2 of the driving transistor DRT in the ith subpixel SPi and the i+1th subpixel SPi+1 are formed. Both the first node N1 and the second node N2 of the driving transistor DRT are floated.

Accordingly, the first node N1 and the second node N2 of the driving transistor DRT in the i-th sub-pixel SPi and the driving transistor DRT in the i+1-th sub-pixel SPi+1 The voltage of the first node N1 and the second node N2 is increased.

After this voltage rise occurs for a certain period of time, a third step (S1430) in the second mobility sensing section may proceed.

Referring to FIGS. 22 and 28 , in the third step S1430 in the second mobility sensing period, the sampling switch SAM connected to the second column lines CL2B and CL2D is turned on, The column lines CL2B and CL2D are electrically connected to the analog-to-digital converter ADC.

Accordingly, the analog-to-digital converter ADC senses the voltage of the second node N2 of the driving transistor DRT in the i-th sub-pixel SPi through the second column line CL2B, and senses the i+1-th voltage. The voltage of the second node N2 of the driving transistor DRT in the sub-pixel SPi+1 is sensed through another second column line CL2D.

In this case, the voltage sensed through the second column line CL2B increases as the current capability (IDS, that is, mobility) of the driving transistor DRT in the i-th sub-pixel SPi increases.

The voltage sensed through the other second column line CL2D increases as the current capability (IDS, that is, mobility) of the driving transistor DRT in the i+1 th subpixel SPi+1 increases.

After the third step (S1430) and the fourth step (S1440), the controller 140 receives a digital value for the sensing voltage from the analog-to-digital converter (ADC), and the driving transistor ( The mobility of the DRT may be identified, and the mobility of the driving transistor DRT in the i+1 th sub-pixel SPi+1 may be identified.

Thereafter, the controller 140 calculates a compensation value (gain, etc.) for compensating for the mobility deviation using the identified mobility, and calculates the i-th sub-pixel SPi and the i+1-th sub-pixel SPi+1. It can be used to change data when generating the next first and second column data corresponding to .

According to the above-described mobility sensing method, according to the unique subpixel structure according to the present embodiments and a driving method of column lines using the same, a driving transistor for two adjacent subpixels is driven through one turn of mobility sensing ( DRT) can be simultaneously sensed. Accordingly, the total time required to sense the mobility of all subpixels disposed on the organic light emitting display panel 110 can be greatly reduced.

29 is a diagram illustrating functional redundancy of the first transistor and the second transistor in the organic light emitting display device according to the present embodiments.

Referring to FIG. 29 , the first transistor T1 of the i-th sub-pixel SPi and the first transistor T1 of the i+1-th sub-pixel SPi+1 are simultaneously connected to the first column line CL1C. Thus, the first column voltage CV1C is simultaneously applied from the first column line CL1C.

Accordingly, the first transistor T1 of each of the two adjacent subpixels SPi and SPi+1 based on the first column line CL1C is connected to the first column voltage CV1C from the first column line CL1C. ) to the first node N1 of the corresponding driving transistor DRT, it has the same function.

That is, the first transistor T1 of each of the two adjacent subpixels SPi and SPi+1 based on the first column line CL1C may be regarded as a functionally redundant transistor.

Similarly, the second transistors T2 of each of the two adjacent subpixels SPi−1 and SPi based on the second column line CV2B may also be regarded as functionally redundant transistors.

Accordingly, in the present embodiments, two adjacent subpixels (SPi and SPi+1) based on the first column line CL1C are connected through one common first transistor T1 without overlapping transistor design. The two sub-pixels (SPi-1 and SPi) that receive the first column voltage CV1C and are adjacent to each other based on the second column line CV2B form the second column through one common second transistor T2. A structure capable of receiving the voltage CB2B may be provided.

This transistor reduction structure will be described with reference to FIGS. 30 and 31 .

30 and 31 are diagrams illustrating a structure for reducing the number of transistors in the organic light emitting display device 100 according to the present embodiments.

Referring to FIG. 30 , in the organic light emitting display panel 110 in the organic light emitting display device 100 according to the present exemplary embodiments, a plurality of first column lines CL1A, CL1C, and CL1E are provided in a column direction and a plurality of first column lines CL1A, CL1C, and CL1E A plurality of column lines CL1A, CL2B, CL1C, CL2D, and CL1E including the second column lines CL2B and CL2D of are disposed, and a plurality of row lines are disposed in a row direction.

In addition, each of the plurality of subpixels (SPi-1, SPi, SPi+1, and SPi+2) includes an organic light emitting diode (OLED), a driving transistor (DRT) for driving the organic light emitting diode (OLED), and a driving transistor (DRT). ) may include a storage capacitor Cst electrically connected between the first node N1 and the second node N2.

The plurality of first column lines CL1A, CL1C, and CL1E and the plurality of second column lines CL2B and CL2D are alternately positioned.

That is, the first column line CL1A, the second column line CL2B, the first column line CL1C, the second column line CL2D, and the first column line CL1E are arranged in this order.

Referring to FIG. 30 , in any one sub-pixel row, consecutive i-th sub-pixel columns (SPC #i), i+1-th sub-pixel columns (SPC #i+1), and i+2-th sub-pixel columns In the sub-pixel column SPC #i+2, the first node N1 of the driving transistor DRT of the sub-pixel SPi located in the i-th sub-pixel column SPC #i and the i+1-th sub-pixel The first node N1 of the driving transistor DRT of the subpixel SPi+1 located in the column SPC #i+1 is electrically connected at the first connection point CP1.

Also, a first transistor T1 is electrically connected between the first connection point CP1 and the first column line CL1C.

That is, the first node N1 of the driving transistor DRT of the subpixel SPi located in the i-th sub-pixel column SPC #i and the sub-pixel located in the i+1-th sub-pixel column SPC #i+1 The first node N1 of the driving transistor DRT of the pixel SPi+1 is connected to the first transistor T1 in common.

Referring to FIG. 30 , the second node N2 of the driving transistor DRT of the sub-pixel SPi+1 located in the i+1-th sub-pixel column SPC #i+1 and the i+2-th sub-pixel column The second node N2 of the driving transistor DRT of the subpixel SPi+2 located at (SPC #i+2) is electrically connected at the second connection point CP2.

Also, the second transistor T2 is electrically connected between the second connection point CP2 and the second column line CL2B.

That is, the second node N2 of the driving transistor DRT of the subpixel SPi+1 located in the i+1 th subpixel column SPC #i+1 and the i+2 th subpixel column SPC #i +2), the second node N2 of the driving transistor DRT of the sub-pixel SPi+2 is electrically connected to the second transistor T2.

According to the above structure, the two adjacent subpixels SPi and SPi+1 based on the first column line CL1C apply the first column voltage CV1C through one common first transistor T1. can be supplied In addition, two adjacent subpixels SPi-1 and SPi based on the second column line CV2B may receive the second column voltage CB2B through one common second transistor T2. .

Therefore, the number of first transistors T1 and second transistors T2 can be reduced by half in an area where there are four subpixels (SPi-1, SPi, SPi+1, and SPi+2), and the organic light emitting display When viewing the entire area of the panel 110, it can be seen that the effect of reducing the number of transistors is very large. Accordingly, the aperture ratio of the organic light emitting display panel 110 can be very high.

Referring to FIG. 31 , each of the plurality of first column lines CL1A, CL1C, and CL1E and the plurality of second column lines CL2B and CL2D may be electrically connected to the digital-to-analog converter DAC.

Also, each of the plurality of second column lines CL2B and CL2D may be electrically connected to the analog-to-digital converter ADC.

The method of driving the organic light emitting display panel 110 for the transistor reduction structure shown in FIGS. 30 and 31 is the same as described above.

According to the present embodiments as described above, the organic light emitting display panel 110 designed with a new concept subpixel structure capable of reducing the number of signal lines and driving the subpixels having this new concept subpixel structure A line driving circuit 120 for a line driving circuit, an organic light emitting display device 100 including the same, an image driving method, and a sensing method may be provided.

Here, the sub-pixel structure of the new concept is a connection structure of signal lines connected to circuit elements in the sub-pixel even though the connection structure of the organic light emitting diode, the transistors DRT, T1 and T2, and the storage capacitor Cst is the same. is new.

For example, conventionally, a data voltage corresponding to an image signal is supplied to a corresponding subpixel through one data line, but according to the present embodiments, two column voltages (first and second column voltages) corresponding to the image signal It is supplied to the corresponding subpixel through these two column lines (first and second column lines).

In addition, two column lines (first and second column lines) are alternately arranged and designed to be shared by two adjacent subpixels.

In addition, according to the present embodiments, an organic light emitting display panel 110, an organic light emitting display device 100, a line driving circuit 120, an image driving method, and a sensing method capable of reducing the number of signal lines and reducing the sensing time can provide.

According to the present embodiments, an organic light emitting display panel 110 having a high aperture ratio, an organic light emitting display device 100, a line driving circuit 120, an image driving method, and a sensing method may be provided.

The above description and accompanying drawings are only illustrative of the technical idea of the present invention, and those skilled in the art can combine the configuration within the range that does not deviate from the essential characteristics of the present invention. , various modifications and variations such as separation, substitution and alteration will be possible. Therefore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. The protection scope of the present invention should be construed according to the following claims, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

100: organic light emitting display device
110: organic light emitting display panel
120: column line driving circuit
130: low line driving circuit
140: controller

Claims (18)

A plurality of column lines including a plurality of first column lines and a plurality of second column lines are disposed in a column direction, a plurality of row lines are disposed in a row direction, and a plurality of subpixels are arranged in a matrix organic light emitting display panels arranged in a type;
a column line driving circuit for driving the plurality of first column lines and the plurality of second column lines; and
a row line driving circuit for driving the plurality of row lines;
Each subpixel,
organic light emitting diode;
a driving transistor for driving the organic light emitting diode;
a first transistor electrically connected between a first node of the driving transistor and the first column line;
a second transistor electrically connected between a second node of the driving transistor and the second column line; and
a storage capacitor electrically connected between a first node and a second node of the driving transistor;
The first column line is located between the i-th sub-pixel column and the i+1-th sub-pixel column,
The second column line is located between the i+1 th sub-pixel column and the i+2 th sub-pixel column,
A drain node or a source node of the first transistor is electrically connected to the first node,
A drain node or a source node of the second transistor is electrically connected to the second node,
wherein i is a natural number greater than or equal to 1. According to claim 1,
The first column line,
connected in common to a first transistor of a subpixel located in the i-th sub-pixel column and a first transistor of a sub-pixel located in the i+1-th sub-pixel column;
The second column line,
A second transistor of a subpixel positioned in the i+1th subpixel column and a second transistor of a subpixel positioned in the i+2th subpixel column are connected in common to each other. According to claim 1,
Each of the plurality of first column lines and the plurality of second column lines is electrically connected to a digital-to-analog converter. According to claim 3,
and a column voltage switch for switching a connection with the digital-to-analog converter for each of the plurality of first column lines and the plurality of second column lines. According to claim 1,
The plurality of second column lines are electrically connected to an analog-to-digital converter. According to claim 5,
a sampling switch for switching a connection between each of the second column lines and an analog-to-digital converter; and
and an initialization voltage switch for switching a connection between each of the second column lines and an initialization voltage supply node. According to claim 1,
The column line driving circuit,
outputting a first column voltage to the first column line and a second column voltage to the second column line;
The difference between the first column voltage and the second column voltage is
An organic light emitting display device corresponding to a data voltage corresponding to luminance to be expressed in a subpixel including a first transistor connected to the first column line and a second transistor connected to the second column line. a plurality of first column lines arranged in a column direction;
a plurality of second column lines arranged in a column direction;
a plurality of row lines arranged in a row direction; and
It includes a plurality of subpixels arranged in a matrix type,
Each of the plurality of subpixels,
organic light emitting diode;
a driving transistor for driving the organic light emitting diode;
a first transistor electrically connected between a first node of the driving transistor and the first column line;
a second transistor electrically connected between a second node of the driving transistor and the second column line; and
a storage capacitor electrically connected between a first node and a second node of the driving transistor;
The first column line is located between the i-th sub-pixel column and the i+1-th sub-pixel column;
The second column line is located between the i+1 th sub-pixel column and the i+2 th sub-pixel column,
A drain node or a source node of the first transistor is electrically connected to the first node,
A drain node or a source node of the second transistor is electrically connected to the second node,
wherein i is a natural number greater than or equal to 1. According to claim 8,
The first column line,
connected in common to a first transistor of a subpixel located in the i-th sub-pixel column and a first transistor of a sub-pixel located in the i+1-th sub-pixel column;
The second column line,
A second transistor of a subpixel positioned in the i+1th subpixel column and a second transistor of a subpixel positioned in the i+2th subpixel column are connected in common to each other. A plurality of first column lines and a plurality of second column lines are located between a plurality of subpixels, and in a line driving circuit for driving the plurality of first column lines and the plurality of second column lines,
K (K is a natural number greater than or equal to 2) digital-to-analog converters;
K output buffers connected to the K digital-to-analog converters;
M+N (M+N=K, where M and N are natural numbers equal to or greater than 1) column voltage switches for switching connections between the K output buffers and the K column lines;
analog to digital converter;
N sampling switches for switching connections between the N second column lines among the M first column lines and the N second column lines included in the K column lines and the analog-to-digital converter; and
At least one initialization switch for switching a connection between the N second column lines and an initialization voltage supply node;
outputting a first column voltage to the first column line and a second column voltage to the second column line;
The difference between the first column voltage and the second column voltage is
A line driving circuit corresponding to a data voltage corresponding to luminance to be expressed in each of the subpixels electrically connected to the first column line and the second column line. According to claim 10,
A column line driving circuit in which the first column line and the second column line alternate. In the image driving method of the organic light emitting display device,
An organic light emitting display panel included in the organic light emitting display device includes a plurality of first column lines disposed in a column direction, a plurality of second column lines disposed in the column direction, and a plurality of subpixels arranged in a matrix type. do,
Each of the plurality of subpixels,
organic light emitting diode;
a driving transistor for driving the organic light emitting diode;
a first transistor electrically connected between a first node of the driving transistor and the first column line;
a second transistor electrically connected between a second node of the driving transistor and the second column line; and
a storage capacitor electrically connected between a first node and a second node of the driving transistor;
The first column line is located between the i-th sub-pixel column and the i+1-th sub-pixel column;
The second column line is located between the i+1 th sub-pixel column and the i+2 th sub-pixel column,
The video driving method,
A first column voltage is applied to the first node of the driving transistor in the i-th subpixel through a first column line, and a second column voltage is applied to the second node of the driving transistor in the i-th subpixel through a second column line. A first step of applying;
a second step of floating a first node and a second node of a driving transistor in the i-th sub-pixel; and
A third step of emitting light from the organic light emitting diode in the i th subpixel;
The first step is
When a first column voltage is applied to the first node of the driving transistor in the ith subpixel through the first column line, the first column voltage is applied to the first node of the driving transistor in the i+1th subpixel through the first column line. simultaneously applying the first column voltage;
When a second column voltage is applied to the second node of the driving transistor in the i-th subpixel through the second column line, the second column voltage is applied to the second node of the driving transistor in the i−1 th subpixel through the second column line. Simultaneously applying the second column voltage,
A drain node or a source node of the first transistor is electrically connected to the first node,
A drain node or a source node of the second transistor is electrically connected to the second node,
wherein i is a natural number greater than or equal to 1. In the sensing method of the organic light emitting display device,
A first column voltage for sensing is simultaneously applied to a first node of a driving transistor in the i-th subpixel and a first node of a driving transistor in the i+1-th subpixel through a first column line, and through a second column line a first step of applying an initialization voltage to a second node of a driving transistor in the ith subpixel and applying an initialization voltage to a second node of a driving transistor in the i+1th subpixel through another second column line;
a second step of simultaneously floating a second node of the driving transistor in the ith subpixel and a second node of the driving transistor in the i+1th subpixel; and
The voltage of the second node of the driving transistor in the i-th sub-pixel is sensed through the second column line, and the voltage of the second node of the driving transistor in the i+1-th sub-pixel is sensed through the other second column line. A sensing method of an organic light emitting display device comprising a third step of sensing. According to claim 13,
In the second step, when the second node of the driving transistor in the ith subpixel and the second node of the driving transistor in the i+1th subpixel are simultaneously floated,
After the third step, the sensing of the organic light emitting display device further includes a fourth step of determining a threshold voltage of a driving transistor in the ith subpixel and determining a threshold voltage of a driving transistor in the i+1th subpixel. method. According to claim 13,
In the second step, when both the first node and the second node of the driving transistor in the i-th subpixel and the first node and the second node of the driving transistor in the i+1-th subpixel are floated,
After the third step, sensing of the organic light emitting display device further comprising a fourth step of determining the mobility of the driving transistor in the ith subpixel and determining the mobility of the driving transistor in the i+1th subpixel. method. A plurality of column lines including a plurality of first column lines and a plurality of second column lines are disposed in a column direction, a plurality of row lines are disposed in a row direction, and an organic light emitting diode, the organic an organic light emitting display panel in which subpixels including a driving transistor for driving a light emitting diode and a storage capacitor electrically connected between a first node and a second node of the driving transistor are arranged in a matrix type;
a column line driving circuit for driving the plurality of first column lines and the plurality of second column lines; and
a row line driving circuit for driving the plurality of row lines;
The first column line and the second column line are alternately positioned,
In the i-th sub-pixel column, the i+1-th sub-pixel column, and the i+2-th sub-pixel column,
A first node of a driving transistor of a subpixel located in an ith subpixel column is electrically connected to a first node of a driving transistor of a subpixel located in an i+1th subpixel column at a first connection point;
A first transistor is electrically connected between the first connection point and the first column line;
A second node of the driving transistor of the subpixel located in the i+1th subpixel column is electrically connected to a second node of the driving transistor of the subpixel located in the i+2th subpixel column at a second connection point;
A second transistor is electrically connected between the second connection point and the second column line;
A drain node or a source node of the first transistor is electrically connected to a first node of the ith subpixel and a first node of the i+1th subpixel;
A drain node or a source node of the second transistor is electrically connected to a second node of the i+1 th subpixel and a second node of the i+2 th subpixel. According to claim 16,
Each of the plurality of first column lines and the plurality of second column lines is electrically connected to a digital-to-analog converter. According to claim 16,
The plurality of second column lines are electrically connected to an analog-to-digital converter.

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