KR102505325B1 - Display device - Google Patents

Abstract

A display device according to an embodiment of the present invention discloses forming a fine pattern of a black matrix in order to correspond to a high resolution. The display device includes a thin film transistor array substrate, a color filter array substrate, and a liquid crystal layer. The thin film transistor array substrate includes a thin film transistor, a pixel electrode and a common electrode. The color filter array substrate includes an upper substrate, a first black matrix, and a second black matrix. The first black matrix is located on the upper substrate and has a lattice shape, and the second black matrix is located on the first black matrix and has a lattice shape. The first black matrix and the second black matrix cross each other.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device.

In general, liquid crystal display devices are driven by using optical anisotropy and polarization properties of liquid crystals. Since the liquid crystal has a thin and long structure, the arrangement of the molecules has directionality, and the direction of the arrangement of the molecules can be controlled by artificially applying an electric field to the liquid crystal. Therefore, if the direction of the arrangement of the molecules of the liquid crystal is arbitrarily adjusted, The molecular arrangement is changed, and light is refracted in the direction of the molecular arrangement of the liquid crystal due to the optical anisotropy, so that image information can be expressed.

Currently, the active matrix liquid crystal display (AM-LCD: Active Matrix LCD, hereinafter, abbreviated as liquid crystal display) in which thin film transistors and pixel electrodes connected to the thin film transistors are arranged in a matrix manner has excellent resolution and ability to implement moving images, It is getting attention. The liquid crystal display device is composed of a color filter substrate on which a common electrode is formed, an array substrate on which pixel electrodes are formed, and a liquid crystal interposed between the two substrates. It is a liquid crystal driving method and has excellent properties such as transmittance and aperture ratio. However, liquid crystal driving by an electric field applied vertically has a disadvantage in that viewing angle characteristics are not excellent. Therefore, in order to overcome the above disadvantages, a transversal field type liquid crystal display having excellent viewing angle characteristics has been proposed. A horizontal electric field type liquid crystal display device has an advantage of improving a viewing angle by driving liquid crystal using a horizontal electric field between a pixel electrode and a common electrode.

Recently, as the resolution of display devices increases and PPI (Pixel Per Inch) increases, the pitch of pixels is decreasing. As the pixel pitch decreases, the pitch of the black matrix formed on the color filter substrate of the display device should also decrease. However, due to the nature of the black matrix, it is difficult to form a fine pattern, and thus it is difficult to cope with high resolution.

The present invention provides a display device capable of forming a fine pattern of a black matrix to correspond to high resolution.

In order to achieve the above object, a display device according to an embodiment of the present invention discloses forming a fine pattern of a black matrix in order to correspond to a high resolution. The display device includes a thin film transistor array substrate, a color filter array substrate, and a liquid crystal layer. The thin film transistor array substrate includes a thin film transistor, a pixel electrode and a common electrode. The color filter array substrate includes an upper substrate, a first black matrix, and a second black matrix. The first black matrix is located on the upper substrate and has a lattice shape, and the second black matrix is located on the first black matrix and has a lattice shape. The first black matrix and the second black matrix cross each other.

The first black matrix includes a plurality of first openings, and the second black matrix includes a plurality of second openings.

One of the plurality of first openings of the first black matrix overlaps four second openings of the plurality of second openings of the second black matrix.

One of the plurality of first openings overlaps with four second openings of the plurality of second openings to define four sub-pixel units.

All four sub-pixel parts have the same size.

The color filter array substrate further includes a color filter positioned between the first black matrix and the second black matrix, and a first overcoat layer positioned on the second black matrix.

A second overcoat layer is further included between the color filter and the second black matrix.

Also, a display device according to an embodiment of the present invention includes a thin film transistor array substrate, a color filter array substrate, and a liquid crystal layer. The thin film transistor array substrate includes a thin film transistor, a pixel electrode and a common electrode. The color filter array substrate includes a first black matrix and a second black matrix. The first black matrix is located on the upper substrate and includes a plurality of first patterns having first straight portions and a plurality of first protrusions protruding from the first straight portions. The second black matrix is located on the first black matrix and includes a plurality of second patterns having second straight portions and a plurality of second protrusions protruding from the second straight portions. The plurality of first patterns partially overlap with the plurality of second patterns.

The first straight part and the second straight part are spaced apart from each other and arranged side by side.

The first protrusion overlaps the second straight portion.

A plurality of sub-pixel parts are partitioned by overlapping a plurality of first patterns and a plurality of second patterns.

The plurality of sub-pixel units have the same size or different sizes.

The color filter array substrate further includes a color filter positioned between the first black matrix and the second black matrix, and a first overcoat layer positioned on the second black matrix.

A second overcoat layer is further included between the color filter and the second black matrix.

A display device according to embodiments of the present invention forms a first black matrix and a second black matrix in different layers on a color filter array substrate, and overlaps the first black matrix and the second black matrix, thereby providing fine details corresponding to high resolution. It is possible to partition the sub-pixel portion of the size. In addition, there is an advantage in that the aperture ratio of each sub-pixel part can be compensated even if the first black matrix and the second black matrix are out of alignment.

1 is a block diagram illustrating a display device according to an exemplary embodiment of the present invention;
2 is a circuit diagram showing pixels of a display device;
3 is a plan view illustrating unit pixels of a display device according to an exemplary embodiment of the present invention;
Figure 4 is a cross-sectional view taken along line II' of Figure 3;
5 is a plan view showing the size of a subpixel;
6 and 7 are cross-sectional views of color filter array substrates of the present invention.
8 is a plan view illustrating a first black matrix and a second black matrix according to the first embodiment of the present invention;
9 is a plan view illustrating a shape in which a first black matrix and a second black matrix intersect according to the first embodiment of the present invention;
10 to 12 are plan views illustrating a first black matrix and a second black matrix according to a second embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. Like reference numbers throughout the specification indicate substantially the same elements. In the following description, if it is determined that a detailed description of a known technology or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted. In addition, component names used in the following description may be selected in consideration of ease of writing specifications, and may be different from names of parts of actual products.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a block diagram illustrating a display device according to an exemplary embodiment, and FIG. 2 is a circuit diagram illustrating pixels of the display device.

Referring to FIG. 1 , a display device according to an exemplary embodiment includes a display panel 100 , a data driving circuit 102 , a gate driving circuit 103 , and a timing controller 101 . A backlight unit for uniformly irradiating light to the liquid crystal display panel may be disposed below the liquid crystal display panel. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The display panel 100 includes a thin film transistor array substrate (or first substrate) and a color filter array substrate (or second substrate) that face each other with a liquid crystal layer interposed therebetween. A pixel array for displaying video data is formed on the liquid crystal display panel 100 . The pixel array includes pixels arranged in a matrix form by a cross structure of data lines and gate lines to display video data. The pixels may be R pixels, G pixels, and B pixels. Neighboring pixels share the same data line. Liquid crystal cells of pixels display an image of video data by adjusting the transmission amount of light by an electric field difference between a data voltage applied to a pixel electrode and a common voltage applied to a common electrode. The common electrode is formed on the color filter array substrate in vertical electric field driving methods such as TN (Twisted Nematic) mode and VA (Vertical Alignment) mode, and in horizontal In the electric field driving method, it is formed on the thin film transistor array substrate together with the pixel electrode.

The thin film transistor array substrate includes data lines, gate lines, thin film transistors, pixel electrodes connected 1:1 to the thin film transistors, and a storage capacitor (not shown) connected 1:1 to the pixel electrodes. Cst), etc. A black matrix and color filters are formed on the color filter array substrate of the display panel 100 . In this embodiment, a common electrode is formed on the thin film transistor array substrate. A polarizer is attached to each of the color filter array substrate and the TFT array substrate of the display panel 100, and an alignment layer for setting a pre-tilt angle of liquid crystal is formed.

The liquid crystal display panel 100 applicable in the present invention may be implemented in any liquid crystal mode as well as TN mode, VA mode, IPS mode, and FFS mode. The liquid crystal display of the present invention may be implemented in any form such as a transmissive liquid crystal display, a transflective liquid crystal display, or a reflective liquid crystal display. A backlight unit is required in a transmissive liquid crystal display and a transflective liquid crystal display. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The data driving circuit 102 includes a plurality of source drive ICs. The output channels of the source drive ICs are connected 1:1 to the data lines of the pixel array. Each of the source drive ICs receives digital video data from the timing controller 101. The source drive ICs convert digital video data into positive/negative data voltages in response to a source timing control signal from the timing controller 101 and supply them to data lines of the pixel array through output channels. The source drive ICs supply data voltages of opposite polarities to neighboring data lines under the control of the timing controller 101, and maintain the same polarity of the data voltages supplied to each data line for one frame period. , the polarity of the data voltage is inverted in the next frame period. Accordingly, the source drive ICs maintain the same polarities of the data voltages for one frame period and invert the polarities of the data voltages in a cycle of one frame period, substantially the same as the column inversion method.

The gate driving circuit 103 sequentially supplies gate pulses to gate lines of the pixel array in response to a gate timing control signal from the timing controller 101 . The timing controller 101 supplies digital video data input from an external system board 104 to the source drive ICs of the data driving circuit 102 . The timing controller 101 generates a source timing control signal for controlling the operation timing of the data driving circuit 102 and a gate timing control signal for controlling the operation timing of the gate driving circuit 103 .

Referring to FIG. 2 , the display device of the present invention converts digital video data into an analog data voltage based on a gamma reference voltage, supplies it to the data line DL, and simultaneously supplies a scan pulse to the gate line GL, The data voltage is charged in the liquid crystal cell (Clc). To this end, the gate electrode of the thin film transistor is connected to the gate line GL, the source electrode is connected to the data line DL, and the drain electrode of the thin film transistor is connected to the pixel electrode of the liquid crystal cell Clc and the storage capacitor Cst1. ) is connected to one electrode of the A common voltage Vcom is supplied to the common electrode of the liquid crystal cell Clc. The storage capacitor Cst1 serves to keep the voltage of the liquid crystal cell Clc constant by charging the data voltage applied from the data line DL when the thin film transistor is turned on. When the scan pulse is applied to the gate line GL, the TFT is turned on to form a channel between the source and drain electrodes, and the voltage on the data line DL is applied to the pixel electrode of the liquid crystal cell Clc. supply At this time, the arrangement of the liquid crystal molecules of the liquid crystal cell Clc is changed by the electric field between the pixel electrode and the common electrode, thereby varying the incident light. In this way, the display device of the present invention operates.

A schematic configuration of a display device according to an exemplary embodiment of the present invention has been described above. Hereinafter, a pixel array structure of a display panel of a display device will be described in detail. In addition, it will be described with reference numerals different from those in FIGS. 1 and 2 .

3 is a plan view illustrating unit pixels of a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 3 , in the display device 100 according to an exemplary embodiment of the present invention, a plurality of pixel units P1 , P2 , and P3 are arranged to form one unit pixel. Each of the plurality of pixel units includes a first pixel unit P1, a second pixel unit P2, and a third pixel unit P3. Each of the first pixel unit P1 , the second pixel unit P2 , and the third pixel unit P3 has a gate line GL extending in a horizontal direction and a first data line (crossing the gate line GL). DL1), the second data line DL2, and the third data line DL3. In the embodiment of the present invention, it is disclosed that the first to third pixel parts P1, P2, and P3 are composed of one unit pixel, but it is not limited thereto, and a unit pixel may be composed of four or five or more pixel parts. may be

The first pixel portion P1 of the present invention is partitioned by the intersection of the gate line GL and the first data line DL1. The first pixel unit P1 includes a first thin film transistor TR1 at the intersection of the gate line GL and the first data line DL1, and the first pixel electrode ( PXL1) is provided. The first thin film transistor TR1 of the first pixel unit P1 includes a first active layer ACT1, a gate line GL acting as a gate electrode, a first data line DL1 acting as a source electrode, and a first A drain electrode DRE1 is included. As the first active layer ACT1 overlaps the first data line DL1 and is formed in a 'U' shape, the first active layer ACT1 crosses the gate line GL twice. The first data line DL1 serving as a source electrode extends in a straight line and contacts one end of the first active layer ACT1 through the first source contact hole SCNT1. Since the first data line DL1 serves as a source electrode, the first source contact hole SCNT1 overlaps the first data line DL1. The first drain electrode DRE1 contacts the other end of the first active layer ACT1 through the first drain contact hole DCNT1. The first drain contact hole DCNT1 does not overlap and is spaced apart from the gate line GL. The first pixel electrode PXL1 is branched in a finger shape and is arranged parallel to the first data line DL1. The first pixel electrode PXL1 is connected to the first drain electrode DRE1 of the first thin film transistor TR1 through the first via hole VIA1. The first via hole VIA1 overlaps the first drain contact hole DCNT1 and the adjacent gate line GL. Although not shown, the first pixel electrode PXL1 faces the common electrode to form an electric field. The common electrode will be described in terms of a cross-sectional structure to be described later.

In this drawing, the thin film transistor is shown as an example in which a region constituting a channel forms a 'U' shape, but is not limited thereto, and may also be formed in an 'I' shape. In addition, although the thin film transistor is shown as an example in which the gate electrode is made of the gate line itself, it is not limited thereto, and may be formed by protruding from the gate line.

Meanwhile, the second pixel unit P2 of the present invention is partitioned by the intersection of the gate line GL and the second data line DL2. The second pixel unit P2 includes a second thin film transistor TR2 at the intersection of the gate line GL and the second data line DL2, and the second pixel electrode ( PXL2) is provided. The second thin film transistor TR2 of the second pixel unit P2 includes a second active layer ACT2, a gate line GL acting as a gate electrode, a second data line DL2 acting as a source electrode, and a second thin film transistor TR2. A drain electrode DRE2 is included. As the second active layer ACT2 overlaps the second data line DL2 and is formed in a 'U' shape, the second active layer ACT2 crosses the gate line GL twice. The second data line DL2 serving as a source electrode contacts one end of the second active layer ACT2 through the second source contact hole SCNT2. Since the second data line DL2 serves as a source electrode, the second source contact hole SCNT2 overlaps the second data line DL2. The second drain electrode DRE2 contacts the other end of the second active layer ACT2 through the second drain contact hole DCNT2. The second drain contact hole DCNT2 does not overlap and is spaced apart from the gate line GL. The second pixel electrode PXL2 is branched in a finger shape and is arranged parallel to the second data line DL2. The second pixel electrode PXL2 is connected to the second drain electrode DRE2 of the second thin film transistor TR2 through the second via hole VIA2. The second via hole VIA2 overlaps the second drain contact hole DCNT2 and the adjacent gate line GL. The second pixel electrode PXL2 faces the common electrode to form an electric field.

The third pixel unit P3 of the present invention is partitioned by the intersection of the gate line GL and the third data line DL3. The third pixel unit P3 includes a third thin film transistor TR3 at the intersection of the gate line GL and the third data line DL3, and a third pixel electrode ( PXL3) is provided. The third thin film transistor TR3 of the third pixel unit P3 includes a third active layer ACT3, a gate line GL acting as a gate electrode, a third data line DL3 acting as a source electrode, and a third A drain electrode DRE3 is included. As the third active layer ACT3 overlaps the third data line DL3 and is formed in a 'U' shape, the third active layer ACT3 crosses the gate line GL twice. The third data line DL3 serving as a source electrode contacts one end of the third active layer ACT3 through the third source contact hole SCNT3. Since the third data line DL3 serves as a source electrode, the third source contact hole SCNT3 overlaps the third data line DL3. The third drain electrode DRE3 contacts the other end of the third active layer ACT3 through the third drain contact hole DCNT3. The third drain contact hole DCNT3 does not overlap and is spaced apart from the gate line GL. The third pixel electrode PXL3 is branched in a finger shape and is arranged parallel to the third data line DL3. The third pixel electrode PXL3 is connected to the third drain electrode DRE3 of the third thin film transistor TR3 through the third via hole VIA3. The third via hole VIA3 overlaps the third drain contact hole DCNT3 and the adjacent gate line GL. The third pixel electrode PXL3 faces the common electrode to form an electric field.

In the display device 100 according to an embodiment of the present invention described above, the first to third pixel units are composed of one unit pixel and are regularly arranged throughout the display device 100 .

Hereinafter, a cross-sectional structure of a display device according to an exemplary embodiment of the present invention will be described with reference to FIG. 4 , which is a cross-sectional view taken along line II' of FIG. 3 .

Referring to FIG. 4 , the display device 100 according to an exemplary embodiment of the present invention is a thin film transistor having a coplanar type structure, and has a structure in which a gate electrode is positioned above an active layer.

More specifically, the light blocking film LS is positioned on the substrate 110 . The substrate 110 is made of transparent or opaque glass, plastic or metal. The light blocking film LS is for blocking external light from entering the inside, and is made of a material capable of blocking light. The light blocking film LS is made of a material having a low reflectance, for example, a resin containing a black material such as carbon black or amorphous silicon (a-Si), germanium (Ge), tantalum oxide (TaOx), It may be made of a semiconductor-based material such as copper oxide (CuOx). A buffer layer 120 is positioned over the entire substrate 110 on which the light blocking film LS is positioned. The buffer layer 120 is formed to protect the thin film transistor formed in a subsequent process from impurities such as alkali ions flowing out from the substrate 110 or lower layers, and is made of silicon oxide (SiOx), silicon nitride (SiNx) or these made up of multiple layers of

A first active layer ACT1 is positioned on the buffer layer 120 . The first active layer ACT1 is made of an oxide semiconductor. An oxide semiconductor is, for example, an amorphous zinc oxide-based semiconductor, in particular, an a-IGZO semiconductor is sputtered using a composite target of gallium oxide (Ga ₂ O ₃ ), indium oxide (In ₂ O ₃ ), and zinc oxide (ZnO) ( sputtering) method. In addition, a chemical vapor deposition method such as chemical vapor deposition or atomic layer deposition (ALD) may be used. Here, in the case of the embodiment of the present invention, the atomic ratio of gallium, indium, and zinc is 1: 1: 1, 2: 2: 1, 3: 2: 1, and 4: 2: 1, respectively, using an oxide target using a zinc oxide-based oxide target. Semiconductors can be deposited. However, the active layer of the present invention is not limited to a zinc oxide-based semiconductor.

The first active layer ACT1 includes two channels (Channel, CH). The channel CH corresponds to an area overlapping the gate line GL serving as a gate electrode. A gate insulating layer 125 is positioned on the first active layer ACT1. The gate insulating film 125 is made of a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof. The gate insulating layer 125 insulates the gate line GL from the first active layer ACT1. A gate line GL is positioned on the gate insulating layer 125 . The gate line GL is made of copper (Cu), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or tantalum (Ta). and tungsten (W), or a single layer or multiple layers of alloys thereof. The gate line GL is positioned to correspond to the channel CH of the first active layer ACT1.

An interlayer insulating layer 130 is positioned on the substrate 110 on which the gate line GL is formed. The interlayer insulating film 130 is made of a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof. In addition, the interlayer insulating layer 130 is provided with a first source contact hole SCNT1 and a first drain contact hole DCNT1 exposing source and drain regions on both sides of the first active layer ACT1. A first data line DL1 serving as a source electrode and a first drain electrode DRE1 are positioned on the interlayer insulating layer 130 . The first data line DL1 and the drain electrode DRE1 may be formed of a single layer or multiple layers, and in the case of a single layer, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti ), any one selected from the group consisting of nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. In addition, when the first data line DL1 and the first drain electrode DRE1 are multi-layered, they are a double layer of molybdenum/aluminum-neodymium, molybdenum/aluminum, or titanium/aluminum, or molybdenum/aluminum-neodymium/molybdenum, molybdenum/aluminum. / can be made of a triple layer of molybdenum or titanium / aluminum / titanium. The first data line DL1 and the first drain electrode DRE1 are connected to the first active layer ACT1 through the first source contact hole SCNT1 and the first drain contact hole DCNT1 formed in the interlayer insulating layer 130 . It is connected to a source region and a drain region, respectively.

A first passivation layer 140 is positioned on the first data line DL1 and the first drain electrode DRE1. The first passivation layer 140 protects the thin film transistor and is made of silicon oxide (SiOx), silicon nitride (SiNx) or a multi-layer thereof. An organic insulating layer 150 is positioned on the first passivation layer 140 . The organic insulating film 150 flattens the level difference at the bottom, and may be made of an organic material such as photo acryl, polyimide, benzocyclobutene resin, or acrylate resin. there is. A common electrode 160 is positioned on the organic insulating layer 150 . The common electrode 160 is integrally formed on the entire surface of the substrate 110 excluding holes to which a common voltage is applied, and may be made of a transparent conductive film. The transparent conductive layer may be a transparent and conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). A second passivation layer 170 is positioned on the common electrode 160 . The second passivation layer 170 is made of silicon oxide (SiOx), silicon nitride (SiNx), or a multi-layer thereof. A first pixel electrode PXL1 is positioned on the second passivation layer 170 . Like the common electrode 160, the first pixel electrode PXL1 is made of a transparent conductive film. Also, the first pixel electrode PXL1 contacts the first drain electrode DRE1 through the first via hole VIA1. Thus, a display device according to an embodiment of the present invention is configured.

5 is a plan view showing the size of a subpixel.

Referring to FIG. 5 , in the case of a black matrix (BM) used to prevent color mixing between red subpixels, green subpixels, and blue subpixels in a display device, the current minimum line width is known to be 4 μm. In some high-resolution models, for example, 800 ppi models, the minimum line width is applied, but in this case, the size of one pixel is 15.7 × 31.5 μm. Accordingly, the interval between patterns is about 12 μm, which is sufficient to form a black matrix. However, in a high-resolution, for example, 1550 ppi ultra-high resolution model, the pixel size is only 8.2 × 16㎛, and in this case, even if the minimum line width is applied to the black matrix, the distance between the black matrices is close to 4㎛ level, making it difficult to form patterns. there is.

Hereinafter, the structure of the embodiments of the present invention that can improve the above-related problems will be described.

<Example 1>

6 and 7 are cross-sectional views of color filter array substrates of the present invention, FIG. 8 is a plan view showing black matrices of the present invention, and FIG. 9 is a plan view showing a shape in which the black matrices of the present invention cross each other.

6 to 9, the color filter array substrate (CFS) of the present invention is formed to face the thin film transistor array substrate of FIG. 4 described above. In the color filter array substrate CFS, the first black matrix BM1 is positioned on the upper substrate UGL. The first black matrix BM1 is made of carbon black or a black resin including black pigment, and serves to block light from below. Accordingly, the first black matrix BM1 partitions subpixels.

The first black matrix BM1 of the present invention is formed in a lattice shape in which two parallel lines and two other parallel lines orthogonally intersect. More specifically, the first line L1 and the second line L2 are spaced apart from each other and disposed in parallel, and the third line L3 and the fourth line L4 are spaced apart from each other and are parallel to each other. At this time, the first line L1 and the second line L2 are orthogonal to the third line L3 and the fourth line L4 to form a lattice shape. The first line L1 and the second line L2 cross the third line L3 and the fourth line L4 at right angles to form a plurality of first openings OP1. Accordingly, the first black matrix BM1 transmits light through the plurality of first openings OP1 and covers the remaining area except for the plurality of first openings OP1, that is, the first line L1, the second line L2, Light is blocked from the third line (L3) and the fourth line (L4).

A color filter CF is positioned on the first black matrix BM1. The color filter CF is made of a color resin including color pigments representing red, green, and blue. The light incident to the color filter CF transmits only the light of the wavelength range of the color of the color filter CF and blocks the rest of the wavelength range. For example, when white light from a light source is incident on a red color filter, light in wavelength bands other than red is blocked and red light is transmitted. When white light from a light source is incident on the green color filter, light in the wavelength band except green is blocked and green light is transmitted. When white light from a light source is incident on the blue color filter, light in the wavelength band except blue is blocked and blue light is transmitted.

A second black matrix BM2 is positioned on the color filter CF. Like the first black matrix BM1 described above, the second black matrix BM2 of the present invention has a lattice shape in which two parallel lines and two other parallel lines orthogonally intersect. More specifically, the fifth line L5 and the sixth line L6 are spaced apart from each other and disposed in parallel, and the seventh line L7 and eighth line L8 are spaced apart from each other and are parallel to each other. At this time, the fifth line L5 and the sixth line L6 form a lattice shape perpendicular to the seventh line L7 and the eighth line L8. The fifth line L5 and the sixth line L6 are orthogonal to the seventh and eighth lines L7 and L8 to form a plurality of second openings OP2 . Accordingly, the second black matrix BM2 transmits light through the plurality of second openings OP2 and covers the remaining areas excluding the plurality of second openings OP2, that is, the fifth line L5, the sixth line L6, Light is blocked from the seventh line (L7) and the eighth line (L8).

A first overcoat layer OC1 is positioned on the second black matrix BM2. The first overcoat layer OC1 serves to flatten the surface by alleviating the level difference in the lower portion. The first overcoat layer OC1 is made of an organic material and is formed by coating in a liquid form. Accordingly, the lower step of the first overcoat layer OC1 may be alleviated. Unlike this, as shown in FIG. 7 , the second overcoat layer OC2 is positioned between the color filter CF and the second black matrix BM2 to alleviate the difference in level between the color filters CF.

As shown in FIGS. 7 and 8 , the first black matrix BM1 and the second black matrix BM2 of the present invention are disposed to cross each other.

For example, in the first black matrix BM1 of the present invention, each of the first line L1, the second line L2, the third line L3, and the fourth line L4 has a line width of 4 μm, and The distance between the first line L1 and the second line L2 and the distance between the third line L3 and the fourth line L4 may be 12 μm, respectively. Further, in the second black matrix BM2, each of the fifth line L5, the sixth line L6, the seventh line L7, and the eighth line L8 has a line width of 4 μm, and the fifth line L5 ) and the sixth line L6 and the seventh line L7 and eighth line L8 may be each formed to be 12 μm.

One of the plurality of first openings OP1 of the first black matrix BM1 overlaps four second openings OP2 of the plurality of second openings OP2 of the second black matrix BM2. One of the plurality of first openings OP1 and four second openings OP2 of the plurality of second openings OP2 overlap to define four sub-pixel parts SPP. Depending on the overlapping and crossing of the first black matrix BM1 and the second black matrix BM2, a 4×4 μm sub-pixel portion SSP may be partitioned. Accordingly, it is possible to partition fine-sized subpixels corresponding to high resolution. At this time, it is preferable that all four sub-pixel parts SSP have the same size, but the present invention is not limited thereto and the size of the sub-pixel part SSP may be formed differently if necessary.

Therefore, the present invention forms a first black matrix and a second black matrix in a lattice shape on a color filter array substrate, and arranges the lattice of the first black matrix and the lattice of the second black matrix to cross each other, thereby corresponding to high resolution. The sub-pixel part may be partitioned.

<Second Embodiment>

10 to 12 are plan views illustrating a first black matrix and a second black matrix according to a second embodiment of the present invention.

Referring to FIG. 10 , the first black matrix BM1 of the present invention is formed of a plurality of first patterns PT1, and each of the plurality of first patterns PT1 has a first straight line portion SL1 and a second pattern PT1. 1 includes a plurality of first protruding portions PR1 protruding in a direction perpendicular to the straight portion SL1. In more detail, the first pattern PT1 includes a plurality of first protrusions PR1 in which the first straight portion SL1 extends in the y-axis direction and protrudes in a direction perpendicular to the first straight portion SL1, that is, in the x-axis direction. ) are included. The plurality of first protrusions PR1 are spaced apart from each other by a predetermined interval. In addition, the plurality of first patterns PT1 are also spaced apart from each other by a predetermined interval.

In addition, the second black matrix BM2 of the present invention is formed of a plurality of second patterns PT2, and each of the plurality of second patterns PT2 has one second straight portion SL2 and a second straight portion ( It includes a plurality of second protrusions PR2 protruding in a direction perpendicular to SL2 . In more detail, the second pattern PT2 includes a plurality of second protrusions PR2 in which the second straight portion SL2 extends in the y-axis direction and protrudes in a direction perpendicular to the second straight portion SL2, that is, in the x-axis direction. ) are included. The plurality of second protrusions PR2 are spaced apart from each other by a predetermined interval. In addition, the plurality of second patterns PT2 are also spaced apart from each other by a predetermined interval.

Referring to FIG. 11 , the aforementioned first black matrix BM1 and second black matrix BM2 partially overlap to partition a plurality of sub-pixel parts SPP. In more detail, the first straight line portion SL1 of the first pattern PT1 of the first black matrix BM1 and the second straight portion SL2 of the second pattern PT2 of the second black matrix BM2 are mutually related to each other. They are spaced apart and placed side by side with each other. The first pattern PT1 of the first black matrix BM1 and the second pattern PT2 of the second black matrix BM2 are alternately disposed. Also, the first protrusion PR1 of the first pattern PT1 of the first black matrix BM1 overlaps the second straight portion SL2 of the adjacent second pattern PT2 of the second black matrix BM2. In addition, the second protruding part PR2 of the second pattern PT2 of the second black matrix BM2 overlaps the second straight part SL2 of the adjacent first pattern PT1 of the first black matrix BM1. .

That is, the plurality of sub-pixel parts SPP are partitioned by overlapping the plurality of first patterns PT1 of the first black matrix BM1 and the plurality of second patterns PT2 of the second black matrix BM2. can The sub-pixel part SPP partitioned by overlapping the first black matrix BM1 and the second black matrix BM2 may be finely formed corresponding to high resolution. For example, the width of the first straight portion SL1 of the first pattern PT1 of the first black matrix BM1 is 4 μm, and the first protrusion PR1 of the first pattern PT1 protrudes by 4.5 μm. , the distance between the first patterns PT1 is 12.5 μm, and the second black matrix BM2 is the same as the first black matrix BM1, and the second black matrix PT2 is 2 The straight line portion SL2 has a width of 4 μm, the second protruding portion PR2 of the second pattern PT2 protrudes by 4.5 μm, and the distance between the second patterns PT2 is 12.5 μm. can be formed In this case, when the first protrusion PR1 overlaps the second straight portion SL2 by 0.5 μm, a subpixel portion SPP having a width of 4 μm may be formed. That is, it is possible to partition sub-pixels of fine size corresponding to high resolution.

In this case, the plurality of sub-pixel parts SPP may have the same or different sizes. As shown in FIG. 11 , the plurality of sub-pixel parts SPP may have the same size as each other. On the other hand, as shown in FIG. 12 , the plurality of sub-pixel parts SPP may be formed to have different sizes. This is because when there is a margin in the alignment of the first black matrix BM1 and the second black matrix BM2, the plurality of sub-pixel parts SPP may be formed to have different sizes. For example, when the size of the red sub-pixel part R and the blue sub-pixel part B is formed small and the green sub-pixel part G is formed large, the red sub-pixel part R and the blue sub-pixel part R and the blue sub-pixel part are formed in an adjacent area. The size of the pixel portion B is formed large and the size of the green sub-pixel portion G is formed small. Accordingly, the aperture ratios of the final red sub-pixel part R, the green sub-pixel part G, and the blue sub-pixel part B may be equally compensated. Therefore, according to the present invention, the aperture ratios of the red sub-pixel part R, the green sub-pixel part G, and the blue sub-pixel part B can be equally compensated even if the sizes of the plurality of sub-pixel parts SPP are different from each other. can

As described above, in the display device according to the second embodiment of the present invention, the first black matrix and the second black matrix are formed in patterns including straight portions and protruding portions on a color filter array substrate, and By arranging the pattern and the pattern of the second black matrix to overlap each other, it is possible to partition a sub-pixel part having a fine size corresponding to high resolution.

As described above, the display device according to embodiments of the present invention forms a first black matrix and a second black matrix in different layers on a color filter array substrate, and overlaps the first black matrix and the second black matrix to achieve high resolution. It is possible to partition a sub-pixel part of a fine size corresponding to . In addition, there is an advantage in that the aperture ratio of each sub-pixel part can be compensated even if the first black matrix and the second black matrix are out of alignment.

Through the above description, those skilled in the art will understand that various changes and modifications are possible without departing from the spirit of the present invention. For example, the x-axis direction or the y-axis direction described in the embodiment of the present invention can be changed to opposite directions, and the size, number and shape of the touch driving electrodes and touch sensing electrodes constituting the common electrode , The position of the touch driving line or touch sensing line connected to each touch electrode can be arbitrarily and appropriately changed, and is not limited to that described in the embodiment of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the invention, but should be determined by the claims.

CFS: color filter array substrate UGL: upper substrate
BM1: first black matrix BM2: second black matrix
CF: color filter OC1: first overcoat layer
OC2: second overcoat layer

Claims (14)

a thin film transistor array substrate including a thin film transistor, a pixel electrode and a common electrode;
a color filter array substrate facing the thin film transistor array substrate; and
A liquid crystal layer interposed between the thin film transistor array substrate and the color filter array substrate;
The color filter array substrate,
upper substrate;
a first black matrix positioned on the upper substrate and formed in a lattice shape;
a color filter positioned on the first black matrix; and
A second black matrix positioned on the color filter and formed in a lattice shape;
The first black matrix and the second black matrix cross each other,
The color filter is disposed between the first black matrix and the second black matrix that cross each other;
Where the first black matrix and the second black matrix intersect, the first black matrix, the second black matrix, and the color filters vertically overlap each other. According to claim 1,
The first black matrix includes a plurality of first openings, and the second black matrix includes a plurality of second openings. According to claim 2,
One of the plurality of first openings of the first black matrix overlaps four second openings of the plurality of second openings of the second black matrix. According to claim 3,
A display device in which one of the plurality of first openings and four second openings of the plurality of second openings overlap to define four sub-pixel parts. According to claim 4,
All of the four sub-pixel parts have the same size. According to claim 1,
The color filter array substrate further includes a first overcoat layer positioned on the second black matrix. According to claim 6,
and a second overcoat layer between the color filter and the second black matrix. a thin film transistor array substrate including a thin film transistor, a pixel electrode and a common electrode;
a color filter array substrate facing the thin film transistor array substrate; and
A liquid crystal layer interposed between the thin film transistor array substrate and the color filter array substrate;
The color filter array substrate,
upper substrate;
a first black matrix positioned on the upper substrate and including a plurality of first patterns having first straight portions and a plurality of first protrusions protruding from the first straight portions;
a color filter positioned on the first black matrix; and
a second black matrix positioned on the color filter and including a plurality of second patterns having second straight parts and a plurality of second protrusions protruding from the second straight parts;
The plurality of first patterns and the plurality of second patterns partially overlap,
The color filter is disposed between the plurality of first patterns and the plurality of second patterns overlapping each other;
In an overlapping area between the plurality of first patterns and the plurality of second patterns, the plurality of first patterns, the plurality of second patterns, and the color filter vertically overlap each other. According to claim 8,
The first straight line portion and the second straight line portion are spaced apart from each other and arranged side by side. According to claim 8,
The display device of claim 1 , wherein the first protrusion overlaps the second straight portion. According to claim 8,
A display device in which a plurality of sub-pixel parts are partitioned by overlapping the plurality of first patterns and the plurality of second patterns. According to claim 11,
The plurality of sub-pixel parts have the same size or different sizes. According to claim 8,
The color filter array substrate further includes a first overcoat layer positioned on the second black matrix. According to claim 13,
and a second overcoat layer between the color filter and the second black matrix.

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