KR20170064127A - Display device - Google Patents

Abstract

A display device according to an embodiment of the present invention discloses forming a fine pattern of a black matrix to correspond to a high resolution. The display device includes a thin film transistor array substrate, a color filter array substrate, and a liquid crystal layer. The thin film transistor array substrate includes a thin film transistor, a pixel electrode, and a common electrode. The color filter array substrate includes an upper substrate, a first black matrix, and a second black matrix. The first black matrix is disposed on the upper substrate and has a lattice shape, and the second black matrix is disposed on the first black matrix and is formed in a lattice shape. The first black matrix and the second black matrix cross each other.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device.

In general, a liquid crystal display device is driven by using optical anisotropy and polarization properties of a liquid crystal. Since the structure of the liquid crystal is narrow and long, it has a directionality in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal. The molecular arrangement is changed, and light is refracted in the direction of molecular arrangement of the liquid crystal due to optical anisotropy, so that image information can be expressed.

Currently, an active matrix liquid crystal display (AM-LCD: hereinafter referred to as a liquid crystal display) in which a thin film transistor and a pixel electrode connected to the thin film transistor are arranged in a matrix manner has excellent resolution and video realization capability It is attracting attention. The liquid crystal display device includes a color filter substrate on which a common electrode is formed, an array substrate on which pixel electrodes are formed, and a liquid crystal interposed between the two substrates. In such a liquid crystal display device, The liquid crystal is driven to have excellent properties such as transmittance and aperture ratio. However, liquid crystal driving by an electric field that is applied up and down has a drawback that the viewing angle characteristic is not excellent. Therefore, a transverse electric field type liquid crystal display device having excellent viewing angle characteristics has been proposed to overcome the above disadvantages. The transverse electric field type liquid crystal display device has an advantage that the viewing angle is improved by driving the liquid crystal using the horizontal electric field between the pixel electrode and the common electrode.

In recent years, as the resolution of the display device has increased and the pixel per inch (PPI) has increased, the pitch of pixels has been decreasing. As the pitch of the pixels is reduced, the pitch of the black matrix formed on the color filter substrate of the display device must also be reduced. However, due to the characteristics of the black matrix, it is difficult to form a fine pattern and it is difficult to cope with a high resolution.

The present invention provides a display device capable of forming a fine pattern of a black matrix to correspond to a high resolution.

In order to achieve the above object, a display device according to an embodiment of the present invention discloses forming a fine pattern of a black matrix to correspond to a high resolution. The display device includes a thin film transistor array substrate, a color filter array substrate, and a liquid crystal layer. The thin film transistor array substrate includes a thin film transistor, a pixel electrode, and a common electrode. The color filter array substrate includes an upper substrate, a first black matrix, and a second black matrix. The first black matrix is disposed on the upper substrate and has a lattice shape, and the second black matrix is disposed on the first black matrix and is formed in a lattice shape. The first black matrix and the second black matrix cross each other.

The first black matrix includes a plurality of first openings, and the second black matrix includes a plurality of second openings.

One of the plurality of first openings of the first black matrix is overlapped with four of the plurality of second openings of the second black matrix.

One of the plurality of first openings and the four second openings out of the plurality of second openings overlap to divide the four sub-pixel portions.

The four sub-pixel portions are all the same in size.

The color filter array substrate further includes a color filter positioned between the first black matrix and the second black matrix, and a first overcoat layer located on the second black matrix.

And a second overcoat layer between the color filter and the second black matrix.

Further, a display device according to an embodiment of the present invention includes a thin film transistor array substrate, a color filter array substrate, and a liquid crystal layer. The thin film transistor array substrate includes a thin film transistor, a pixel electrode, and a common electrode. The color filter array substrate includes a first black matrix and a second black matrix. The first black matrix is disposed on the upper substrate and includes a plurality of first patterns having a plurality of first protrusions protruding from the first rectilinear section and the first rectilinear section. The second black matrix includes a plurality of second patterns located on the first black matrix and having a plurality of second protrusions protruding from the second rectilinear section and the second rectilinear section. A plurality of first patterns and a plurality of second patterns partially overlap.

The first rectilinear section and the second rectilinear section are arranged to be spaced apart from each other.

The first projecting portion overlaps with the second straight line portion.

A plurality of sub-pixel portions are partitioned by overlapping a plurality of first patterns and a plurality of second patterns.

The plurality of sub-pixel portions have the same or different sizes.

The color filter array substrate further includes a color filter positioned between the first black matrix and the second black matrix, and a first overcoat layer located on the second black matrix.

And a second overcoat layer between the color filter and the second black matrix.

The display device according to the embodiments of the present invention may be configured such that the first black matrix and the second black matrix are formed on different layers on the color filter array substrate and the first black matrix and the second black matrix are overlapped with each other, Size sub-pixel portion can be partitioned. Further, there is an advantage that even if the first black matrix and the second black matrix are aligned, the aperture ratio of each sub-pixel portion can be compensated.

1 is a block diagram showing a display device according to an embodiment of the present invention;
2 is a circuit diagram showing pixels of a display device;
3 is a plan view showing a unit pixel of a display device according to an embodiment of the present invention.
4 is a cross-sectional view taken along line I-I 'of FIG. 3;
5 is a plan view showing a size of a subpixel.
Figures 6 and 7 are cross-sectional views of color filter array substrates of the present invention.
8 is a plan view showing a first black matrix and a second black matrix according to the first embodiment of the present invention.
9 is a plan view showing a shape in which a first black matrix and a second black matrix intersect according to the first embodiment of the present invention.
10 to 12 are plan views showing a first black matrix and a second black matrix according to a second embodiment of the present invention;

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description, a detailed description of known technologies or configurations related to the present invention will be omitted when it is determined that the gist of the present invention may be unnecessarily obscured. In addition, the component names used in the following description may be selected in consideration of easiness of specification, and may be different from the parts names of actual products.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a display device according to an embodiment of the present invention, and FIG. 2 is a circuit diagram showing pixels of a display device.

Referring to FIG. 1, a display device according to an exemplary embodiment of the present invention includes a display panel 100, a data driving circuit 102, a gate driving circuit 103, and a timing controller 101. A backlight unit for uniformly irradiating light to the liquid crystal display panel may be disposed below the liquid crystal display panel. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The display panel 100 includes a thin film transistor array substrate (or a first substrate) and a color filter array substrate (or a second substrate) facing each other with a liquid crystal layer interposed therebetween. In the liquid crystal display panel 100, a pixel array for displaying video data is formed. The pixel array includes pixels arranged in a matrix form by an intersection structure of the data lines and the gate lines to display video data. The pixels may be R pixels, G pixels, and B pixels. Neighboring pixels share the same data line. The liquid crystal cells of the pixels display an image of the video data by adjusting the amount of light transmission by the electric field difference between the data voltage applied to the pixel electrode and the common voltage applied to the common electrode. The common electrode is formed on a color filter array substrate in a vertical electric field driving method such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode. The common electrode is horizontally arranged in the IPS (In Plane Switching) mode and the FFS And is formed on the thin film transistor array substrate together with the pixel electrode in the electric field driving system.

The thin film transistor array substrate includes pixel electrodes connected to data lines, gate lines, thin film transistors, and thin film transistors at a ratio of 1: 1, storage capacitors (not shown) connected to the pixel electrodes at 1: Cst) and the like. On the color filter array substrate of the display panel 100, a black matrix and a color filter are formed. In this embodiment, a common electrode is formed on the thin film transistor array substrate. A polarizing plate is attached to each of the color filter array substrate and the TFT array substrate of the display panel 100 to form an alignment film for setting a pre-tilt angle of the liquid crystal.

The liquid crystal display panel 100 applicable to the present invention can be implemented in any liquid crystal mode as well as a TN mode, a VA mode, an IPS mode, and an FFS mode. The liquid crystal display device of the present invention can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, and a reflective liquid crystal display device. In a transmissive liquid crystal display device and a transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The data driving circuit 102 includes a plurality of source drive ICs. The output channels of the source drive ICs are connected 1: 1 to the data lines of the pixel array. Each of the source drive ICs receives digital video data from the timing controller 101. The source driver ICs convert the digital video data into positive / negative data voltages in response to a source timing control signal from the timing controller 101 and supply the data lines through the output channels to the data lines of the pixel array. The source drive ICs supply data voltages of opposite polarities to neighboring data lines under the control of the timing controller 101 and maintain the polarities of the data voltages supplied to the respective data lines to remain the same for one frame period , The polarity of the data voltage is inverted in the next frame period. Thus, the source drive ICs maintain the polarity of the data voltages the same for one frame period, substantially the same as the column-inversion method, and reverse the polarity of the data voltage at one frame period.

The gate driving circuit 103 sequentially supplies gate pulses to the gate lines of the pixel array in response to the gate timing control signal from the timing controller 101. [ The timing controller 101 supplies the digital video data input from the external system board 104 to the source drive ICs of the data driving circuit 102. The timing controller 101 generates a source timing control signal for controlling the operation timing of the data driving circuit 102 and a gate timing control signal for controlling the operation timing of the gate driving circuit 103.

2, the display apparatus of the present invention converts digital video data into an analog data voltage based on a gamma reference voltage and supplies the analog data voltage to a data line DL and a scan pulse to a gate line GL, And charges the liquid crystal cell Clc with the data voltage. To this end, the gate electrode of the thin film transistor is connected to the gate line GL, the source electrode thereof is connected to the data line DL, and the drain electrode of the thin film transistor is connected to the pixel electrode of the liquid crystal cell Clc and the storage capacitor Cst1 As shown in Fig. A common voltage Vcom is supplied to the common electrode of the liquid crystal cell Clc. The storage capacitor Cst1 functions to maintain the voltage of the liquid crystal cell Clc constant by charging the data voltage applied from the data line DL when the thin film transistor is turned on. When a scan pulse is applied to the gate line GL, the TFT is turned on to form a channel between the source electrode and the drain electrode to apply a voltage on the data line DL to the pixel electrode of the liquid crystal cell Clc Supply. At this time, the liquid crystal molecules of the liquid crystal cell Clc are changed in arrangement by the electric field between the pixel electrode and the common electrode to change the incident light. As a result, the display device of the present invention is operated.

The schematic configuration of the display device according to the embodiment of the present invention has been described above. Hereinafter, the pixel array structure of the display panel of the display device will be described in detail. 1 and 2 are denoted by different reference numerals.

3 is a plan view showing a unit pixel of a display device according to an embodiment of the present invention.

Referring to FIG. 3, a display device 100 according to an exemplary embodiment of the present invention includes a plurality of pixel units P1, P2, and P3 to form one unit pixel. The plurality of pixel portions each include a first pixel portion P1, a second pixel portion P2, and a third pixel portion P3. Each of the first pixel portion P1, the second pixel portion P2 and the third pixel portion P3 includes a gate line GL extended in the horizontal direction and a first data line GL intersecting the gate line GL DL1, a second data line DL2, and a third data line DL3. In the exemplary embodiment of the present invention, the first through third pixel portions P1, P2, and P3 are configured to include one unit pixel, but the present invention is not limited thereto. The unit pixel may include four or five or more pixel portions It is possible.

The first pixel portion P1 of the present invention is partitioned by the intersection of the gate line GL and the first data line DL1. The first pixel unit P1 includes a first thin film transistor TR1 at the intersection of the gate line GL and the first data line DL1 and a first pixel electrode TR1 connected to the first thin film transistor TR1. PXL1. The first thin film transistor TR1 of the first pixel portion P1 includes a first active layer ACT1, a gate line GL serving as a gate electrode, a first data line DL1 serving as a source electrode, And a drain electrode DRE1. The first active layer ACT1 overlaps with the first data line DL1 to have a U-shape, so that the first active layer ACT1 crosses the gate line GL twice. The first data line DL1 serving as a source electrode extends in a straight line and contacts one end of the first active layer ACT1 by a first source contact hole SCNT1. The first source contact hole SCNT1 overlaps the first data line DL1 because the first data line DL1 serves as a source electrode. The first drain electrode DRE1 contacts the other end of the first active layer ACT1 by the first drain contact hole DCNT1. The first drain contact hole DCNT1 is spaced apart from the gate line GL without overlapping. The first pixel electrode PXL1 is branched into a finger shape and arranged in parallel with the first data line DL1. The first pixel electrode PXL1 is connected to the first drain electrode DRE1 of the first thin film transistor TR1 through the first via hole VIA1. The first via hole VIA1 overlaps the gate line GL adjacent to the first drain contact hole DCNT1. Although not shown, the first pixel electrode PXL1 forms an electric field opposite to the common electrode. The common electrode will be described in the cross-sectional structure described later.

In this figure, the channel region of the thin film transistor is shown as 'U'. However, the present invention is not limited to this, and the channel region may also be formed as 'I'. In addition, although the thin film transistor has been illustrated by way of example in which the gate electrode is formed by the gate line itself, the thin film transistor is not limited thereto and may be protruded from the gate line.

Meanwhile, the second pixel portion P2 of the present invention is partitioned by the intersection of the gate line GL and the second data line DL2. The second pixel unit P2 includes a second thin film transistor TR2 at the intersection of the gate line GL and the second data line DL2 and a second pixel electrode TR2 connected to the second thin film transistor TR2. PXL2. The second thin film transistor TR2 of the second pixel portion P2 includes a second active layer ACT2, a gate line GL serving as a gate electrode, a second data line DL2 serving as a source electrode, Drain electrode DRE2. The second active layer ACT2 overlaps with the second data line DL2 to have a U-shape, so that the second active layer ACT2 crosses the gate line GL twice. The second data line DL2 serving as the source electrode is connected to one end of the second active layer ACT2 by the second source contact hole SCNT2. The second source contact hole SCNT2 overlaps the second data line DL2 because the second data line DL2 serves as the source electrode. The second drain electrode DRE2 contacts the other end of the second active layer ACT2 by the second drain contact hole DCNT2. The second drain contact hole DCNT2 is not overlapped with the gate line GL but is spaced apart. The second pixel electrode PXL2 is branched in a finger shape and arranged in parallel with the second data line DL2. And the second pixel electrode PXL2 is connected to the second drain electrode DRE2 of the second thin film transistor TR2 through the second via hole VIA2. The second via hole VIA2 overlaps the second drain contact hole DCNT2 and the adjacent gate line GL. The second pixel electrode PXL2 forms an electric field opposite to the common electrode.

The third pixel portion P3 of the present invention is partitioned by the intersection of the gate line GL and the third data line DL3. The third pixel unit P3 includes a third thin film transistor TR3 at the intersection of the gate line GL and the third data line DL3 and a third pixel electrode TR3 connected to the third thin film transistor TR3. PXL3. The third thin film transistor TR3 of the third pixel portion P3 includes a third active layer ACT3, a gate line GL serving as a gate electrode, a third data line DL3 serving as a source electrode, Drain electrode DRE3. The third active layer ACT3 overlaps the third data line DL3 and has the U-shape, so that the third active layer ACT3 crosses the gate line GL twice. And the third data line DL3 serving as the source electrode is connected to one end of the third active layer ACT3 by the third source contact hole SCNT3. The third source contact hole SCNT3 overlaps the third data line DL3 because the third data line DL3 functions as a source electrode. The third drain electrode DRE3 is connected to the other end of the third active layer ACT3 by the third drain contact hole DCNT3. The third drain contact hole DCNT3 is not overlapped with the gate line GL but is spaced apart. The third pixel electrode PXL3 is branched into a finger shape and arranged in parallel with the third data line DL3. The third pixel electrode PXL3 is connected to the third drain electrode DRE3 of the third thin film transistor TR3 through the third via hole VIA3. The third via hole VIA3 overlaps the third drain contact hole DCNT3 and the adjacent gate line GL. The third pixel electrode PXL3 forms an electric field opposite to the common electrode.

In the display device 100 according to an embodiment of the present invention, the first to third pixel units are formed of one unit pixel and are regularly arranged throughout the display device 100. [

Hereinafter, a cross-sectional structure of a display device according to an embodiment of the present invention will be described with reference to FIG. 4, which is a cross-sectional view taken along line I-I 'of FIG.

Referring to FIG. 4, a display device 100 according to an exemplary embodiment of the present invention is a thin film transistor of a coplanar type structure in which a gate electrode is located on an active layer.

More specifically, the light blocking film LS is located on the substrate 110. [ The substrate 110 is made of transparent or opaque glass, plastic or metal. The light blocking film LS is for blocking external light from entering the inside, and is made of a material capable of blocking light. The light-shielding film LS is made of a material having a low reflectance. For example, the light-shielding film LS may be made of a resin including a black coloring material such as carbon black or a resin containing amorphous silicon (a-Si), germanium (Ge), tantalum oxide (TaOx) And copper oxide (CuOx). The buffer layer 120 is positioned on the entire substrate 110 on which the light shielding film LS is disposed. The buffer layer 120 is formed to protect a thin film transistor formed in a subsequent process from an impurity such as an alkali ion or the like flowing out from the substrate 110 or the lower layers. The buffer layer 120 may be formed of silicon oxide (SiOx), silicon nitride .

A first active layer (ACT1) is located on the buffer layer (120). The first active layer ACT1 is made of an oxide semiconductor. For example, the a-IGZO semiconductor is sputtered by using a composite target of gallium oxide (Ga ₂ O ₃ ), indium oxide (In ₂ O ₃ ), and zinc oxide (ZnO) as an amorphous zinc oxide- sputtering method. In addition, a chemical vapor deposition method such as chemical vapor deposition or atomic layer deposition (ALD) may be used. Here, in the case of the embodiment of the present invention, an oxide target having an atomic ratio of gallium, indium and zinc of 1: 1: 1, 2: 2: 1, 3: 2: 1 and 4: A semiconductor can be deposited. However, the active layer of the present invention is not limited to the zinc oxide-based semiconductor.

The first active layer ACT1 includes two channels (CH, CH). The channel CH corresponds to a region overlapping with a gate line GL serving as a gate electrode. A gate insulating film 125 is disposed on the first active layer ACT1. The gate insulating film 125 is formed of a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof. The gate insulating film 125 isolates the gate line GL from the first active layer ACT1. A gate line GL is located on the gate insulating film 125. [ The gate line GL may be formed of a material selected from the group consisting of copper (Cu), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), tantalum And tungsten (W), or an alloy thereof. The gate line GL is located corresponding to the channel CH of the first active layer ACT1.

The interlayer insulating layer 130 is disposed on the substrate 110 on which the gate lines GL are formed. The interlayer insulating film 130 is formed of a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof. The interlayer insulating layer 130 is provided with a first source contact hole SCNT1 and a first drain contact hole DCNT1 that expose source and drain regions on both sides of the first active layer ACT1. A first data line DL1 and a first drain electrode DRE1 serving as a source electrode are positioned on the interlayer insulating layer 130. [ The first data line DL1 and the drain electrode DRE1 may be formed of a single layer or a multilayer and may be formed of a metal such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au) ), Nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. When the first data line DL1 and the first drain electrode DRE1 are multilayered, a double layer of molybdenum / aluminum-neodymium, molybdenum / aluminum or titanium / aluminum or molybdenum / aluminum-neodymium / molybdenum, molybdenum / aluminum / Molybdenum or a triple layer of titanium / aluminum / titanium. The first data line DL1 and the first drain electrode DRE1 are electrically connected to the first active layer ACT1 through the first source contact hole SCNT1 formed in the interlayer insulating layer 130 and the first drain contact hole DCNT1. Source region and a drain region, respectively.

The first passivation film 140 is located on the first data line DL1 and the first drain electrode DRE1. The first passivation film 140 protects the thin film transistor and is made of silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer thereof. An organic insulating film 150 is disposed on the first passivation film 140. The organic insulating layer 150 may be formed of an organic material such as photo acryl, polyimide, benzocyclobutene resin, acrylate resin, or the like, have. The common electrode 160 is positioned on the organic insulating layer 150. The common electrode 160 is integrally formed on the entire surface of the substrate 110 except for the holes and is applied with a common voltage and may be formed of a transparent conductive film. The transparent conductive film may be a transparent and conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide). The second passivation film 170 is located on the common electrode 160. The second passivation film 170 is made of silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer thereof. And the first pixel electrode PXL1 is located on the second passivation film 170. [ The first pixel electrode PXL1 is formed of a transparent conductive film like the common electrode 160. Also, the first pixel electrode PXL1 contacts the first drain electrode DRE1 through the first via hole VIA1. Therefore, a display device according to an embodiment of the present invention is constituted.

5 is a plan view showing a size of a subpixel.

Referring to FIG. 5, in the case of a black matrix (BM) used to prevent color mixing between red subpixels, green subpixels, and blue subpixels in a display device, the current minimum line width is known to be 4 μm. In some high resolution models, for example 800 ppi, the minimum line width is applied, but in this case the size of one pixel is 15.7 × 31.5 μm. Therefore, the spacing between the patterns is about 12 占 퐉, which is enough to form the black matrix. However, for example, in a high-resolution model with a high resolution of 1550 ppi, the pixel size is only 8.2 × 16 μm. In this case, even if the minimum line width is applied, the black matrix has a gap of 4 μm, have.

Hereinafter, the structure of embodiments of the present invention capable of solving the above problems will be described.

≪ Example 1 >

FIGS. 6 and 7 are cross-sectional views of the color filter array substrates of the present invention, FIG. 8 is a plan view of the black matrix of the present invention, and FIG. 9 is a plan view of a cross section of the black matrix of the present invention.

Referring to Figs. 6 to 9, the color filter array substrate CFS of the present invention is formed opposite to the thin film transistor array substrate of Fig. 4 described above. The color filter array substrate CFS has the first black matrix BM1 on the upper substrate UGL. The first black matrix BM1 is made of a black resin containing carbon black or a pigment of black, and serves to shield the lower light. Thus, the first black matrix BM1 delimits subpixels.

The first black matrix BM1 of the present invention has a lattice shape in which two parallel lines and two other parallel lines are perpendicular to each other. In more detail, the first line L1 and the second line L2 are arranged in parallel with each other, and the third line L3 and the fourth line L4 are spaced apart from each other and become parallel. At this time, the first line L1 and the second line L2 form a lattice orthogonal to the third line L3 and the fourth line L4. The first line L1 and the second line L2 are perpendicular to the third line L3 and the fourth line L4 to form a plurality of first openings OP1. Accordingly, the first black matrix BM1 transmits light in the plurality of first openings OP1 and the remaining regions excluding the plurality of first openings OP1, that is, the first line L1, the second line L2, The third line L3 and the fourth line L4.

A color filter CF is disposed on the first black matrix BM1. The color filter CF is made of a color resin including color pigments representing red, green and blue. The light incident on the color filter CF transmits only the light of the color wavelength of the corresponding color filter CF and blocks the remaining wavelength band. For example, when a white light of a light source is incident on a red color filter, the light of the remaining wavelength except red is blocked and red light is transmitted. When the white light of the light source is incident on the green color filter, the light of the remaining wavelength except green is cut off and the green light is transmitted. When the white light of the light source is incident on the blue color filter, the light of the remaining wavelength range except blue is blocked and the blue light is transmitted.

 A second black matrix BM2 is located on the color filter CF. The second black matrix BM2 of the present invention has a lattice shape in which two parallel lines and two other parallel lines are orthogonal to each other like the first black matrix BM1 described above. In more detail, the fifth line L5 and the sixth line L6 are arranged apart from each other in parallel, and the seventh line L7 and the eighth line L8 are spaced apart from each other and become parallel. At this time, the fifth line L5 and the sixth line L6 intersect the seventh line L7 and the eighth line L8 in a lattice shape. The fifth line L5 and the sixth line L6 are orthogonal to the seventh line L7 and the eighth line L8 to form a plurality of second openings OP2. Therefore, the second black matrix BM2 transmits light in the plurality of second openings OP2 and the remaining regions except for the plurality of second openings OP2, i.e., the fifth line L5, the sixth line L6, The seventh line L7 and the eighth line L8.

And the first overcoat layer OC1 is located on the second black matrix BM2. The first overcoat layer OC1 serves to smooth the surface by relaxing the lower step. The first overcoat layer OC1 is formed by a method of coating an organic material in the form of a liquid. Therefore, the lower step of the first overcoat layer OC1 can be relaxed. The second overcoat layer OC2 is positioned between the color filter CF and the second black matrix BM2 as shown in Fig. 7, so that the step of the color filter CF can be relaxed.

As shown in FIGS. 7 and 8, the first black matrix BM1 and the second black matrix BM2 of the present invention are arranged so as to cross each other.

For example, in the first black matrix BM1 of the present invention, the line widths of the first line L1, the second line L2, the third line L3 and the fourth line L4 are each 4 μm, The interval between the first line L1 and the second line L2 and the interval between the third line L3 and the fourth line L4 may be 12 mu m. The line widths of the fifth line L5, the sixth line L6, the seventh line L7 and the eighth line L8 of the second black matrix BM2 are respectively 4 占 퐉 and the fifth line L5 ) And the sixth line L6 and the interval between the seventh line L7 and the eighth line L8 may be 12 占 퐉, respectively.

One of the plurality of first openings OP1 of the first black matrix BM1 overlaps with the second plurality of openings OP2 of the plurality of second openings OP2 of the second black matrix BM2. One of the plurality of first openings OP1 and the four second openings OP2 of the plurality of second openings OP2 overlap to divide the four subpixel portions SPP. The sub pixel unit SSP of 4 x 4 mu m can be divided according to the superposition and the intersection of the first black matrix BM1 and the second black matrix BM2. Therefore, it is possible to divide subpixels of a small size corresponding to high resolution. At this time, it is preferable that the four subpixel portions (SSP) have the same size, but the present invention is not limited thereto, and the size of the subpixel portion (SSP) may be formed differently if necessary.

Therefore, in the present invention, the first black matrix and the second black matrix are formed in a lattice shape on the color filter array substrate, and the lattice of the first black matrix and the lattice of the second black matrix cross each other, The sub-pixel portion can be partitioned.

≪ Embodiment 2 >

10 to 12 are plan views showing a first black matrix and a second black matrix according to a second embodiment of the present invention.

Referring to FIG. 10, the first black matrix BM1 of the present invention is formed of a plurality of first patterns PT1, and each of the plurality of first patterns PT1 includes a first straight line portion SL1, And a plurality of first protrusions PR1 protruding in a direction perpendicular to the first linear portion SL1. More specifically, the first pattern PT1 includes a plurality of first protrusions PR1 extending in the y-axis direction of the first rectilinear section SL1 and extending in the direction perpendicular to the first rectilinear section SL1, that is, in the x- ). The plurality of first projections PR1 are spaced apart by a predetermined distance. Also, the plurality of first patterns PT1 are spaced apart from each other by a predetermined distance.

The second black matrix BM2 of the present invention is formed of a plurality of second patterns PT2 and each of the plurality of second patterns PT2 includes a second straight line portion SL2 and a second straight line portion And a plurality of second protrusions PR2 protruding in a direction perpendicular to the first protrusions PR2. More specifically, the second pattern PT2 includes a plurality of second protrusions PR2 extending in the y-axis direction of the second rectilinear section SL2 and extending in the direction perpendicular to the second rectilinear section SL2, that is, in the x- ). The plurality of second projections PR2 are disposed apart from each other by a predetermined distance. The plurality of second patterns PT2 are also spaced apart from each other by a predetermined distance.

Referring to FIG. 11, the first black matrix BM1 and the second black matrix BM2 may be partially overlapped to divide a plurality of subpixel portions SPP. More specifically, the first rectilinear section SL1 of the first pattern PT1 of the first black matrix BM1 is connected to the second rectilinear section SL2 of the second pattern PT2 of the second black matrix BM2 Spaced and arranged side by side. The first pattern PT1 of the first black matrix BM1 and the second pattern PT2 of the second black matrix BM2 are alternately arranged. The first projecting portion PR1 of the first pattern PT1 of the first black matrix BM1 overlaps the second straight line portion SL2 of the second pattern PT2 of the adjacent second black matrix BM2. The second projecting portion PR2 of the second pattern PT2 of the second black matrix BM2 overlaps the second straight line portion SL2 of the first pattern PT1 of the adjacent first black matrix BM1 .

That is, by overlapping the plurality of first patterns PT1 of the first black matrix BM1 and the plurality of second patterns PT2 of the second black matrix BM2, a plurality of subpixel portions SPP are partitioned . The subpixel portions SPP partitioned by the overlap of the first black matrix BM1 and the second black matrix BM2 can be finely formed corresponding to high resolution. For example, when the width of the first straight line portion SL1 of the first pattern PT1 of the first black matrix BM1 is 4 占 퐉 and the first projecting portion PR1 of the first pattern PT1 is protruded by 4.5 占 퐉 The distance between the first patterns PT1 is 12.5 占 퐉 and the second black matrix BM2 is formed in the same manner as the first black matrix BM1. The second straight line segment SL2 has a width of 4 占 퐉 and the second protrusions PR2 of the second pattern PT2 are protruded by 4.5 占 퐉 and the distance between the second patterns PT2 is 12.5 占 퐉 . At this time, if the first projecting portion PR1 is overlapped with the second straight portion SL2 by 0.5 占 퐉, the sub-pixel portion SPP having a width of 4 占 퐉 can be formed. That is, subpixels of a small size corresponding to a high resolution can be partitioned.

At this time, the plurality of subpixel portions SPP may have the same or different sizes. As shown in FIG. 11, the plurality of sub-pixel portions SPP may be formed to have the same size. On the other hand, as shown in FIG. 12, the plurality of sub-pixel portions SPP may be formed to have different sizes. If there is a margin in the alignment between the first black matrix BM1 and the second black matrix BM2, the plurality of subpixel portions SPP may be formed to have different sizes. For example, when the red subpixel portion R and the blue subpixel portion B are formed to be small in size and the green subpixel portion G is formed to be large, the red subpixel portion R and the blue subpixel portion R The pixel portion B is formed to have a large size and the green sub-pixel portion G is formed to be small. Accordingly, the aperture ratios of the final red subpixel portion R, green subpixel portion G, and blue subpixel portion B can be compensated equally. Therefore, even if the plurality of subpixel portions SPP are formed to have different sizes, the present invention can equally compensate the aperture ratios of the red subpixel portion R, the green subpixel portion G, and the blue subpixel portion B .

As described above, in the display device according to the second embodiment of the present invention, the first black matrix and the second black matrix are formed on the color filter array substrate with the patterns including the straight line portion and the projection portion, and the first black matrix By arranging the pattern and the pattern of the second black matrix so as to overlap with each other, it is possible to divide the sub-pixel portion having a small size corresponding to the high resolution.

As described above, in the display device according to the embodiments of the present invention, the first black matrix and the second black matrix are formed in different layers on the color filter array substrate, and the first black matrix and the second black matrix are overlapped with each other, Pixel subpixel portion corresponding to the subpixel portion corresponding to the subpixel portion. Further, there is an advantage that even if the first black matrix and the second black matrix are aligned, the aperture ratio of each sub-pixel portion can be compensated.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. For example, the x-axis direction and the y-axis direction described in the embodiment of the present invention can be changed in directions opposite to each other, and the size, number and shape of the touch driving electrode and the touch sensing electrode constituting the common electrode , The positions of the touch driving line and the touch sensing line connected to the respective touch electrodes can be arbitrarily changed appropriately and are not limited to those described in the embodiments of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the invention but should be defined by the claims.

CFS: color filter array substrate UGL: upper substrate
BM1: first black matrix BM2: second black matrix
CF: color filter OC1: first overcoat layer
OC2: second overcoat layer

Claims (14)

A thin film transistor array substrate including a thin film transistor, a pixel electrode, and a common electrode;
A color filter array substrate facing the thin film transistor array substrate; And
And a liquid crystal layer interposed between the thin film transistor array substrate and the color filter array substrate,
The color filter array substrate includes:
An upper substrate;
A first black matrix disposed on the upper substrate and having a lattice shape; And
And a second black matrix located on the first black matrix and in a lattice shape,
Wherein the first black matrix and the second black matrix cross each other. The method according to claim 1,
Wherein the first black matrix includes a plurality of first openings, and the second black matrix includes a plurality of second openings. 3. The method of claim 2,
Wherein one of the plurality of first openings of the first black matrix overlaps with four second openings of the plurality of second openings of the second black matrix. The method of claim 3,
And one of the plurality of first openings overlaps with four second openings of the plurality of second openings to divide the four sub-pixel portions. 5. The method of claim 4,
Wherein the four sub-pixel portions are all the same size. The method according to claim 1,
The color filter array substrate includes:
A color filter positioned between the first black matrix and the second black matrix; And
And a first overcoat layer disposed on the second black matrix. The method according to claim 6,
And a second overcoat layer between the color filter and the second black matrix. A thin film transistor array substrate including a thin film transistor, a pixel electrode, and a common electrode;
A color filter array substrate facing the thin film transistor array substrate; And
And a liquid crystal layer interposed between the thin film transistor array substrate and the color filter array substrate,
The color filter array substrate includes:
An upper substrate;
A first black matrix disposed on the upper substrate and including a plurality of first patterns having a first rectilinear section and a plurality of first protrusions protruding from the first rectilinear section; And
And a second black matrix disposed on the first black matrix and including a plurality of second patterns having a second rectilinear section and a plurality of second protrusions protruding from the second rectilinear section,
Wherein the plurality of first patterns and the plurality of second patterns partially overlap each other. 9. The method of claim 8,
Wherein the first rectilinear section and the second rectilinear section are spaced apart from each other and arranged in parallel. 9. The method of claim 8,
And the first projecting portion overlaps with the second straight line portion. 9. The method of claim 8,
And a plurality of sub-pixel portions are partitioned by overlapping the plurality of first patterns and the plurality of second patterns. 12. The method of claim 11,
Wherein the plurality of sub-pixel portions have the same or different sizes. 9. The method of claim 8,
The color filter array substrate includes:
A color filter positioned between the first black matrix and the second black matrix; And
And a first overcoat layer disposed on the second black matrix. 14. The method of claim 13,
And a second overcoat layer between the color filter and the second black matrix.

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