CN112133708B - Display panel, display device and manufacturing method of display panel - Google Patents
Display panel, display device and manufacturing method of display panel Download PDFInfo
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- H—ELECTRICITY
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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- G—PHYSICS
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
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- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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Abstract
The invention provides a display panel, a display device and a manufacturing method of the display panel, wherein the display panel comprises a display area and a non-display area, the display area surrounds the non-display area, the non-display area comprises a module setting area, and the light transmittance of the display panel in the module setting area is larger than a preset value; the display panel includes an array substrate, the array substrate including: a first substrate; a buffer layer on one side of the first substrate; the thin film transistors are positioned on one side of the buffer layer, which is far away from the first substrate; the film layers of the thin film transistors are only present in the non-display area except the module setting area and the display area; the buffer layer is arranged in the display area and the non-display area and covers the module setting area. The invention improves the light transmittance of the display panel in the module setting area, reduces the process procedures and improves the production efficiency.
Description
The application is divisional application with application number 201811162738.2, application date 2018, 09 and 30, and invention title "a display panel, a display device, and a manufacturing method of the display panel".
Technical Field
The invention relates to the technical field of display, in particular to a display panel, a display device and a manufacturing method of the display panel.
Background
With the continuous development of display technologies, display screens such as "borderless" and "full screen" have become a research hotspot in the display field. The larger screen occupation ratio brings more excellent visual experience to users and can display more information, so that the pursuit of the larger screen occupation ratio becomes the mainstream development trend of display products.
In the prior art, in order to pursue a high screen occupation ratio, a frame is continuously compressed, a special-shaped screen is designed, the overall screen with a hole structure becomes the latest design trend, and devices such as a camera and a receiver can be placed at the hole position. The screen occupation ratio can be improved to the maximum extent by placing the camera at the opening in the display area of the display screen, but the hole digging technology requires that the glass cutting precision and the technological capability are very strict, so the mode faces the problems of low productivity, low yield, high cost and the like. Another solution is to keep the glass substrate and the layers (e.g., gate insulating layer and interlayer insulating layer) that are simultaneously formed corresponding to the display region, thereby reducing the transmittance of the display panel in the module installation region.
Disclosure of Invention
The invention provides a display panel, a display device and a manufacturing method of the display panel, aiming at improving the light transmittance of the display panel in a module setting area, reducing the process and improving the production efficiency.
In a first aspect, an embodiment of the present invention provides a display panel, where the display panel includes a display area and a non-display area, the display area surrounds the non-display area, the non-display area includes a module setting area, and a light transmittance of the display panel in the module setting area is greater than a preset value;
the display panel includes an array substrate, the array substrate including:
a first substrate;
a buffer layer on one side of the first substrate;
the thin film transistors are positioned on one side of the buffer layer, which is far away from the first substrate;
the film layers of the thin film transistors are only present in the non-display area except the module setting area and the display area; the buffer layer is arranged in the display area and the non-display area and covers the module setting area.
In a second aspect, an embodiment of the present invention provides a display device, including the display panel of the first aspect, and the display device further includes a photosensitive module, where the photosensitive module is disposed in the module setting area.
In a third aspect, an embodiment of the present invention provides a method for manufacturing a display panel, where the display panel includes a display area and a non-display area, the display area surrounds the non-display area, and the non-display area includes a module setting area; the display panel comprises an array substrate;
the manufacturing method comprises the following steps:
forming a buffer layer covering the display region and the non-display region on a first substrate of the array substrate;
forming a plurality of thin film transistors on the buffer layer of the display area, and removing a portion of each of the plurality of thin film transistors extending to the module setting area on the film layer to expose the buffer layer of the module setting area.
The embodiment of the invention provides a display panel, which comprises a display area and a non-display area, wherein the display area surrounds the non-display area, a module setting area for light passing is arranged in the non-display area, and for example, a camera can be arranged in the module setting area. The module setting area reserves the first substrate, namely, the first substrate is not cut off by adopting a hole digging mode, so that the problems of low yield and low yield caused by the hole digging technology are solved. The embodiment of the invention removes the part of the film layer where the thin film transistor is positioned in the module setting area, and reserves the buffer layer in the module setting area. The advantages of this arrangement are: on one hand, the film layer where the thin film transistor is located, such as the gate insulating layer and the interlayer insulating layer, is removed to improve the light transmittance of the module setting region. On the other hand, when the film layers (such as the gate insulating layer and the interlayer insulating layer) where the thin film transistors are located are etched by using the original process to form the through holes, the parts, extending to the module setting area, of the film layers in the thin film transistors are removed simultaneously in the same process flow, and a new process flow does not need to be added. If the buffer layer in the module setting area needs to be removed, no corresponding etching process exists in the display area, so that one more process is needed. On the other hand, the buffer layer can be used as a protective layer to cover the first substrate, so that water vapor and impurity particles are prevented from entering the display panel, and the reliability of the display panel is improved. The embodiment of the invention improves the light transmittance of the display panel in the module setting area, reduces the process procedures and improves the production efficiency.
Drawings
Fig. 1 is a schematic top view of a display panel according to an embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view along the direction AA' in FIG. 1;
fig. 3 is a schematic cross-sectional view of another array substrate according to an embodiment of the invention;
fig. 4 is a schematic cross-sectional structure view of another array substrate according to an embodiment of the invention;
fig. 5 is a schematic cross-sectional view illustrating another array substrate according to an embodiment of the invention;
fig. 6 is a schematic cross-sectional structure view of another array substrate according to an embodiment of the invention;
fig. 7 is a schematic cross-sectional view illustrating another display panel according to an embodiment of the invention;
FIG. 8 is a top view of a portion of another display panel according to an embodiment of the present invention;
FIG. 9 is a schematic cross-sectional view taken along the direction BB' in FIG. 8;
FIG. 10 is a top view of a portion of another display panel according to an embodiment of the present invention;
FIG. 11 is a schematic cross-sectional view taken along the direction CC' of FIG. 10;
fig. 12 is a schematic structural diagram of a pixel according to an embodiment of the present invention;
fig. 13 is a schematic cross-sectional view illustrating another display panel according to an embodiment of the invention;
fig. 14 is a schematic structural diagram of a display device according to an embodiment of the present invention;
Fig. 15 is a flowchart of a method for manufacturing a display panel according to an embodiment of the present invention;
FIG. 16 is a flowchart of another method for fabricating a display panel according to an embodiment of the present invention;
FIG. 17 is a flowchart of another method for fabricating a display panel according to an embodiment of the present invention;
fig. 18a to 18k are schematic views illustrating a manufacturing method of an array substrate in a display panel according to an embodiment of the invention;
FIG. 19 is a flowchart of another method for fabricating a display panel according to an embodiment of the present invention;
fig. 20a to 20c are schematic diagrams illustrating a manufacturing method of a color filter substrate in a display panel according to an embodiment of the invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Fig. 1 is a schematic top view of a display panel according to an embodiment of the present invention, and fig. 2 is a schematic cross-sectional view along the direction AA' in fig. 1. referring to fig. 1 and fig. 2, a display panel 100 includes a display area 110 and a non-display area 120, the display area 110 surrounds the non-display area 120, the non-display area 120 includes a module setting area 121, and a light transmittance of the display panel 100 in the module setting area 121 is greater than a predetermined value. The display area 110 may be used for displaying an image, and the display area 110 may include a plurality of pixels arranged in an array, each pixel may include a plurality of sub-pixels, each sub-pixel may include an opening area and a non-opening area, the opening area is a light-transmitting area, and the non-opening area is a non-light-transmitting area. The non-display area 120 is an area where no image display area is performed.
The display panel 100 includes an array substrate 200, and the array substrate 200 includes a first substrate 11, a buffer layer 12, and a plurality of thin film transistors 1. The buffer layer 12 is positioned at one side of the first substrate 11. The thin film transistors 1 are located on the buffer layer 12 side away from the first substrate 11. The thin film transistor 1 may include a semiconductor layer 103, a gate electrode 102, a source electrode 101, and a drain electrode 104, where the gate electrode 102 is located between the semiconductor layer 103 and the source and drain electrodes (short for the source electrode 101 and the drain electrode 104), and belongs to a thin film transistor with a top gate structure. In other embodiments, the thin film transistor 1 may also be a thin film transistor with a bottom-gate structure, in which the semiconductor layer 103 is located between the gate electrode 102 and the source/drain electrode. The film layers of the thin film transistors 1 are only present in the non-display area 120 except for the module setting area 121 and the display area 110. The buffer layer 12 is disposed in the display region 110 and the non-display region 120, and covers the module installation region 121. That is, the buffer layer 12 is disposed in the module disposing region 121, and the film layer where the thin film transistor 1 is disposed does not exist in the module disposing region 121. For example, referring to fig. 2, the thin film transistor 1 is located in a layer including a gate insulating layer 13 and an interlayer insulating layer 14, where the gate insulating layer 13 and the interlayer insulating layer 14 may be an organic insulating layer, an inorganic insulating layer, or a stacked structure of the organic insulating layer and the inorganic insulating layer, and this is not particularly limited in this embodiment of the invention, and is specifically determined in practical situations. The gate insulating layer 13 is located between the gate electrode 102 and the semiconductor layer 103, and the interlayer insulating layer 14 is located between the gate electrode 102 and the source-drain electrode. In the region other than the module setting region 121 in the non-display region 120 and in the display region 110, there are a buffer layer 12, a gate insulating layer 13, and an interlayer insulating layer 14; in the module setting region 121, the buffer layer 12 is present, and the gate insulating layer 13 and the interlayer insulating layer 14 are not present.
The embodiment of the invention provides a display panel, which comprises a display area and a non-display area, wherein the display area surrounds the non-display area, a module setting area for light passing is arranged in the non-display area, and for example, a camera can be arranged in the module setting area. The module setting area reserves the first substrate, namely, the first substrate is not cut off by adopting a hole digging mode, so that the problems of low yield and low yield caused by the hole digging technology are solved. The embodiment of the invention removes the part of the film layer where the thin film transistor is positioned in the module setting area, and reserves the buffer layer in the module setting area. The advantages of this arrangement are: on one hand, the film layer where the thin film transistor is located, such as the gate insulating layer and the interlayer insulating layer, is removed to improve the light transmittance of the module setting region. On the other hand, when the film layers (such as the gate insulating layer and the interlayer insulating layer) where the thin film transistors are located are etched by using the original process to form the through holes, the parts, extending to the module setting area, of the film layers in the thin film transistors are removed simultaneously in the same process flow, and a new process flow does not need to be added. If the buffer layer in the module setting area needs to be removed, no corresponding etching process exists in the display area, so that one more process is needed. On the other hand, the buffer layer can be used as a protective layer to cover the first substrate, so that water vapor and impurity particles are prevented from entering the display panel, and the reliability of the display panel is improved. The embodiment of the invention improves the light transmittance of the display panel in the module setting area, reduces the process procedures and improves the production efficiency.
Fig. 3 is a schematic cross-sectional structure view of another array substrate according to an embodiment of the present invention, and referring to fig. 3, the array substrate 200 further includes an array planarization layer 15 and a first passivation layer 16 sequentially stacked, where the array planarization layer 15 is located on a side of the plurality of thin film transistors 1 away from the first substrate 11. The array planarization layer 15 and the first passivation layer 16 exist only in the non-display region 120 except for the module setting region 121 and the display region 110. In the region of the non-display region 120 other than the module setting region 121 and in the display region 110, there are a buffer layer 12, a gate insulating layer 13, an interlayer insulating layer 14, an array planarization layer 15, and a first passivation layer 16; in the module setting region 121, the buffer layer 12 is present, and the gate insulating layer 13, the interlayer insulating layer 14, the array planarization layer 15, and the first passivation layer 16 are not present. The array planarization layer 15 may be made of an organic material, for example, and the array planarization layer 15 may have a larger thickness to planarize the surface undulations caused by the non-uniform pattern of the film layers below the array planarization layer 15, so as to planarize the planarized surface, thereby facilitating the formation of other film layers above the array planarization layer 15. In the embodiment of the invention, the buffer layer 12 is only arranged on one side of the first substrate 11 in the module setting region 121, so that the transmittance of the module setting region 121 is improved.
Exemplarily, referring to fig. 3, the array substrate may further include a pixel electrode 2 and a common electrode 3, and the pixel electrode 2 is electrically connected to the drain electrode 104 of the thin film transistor 1. The thin film transistor 1 is used to control a voltage value/a current value of the pixel electrode 2, thereby controlling an electric field formed between the pixel electrode 2 and the common electrode 3, and further controlling the display of the display panel. In the case that the display panel is a liquid crystal display panel, the liquid crystal display panel further includes liquid crystal molecules, and the liquid crystal molecules can rotate under the action of an electric field formed between the pixel electrode 2 and the common electrode 3 to control whether light emitted from the backlight is transmitted or not, so as to display an image. In the embodiment of the present invention, the first passivation layer 16 is an insulating layer between the pixel electrode 2 and the common electrode 3. Fig. 3 is only an example that the pixel electrode 2 is located on the common electrode 3 away from the first substrate 11, in other embodiments, the pixel electrode 2 may also be located on a side of the common electrode 3 close to the first substrate 11, which is not limited in this embodiment of the present invention.
Fig. 4 is a schematic cross-sectional structure view of another array substrate according to an embodiment of the present invention, and referring to fig. 4, the array substrate 200 further includes a second passivation layer 17 disposed on a side of the first passivation layer 16 away from the first substrate 11, and the second passivation layer 17 is only present in a region of the non-display region 120 except for the module disposing region 121 and the display region 110. In the region of the non-display region 120 other than the module setting region 121 and in the display region 110, there are a buffer layer 12, a gate insulating layer 13, an interlayer insulating layer 14, an array planarization layer 15, a first passivation layer 16, and a second passivation layer 17; in the module setting region 121, the buffer layer 12 is present, and the gate insulating layer 13, the interlayer insulating layer 14, the array planarization layer 15, the first passivation layer 16, and the second passivation layer 17 are not present. In the embodiment of the invention, the buffer layer 12 is only arranged on one side of the first substrate 11 in the module setting region 121, so that the transmittance of the module setting region 121 is improved.
Exemplarily, referring to fig. 4, the array substrate may further include a pixel electrode 2, a common electrode 3, and a touch wiring layer 4, and the pixel electrode 2 is electrically connected to the drain electrode 104 of the thin film transistor 1. The touch wiring layer 4 may be provided with touch wirings, the touch wirings are electrically connected to the common electrode 3 which is reused as a touch electrode, and the touch wirings can provide touch signals for the touch electrodes electrically connected thereto. In the embodiment of the present invention, the first passivation layer 16 is an insulating layer between the pixel electrode 2 and the touch routing layer 4, and the second passivation layer 17 is an insulating layer between the pixel electrode 2 and the common electrode 3.
Fig. 5 is a schematic cross-sectional structure view of another array substrate according to an embodiment of the present invention, which is different from fig. 3 in that an array planarization layer 15 and a first passivation layer 16 are further disposed in the module disposing region 121, and referring to fig. 5, the array substrate 200 further includes the array planarization layer 15 and the first passivation layer 16 sequentially stacked, and the array planarization layer 15 is located on a side of the plurality of thin film transistors 1 away from the first substrate 11. The array planarization layer 15 and the first passivation layer 16 exist in the display region 110 and the non-display region 120, and cover the module disposing region 121. In the region of the non-display region 120 other than the module setting region 121 and in the display region 110, there are a buffer layer 12, a gate insulating layer 13, an interlayer insulating layer 14, an array planarization layer 15, and a first passivation layer 16; in the module setting region 121, the buffer layer 12, the array planarization layer 15, and the first passivation layer 16 are present, and the gate insulating layer 13 and the interlayer insulating layer 14 are not present. Since the gate insulating layer 13 and the interlayer insulating layer 13 in the film layer in which the thin film transistor 1 is located are mostly made of materials such as silicon oxide and silicon nitride, and the light transmittance of these materials is not good, the film layer in which the thin film transistor 1 is located in the module setting region 121 is removed. The remaining array planarization layer 15 and the first passivation layer 16 may satisfy the requirements of the module, such as a camera, for light. When the display panel is pressed by the outside, since the array planarization layer 15 and the first passivation layer 16 can provide support for the first substrate 11, the box thickness change is small, the rainbow texture problem is avoided, and the display effect of the display panel is improved.
Fig. 6 is a schematic cross-sectional structure view of another array substrate according to an embodiment of the present invention, which is different from fig. 4 in that an array planarization layer 15, a first passivation layer 16 and a second passivation layer 17 are further disposed in the module disposing region 121, and referring to fig. 6, the array substrate 200 further includes the second passivation layer 17 disposed on a side of the first passivation layer 16 away from the first substrate 11, and the second passivation layer 17 is present in the display region 110 and the non-display region 120 and covers the module disposing region 121. In the non-display region 120 except for the module setting region 121 and in the display region 110, there are a buffer layer 12, a gate insulating layer 13, an interlayer insulating layer 14, an array planarization layer 15, a first passivation layer 16, and a second passivation layer 17; in the module setting region 121, the buffer layer 12, the array planarization layer 15, the first passivation layer 16, and the second passivation layer 17 are present, and the gate insulating layer 13 and the interlayer insulating layer 14 are not present. The remaining array planarization layer 15, the first passivation layer 16, and the second passivation layer 17 may satisfy the requirements of the module, such as a camera, for light. When the display panel is pressed by the outside, the array planarization layer 15, the first passivation layer 16 and the second passivation layer 17 can provide support for the first substrate 11, and compared with the support for the first substrate 11 by using the array planarization layer 15 and the first passivation layer 16, the support effect is better, the box thickness variation is smaller, the occurrence of the rainbow texture problem is avoided, and the display effect of the display panel is further improved.
It should be noted that the array substrate 200 provided in each embodiment of the present invention may be an array substrate in a liquid crystal display panel, an organic light emitting display panel, or an electrophoretic display panel, and other components in the display panel except for the array substrate 200 may be designed accordingly according to an inventive concept provided by the present invention (i.e., to improve the light transmittance of the module setting region and reduce the process).
Fig. 7 is a schematic cross-sectional structure view of another display panel according to an embodiment of the invention, and referring to fig. 7, the display panel 100 further includes a color filter substrate 300 opposite to the array substrate 200. The display panel 100 further includes a liquid crystal layer 400 located between the array substrate 200 and the color film substrate 300, and the liquid crystal layer 400 includes a plurality of liquid crystal molecules. The color filter substrate 300 includes a second substrate 21, a black matrix 22, a color resist layer 23, and a color filter planarization layer 24. The black matrix 22 is positioned on a side of the second substrate 21 adjacent to the first substrate 11. The color resist layer 23 is located on the side of the black matrix 22 away from the second substrate 21. The color film planarization layer 24 is located on the side of the color resist layer 23 away from the second substrate 21. The light cannot pass through the black matrix 22, and the light passing through the color resist layer 23 has a corresponding color (for example, if the color resist layer 23 includes a red color resist, the light passing through the red color resist in the color resist layer 23 appears red). The black matrix 22 and the color resist layer 23 exist only in the region other than the module setting region 121 in the non-display region 120 and in the display region 110. The color film planarization layer 24 is disposed in the display area 110 and the non-display area 120 and covers the module setting area 121. A black matrix 22, a color resist layer 23 and a color film planarization layer 24 are present in the non-display area 120 except for the module setting area 121 and in the display area 110; in the module setting region 121, the color filter planarization layer 24 is present, and the black matrix 22 and the color resist layer 23 are not present. Since the black matrix 22 is opaque, the color resist layer 23 has a strong wavelength selectivity to light incident thereon, and thus the black matrix 22 and the color resist layer 23 in the module setting region 121 are removed. The color film planarization layer 24 has a high transmittance, and the color film planarization layer 24 can meet the light transmittance requirement. If the color film planarization layer 24 in the module setting area 121 needs to be removed, there is no corresponding etching process in the display area 110, so that one more process is required. The embodiment of the invention improves the light transmittance of the display panel 100 in the module setting area 121, reduces the process procedures and improves the production efficiency.
Fig. 8 is a top view of a partial structure of another display panel according to an embodiment of the invention, fig. 9 is a schematic cross-sectional structure along the direction BB' in fig. 8, and referring to fig. 8 and 9, the non-display area 120 further includes a wiring area 122, and the wiring area 122 surrounds the module installation area 121. The wiring region 122 is provided with a frame sealing adhesive 500 surrounding the module setting region 121, and the frame sealing adhesive 500 is located between the array substrate 200 and the color film substrate 300. The frame sealing adhesive 500 provides support for the array substrate 200 and the color filter substrate 300 in the non-display area 120, so as to maintain the box thickness, and prevent the array substrate 200 and the color filter substrate 300 from being greatly deformed in the module setting area 121 when the display panel 100 is subjected to an external force, thereby affecting the optical performance of devices arranged in the module setting area 121. In the embodiment of the invention, the wiring area 122 is an area of the non-display area 120 except the module setting area 121.
Fig. 10 is a top view of a partial structure of another display panel according to an embodiment of the present invention, fig. 11 is a schematic cross-sectional structure view along a direction CC' in fig. 10, and referring to fig. 10 and fig. 11, the non-display area 120 further includes a supporting pillar disposing area 123 and a wiring area 122, the supporting pillar disposing area 123 surrounds the module disposing area 121, and the wiring area 122 surrounds the supporting pillar disposing area 123. In the support post setting area 123, a plurality of first main support posts 611 located between the array substrate 200 and the color filter substrate 300 are disposed. In the wiring region 122, the array substrate 300 includes a plurality of signal traces.
Fig. 12 is a schematic structural diagram of a pixel according to an embodiment of the present invention, and referring to fig. 10, fig. 11 and fig. 12, a pixel unit 30 may include three sub-pixels, which are a first sub-pixel 31, a second sub-pixel 32 and a third sub-pixel 33, respectively, where the first sub-pixel 31 may be a red sub-pixel, the second sub-pixel 32 may be a green sub-pixel, and the third sub-pixel 33 may be a blue sub-pixel. Any one of the sub-pixels is electrically connected to one of the first signal lines 41 and one of the second signal lines 42. It is understood that in other embodiments, one pixel unit 30 may further include 2 or 4 sub-pixels, which is not limited by the present invention. The first signal lines 41 are scan lines, and the second signal lines 42 are data lines. The plurality of signal traces on the wiring region 122 of the array substrate 300 may include, for example, the first signal lines 41 and/or the second signal lines 42.
Alternatively, referring to fig. 10 and 11, a plurality of second main support columns 612 are provided in the display area 110. The density of the first main support columns 611 in the support column setting area 123 is greater than that of the second main support columns 612 in the display area 110. Wherein the density of the support pillars refers to the number of support pillars provided in a unit area. In the embodiment of the present invention, the number of the second main supporting pillars 612 arranged in a unit area in the display area 110 is smaller than the number of the first main supporting pillars 611 arranged in a unit area in the supporting pillar arranging area 123. That is, in the display area 110, the second main supporting columns 612 are sparsely arranged; in the support post setting area 123, the first main support posts 611 are set densely. If the density of the first main support columns 611 in the support column setting area 123 is less than or equal to the density of the second main support columns 612 in the display area 110, the number of the first main support columns 611 arranged in the whole non-display area 120 is too small to better maintain the box thickness because the module setting area 121 and the wiring area 122 are not provided with the first main support columns 611. In the embodiment of the present invention, the density of the first main support pillars 611 in the support pillar setting area 123 is greater than the density of the second main support pillars 612 in the display area 110, so that the box thickness can be better maintained, and the array substrate 200 and the color filter substrate 300 are prevented from generating great deformation in the module setting area 121 when the display panel is subjected to an external force, which affects the optical performance of the device disposed in the module setting area 121. In the embodiment of the invention, the wiring area 122 and the supporting pillar setting area 123 are areas of the non-display area 120 except the module setting area 121.
Alternatively, referring to fig. 10 and 12, the display panel 100 includes a plurality of pixels 30 arranged in an array, each pixel 30 includes a plurality of sub-pixels, the pixel 30 is located in the display area 110, the area of the pixel 30 is S1, and the area of the module setting area 121 is S2. The area of the pixel 30 and the area of the module disposition region 121 both refer to the plan view area thereof, i.e., the orthographic projection area on the first substrate 11. In the support column setting area 123, the number N of the first main support columns 611 satisfies:
wherein A is the distribution density of the first main supporting column 611, and A is more than or equal to 0.03 and less than or equal to 0.06. When the number N of the first main supporting pillars 611 satisfies:
meanwhile, the density of the first main supporting columns 611 in the supporting column setting area 123 is greater than that of the second main supporting columns 612 in the display area 110, and the density of the first main supporting columns 611 is less than a set threshold, so that the density of the first main supporting columns 611 is moderate.
Alternatively, referring to fig. 10 and 11, the first main supporting pillars 611 and the second main supporting pillars 612 are formed in the same process using the same material, so that the process is saved.
Fig. 13 is a schematic cross-sectional view illustrating another display panel according to an embodiment of the present invention, and referring to fig. 13, a plurality of first auxiliary support columns 621 are further disposed in the support column disposition area 123, wherein the height of the first auxiliary support columns 621 is smaller than that of the first main support column 611. The display area 110 is further provided with a plurality of second auxiliary supporting columns 622, the height of the second auxiliary supporting columns 622 is smaller than that of the second main supporting columns 612, and the plurality of first auxiliary supporting columns 621 and the plurality of second auxiliary supporting columns 622 are formed by using the same material in the same process, so that the process is saved. The height of the support columns (which may include the first main support column 611, the second main support column 612, the first auxiliary support column 621, and the second auxiliary support column 622, for example) refers to the distance between the end of the support column close to the array substrate 200 and the end of the support column far away from the array substrate 200. The first auxiliary supporting column 621 and the second auxiliary supporting column 622 have smaller heights relative to the first main supporting column 611 and the second main supporting column 612, so that the display panel can be supported when being subjected to larger pressure, abnormal display phenomena caused by larger deformation of the display panel are prevented, and the normal operation of the display panel is ensured. Further, the first main supporting column 611 and the second main supporting column 612 have the same height, and the first auxiliary supporting column 621 and the second auxiliary supporting column 622 have the same height, so that the supporting force provided by the first main supporting column 611 for the display panel in the display area 110 is the same as the supporting force provided by the second main supporting column 612 for the display panel in the non-display area 120, and the supporting force provided by the first auxiliary supporting column 621 for the display panel in the display area 110 is the same as the supporting force provided by the second auxiliary supporting column 622 for the display panel in the non-display area 120, and the process is relatively simple.
Fig. 14 is a schematic structural view of a display device according to an embodiment of the present invention, and as shown in fig. 14, a display device 600 according to an embodiment of the present invention includes the display panel 100 according to any embodiment of the present invention, and the display device 600 further includes a photosensitive module 700, where the photosensitive module 700 is disposed in the module disposing area 121. The photosensitive module 700 can be, for example, a camera module, an infrared sensing module, or a fingerprint module. The display device 600 may be a mobile phone shown in fig. 14, or may be a computer, a television, an intelligent wearable device, and the like, which is not limited in this embodiment of the present invention.
Fig. 15 is a flowchart of a method for manufacturing a display panel according to an embodiment of the present invention, and fig. 18a to 18k are schematic diagrams of manufacturing an array substrate in a display panel according to an embodiment of the present invention, and referring to fig. 15 and fig. 18a to 18k, the display panel includes a display area 110 and a non-display area 120, the display area 110 surrounds the non-display area 120, and the non-display area 120 includes a module setting area 121. The display panel comprises an array substrate, and the manufacturing method of the display panel comprises the manufacturing method of the array substrate. The manufacturing method of the display panel comprises the following steps:
S110, a buffer layer 12 covering the display region 110 and the non-display region 120 is formed on the first substrate 11 of the array substrate (refer to fig. 18 a).
S120, forming a plurality of thin film transistors 1 on the buffer layer 12 of the display region 110, and removing a portion of each of the thin film transistors 1 extending to the module disposing region 121 on the film layer to expose the buffer layer 12 of the module disposing region 121.
The embodiment of the invention removes the part of the film layer where the thin film transistor is positioned in the module setting area, and reserves the buffer layer in the module setting area. The advantage of this arrangement is that: on one hand, the film layer where the thin film transistor is located, such as the gate insulating layer and the interlayer insulating layer, is removed to improve the light transmittance of the module setting region. On the other hand, when the film layers (such as the gate insulating layer and the interlayer insulating layer) where the thin film transistors are located are etched by using the original process to form the through holes, the parts, extending to the module setting area, of the film layers in the thin film transistors are removed simultaneously in the same process flow, and a new process flow does not need to be added. If the buffer layer in the module setting area needs to be removed, no corresponding etching process exists in the display area, so that one more process is needed. On the other hand, the buffer layer can be used as a protective layer to cover the first substrate, so that water vapor and impurity particles are prevented from entering the display panel, and the reliability of the display panel is improved. The embodiment of the invention improves the light transmittance of the display panel in the module setting area, reduces the process procedures and improves the production efficiency.
Fig. 16 is a flowchart of another manufacturing method of a display panel according to an embodiment of the present invention, and referring to fig. 16 and fig. 18a to 18k, step S120 may further include the following sub-steps:
s121, the semiconductor layer 103 is formed on the buffer layer 12 of the display region 110 (refer to fig. 18 b).
S122, the gate insulating layer 13 covering the display region 110 and the non-display region 120 is formed (refer to fig. 18 c).
S123, forming a gate electrode 102 on the gate insulating layer 13 of the display region 110 (refer to fig. 18 d).
And S124, forming the interlayer insulating layer 14 covering the display region 110 and the non-display region 120 (refer to fig. 18 e).
S125, the gate insulating layer 13 and the interlayer insulating layer 14 in the display region 110 are removed to form a via hole exposing the semiconductor layer 103, and the gate insulating layer 13 and the interlayer insulating layer 14 of the module setting region 121 are removed (refer to fig. 18 f).
S126, forming the source electrode 101 and the drain electrode 104 in the display region 110, and electrically connecting the source electrode 101 and the drain electrode 104 with the semiconductor layer 103 through the via hole (refer to fig. 18 g).
Fig. 17 is a flowchart of another manufacturing method of a display panel according to an embodiment of the present invention, referring to fig. 17 and fig. 18a to 18k, optionally, after step S120, the manufacturing method of the display panel may further include the following steps:
S130, forming an array planarization layer 15 covering the display region 110 and the non-display region 120 on the side of the plurality of thin film transistors 1 away from the first substrate 11 (refer to fig. 18 h).
S140, forming a first passivation layer 16 covering the display region 110 and the non-display region 120 on the side of the array planarization layer 15 away from the first substrate 11 (refer to fig. 18 i).
For an in-cell touch display panel (i.e., a display panel in which the touch panel function is embedded in a cell), the array substrate may further include a touch routing layer, the common electrode may be reused as a touch electrode, and a touch signal may be provided to a touch electrode electrically connected to the common electrode through a touch routing disposed in the touch electrode layer. The manufacturing method of the display panel can further comprise the following steps:
s150, forming a second passivation layer 17 covering the display region 110 and the non-display region 120 on the side of the first passivation layer 16 away from the first substrate 11 (refer to fig. 18 j).
S160, removing the array planarization layer 15, the first passivation layer 16 and the second passivation layer 17 in the display region 110 to form a via hole exposing the drain electrode 104 of the thin film transistor 1, and removing the array planarization layer 15, the first passivation layer 16 and the second passivation layer 17 in the module setting region 121 (refer to fig. 18 k).
Optionally, after step S130 and before step S140, the method for manufacturing a display panel may further include: the touch routing layer 4 is formed on the side of the array planarization layer 15 away from the first substrate 11.
Optionally, after step S140 and before step S150, the method for manufacturing a display panel may further include: the common electrode 3 is formed on the first passivation layer 16 on the side away from the first substrate 11.
Optionally, referring to fig. 6 at the same time, after step S160, the manufacturing method of the display panel may further include: a pixel electrode 2 is formed on the side of the second passivation layer 17 away from the first substrate 11, and the pixel electrode 2 is electrically connected to the drain electrode 104 of the thin film transistor 1.
Fig. 19 is a flowchart of another manufacturing method of a display panel according to an embodiment of the present invention, and fig. 20a to 20c are schematic diagrams of manufacturing a color filter substrate in the display panel according to the embodiment of the present invention, and referring to fig. 19 and fig. 20a to 20c, the display panel includes a color filter substrate opposite to an array substrate, and the manufacturing method of the display panel includes a manufacturing method of the color filter substrate. The manufacturing method of the display panel further comprises the following steps:
s210, sequentially forming a black matrix 22 and a color resist layer 23 on one side of the second substrate 21 of the color filter substrate, which cover the non-display area 120 except the module setting area 121 and the display area 110 (refer to fig. 20a and 20 b).
S220, a color film planarization layer 24 covering the display region 110 and the non-display region 120 is formed on the black matrix 22, the color resist layer 23 and the exposed second substrate 21 (see fig. 20 c).
It should be noted that in the manufacturing method of the display panel provided in each embodiment of the present invention, the film layer covering the display area 110 and the non-display area 120 also covers the module setting area 121 in the non-display area 120.
In the embodiment of the present invention, since the black matrix 22 is opaque, the color resist layer 23 has a strong wavelength selectivity to the light incident thereon, and thus the black matrix 22 and the color resist layer 23 in the module setting region 121 are removed. The color film planarization layer 24 has a high transmittance, and the color film planarization layer 24 can meet the light transmittance requirement. If the color film planarization layer 24 in the module setting area needs to be removed, there is no corresponding etching process in the display area 110, so that one more process is required. The embodiment of the invention improves the light transmittance of the display panel in the module setting area, reduces the process procedures and improves the production efficiency.
Optionally, the manufacturing method of the display panel may further include: an array alignment film covering the display region 110 and the non-display region 120 is formed on one side of the pixel electrode 2 away from the first substrate, and a color film alignment film covering the display region 110 and the non-display region 120 is formed on one side of the color film planarization layer 24 away from the second substrate 21, and the array alignment film and the color film alignment film are used for enabling liquid crystal molecules to be regularly arranged according to a preset direction. After the array substrate and the color film substrate are formed, the manufacturing method of the display panel may further include: and dropping liquid crystals, and performing box alignment on the array substrate and the color film substrate, which are not described herein again.
It is to be noted that the foregoing description is only exemplary of the invention and that the principles of the technology may be employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious modifications, rearrangements, combinations and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (13)
1. The display panel is characterized by comprising a display area and a non-display area, wherein the display area surrounds the non-display area, the non-display area comprises a module setting area, and the light transmittance of the display panel in the module setting area is larger than a preset value;
the display panel includes an array substrate, the array substrate including:
a first substrate;
a buffer layer on one side of the first substrate;
the thin film transistors are positioned on one side of the buffer layer, which is far away from the first substrate;
The film layers of the thin film transistors are only present in the non-display area except the module setting area and the display area; the buffer layer is arranged in the display area and the non-display area and covers the module setting area;
the array substrate further comprises an array planarization layer and a first passivation layer which are sequentially stacked, wherein the array planarization layer is positioned on one side, away from the first substrate, of the plurality of thin film transistors;
the array planarization layer and the first passivation layer are only present in the non-display region except for the module setting region and the display region.
2. The display panel according to claim 1, wherein the array substrate further comprises a second passivation layer on a side of the first passivation layer away from the first substrate, the second passivation layer being present only in the non-display region except for the module disposing region and in the display region.
3. The display panel according to claim 1, further comprising a color film substrate opposed to the array substrate; the color film substrate comprises:
A second substrate;
the black matrix is positioned on one side of the second substrate, which is close to the first substrate;
the color resistance layer is positioned on one side of the black matrix, which is far away from the second substrate;
the color film planarization layer is positioned on one side, far away from the second substrate, of the color resistance layer;
the black matrix and the color resistance layer are only present in the non-display area except the module setting area and the display area; the color film planarization layer is arranged in the display area and the non-display area and covers the module setting area.
4. The display panel according to claim 3, wherein the non-display region further includes a wiring region; the wiring area surrounds the module setting area;
the wiring area is provided with frame sealing glue surrounding the module arrangement area, and the frame sealing glue is located between the array substrate and the color film substrate.
5. The display panel according to claim 3, wherein the non-display region further includes a support post setting region and a wiring region;
the support column arrangement area surrounds the module arrangement area; the wiring area surrounds the support column arrangement area; a plurality of first main supporting columns located between the array substrate and the color film substrate are arranged in the supporting column arrangement area; in the wiring area, the array substrate comprises a plurality of signal wirings.
6. The display panel according to claim 5, wherein a plurality of second main support pillars are disposed in the display area;
the density of the first main supporting columns in the supporting column setting area is greater than that of the second main supporting columns in the display area.
7. The display panel of claim 5, wherein the display panel comprises a plurality of pixels arranged in an array, each of the pixels comprises a plurality of sub-pixels, the pixels are located in the display region, the area of the pixels is S1, and the area of the module setting region is S2;
in the support column setting area, the number N of the first main support columns satisfies:
wherein A is the distribution density of the first main supporting column, and A is more than or equal to 0.03 and less than or equal to 0.06.
8. The display panel of claim 6, wherein the first main support pillars and the second main support pillars are formed of the same material in the same process.
9. The display panel according to claim 6, wherein a plurality of first auxiliary support columns are further disposed in the support column disposition region, and the height of the first auxiliary support columns is smaller than that of the first main support columns; the display area is further provided with a plurality of second auxiliary supporting columns, the height of each second auxiliary supporting column is smaller than that of the corresponding second main supporting column, and the plurality of first auxiliary supporting columns and the plurality of second auxiliary supporting columns are formed by the same material in the same process.
10. A display device, comprising the display panel of any one of claims 1 to 9, further comprising a photosensitive module, wherein the photosensitive module is disposed in the module disposing area.
11. The manufacturing method of the display panel is characterized in that the display panel comprises a display area and a non-display area, the display area surrounds the non-display area, and the non-display area comprises a module setting area; the display panel comprises an array substrate;
the manufacturing method comprises the following steps:
forming a buffer layer covering the display region and the non-display region on a first substrate of the array substrate;
forming a plurality of thin film transistors on the buffer layer of the display area, and removing a portion of each of the plurality of thin film transistors extending to the module arrangement area on the film layer to expose the buffer layer of the module arrangement area;
forming an array planarization layer covering the display area and the non-display area on one side of the thin film transistors, which is far away from the first substrate;
forming a first passivation layer covering the display area and the non-display area on one side of the array planarization layer away from the first substrate;
Removing the array planarization layer and the first passivation layer in the display region to form a through hole exposing the drain electrode of the thin film transistor, and removing the array planarization layer and the first passivation layer in the module setting region.
12. The method of claim 11, wherein forming a plurality of thin film transistors on the buffer layer of the display region and removing a portion of each of the plurality of thin film transistors in a film layer extending to the module disposing region to expose the buffer layer of the module disposing region comprises:
forming a semiconductor layer on the buffer layer of the display region;
forming a gate insulating layer covering the display region and the non-display region;
forming a gate electrode on the gate insulating layer of the display region;
forming an interlayer insulating layer covering the display region and the non-display region;
removing the gate insulating layer and the interlayer insulating layer in the display region to form a through hole exposing the semiconductor layer, and removing the gate insulating layer and the interlayer insulating layer in the module setting region;
and forming a source electrode and a drain electrode in the display area, wherein the source electrode and the drain electrode are electrically connected with the semiconductor layer through the through hole.
13. The method according to claim 11, wherein the display panel further comprises a color film substrate opposite to the array substrate; the manufacturing method further comprises the following steps:
sequentially forming a black matrix and a color resistance layer which cover the area except the module setting area in the non-display area and the display area on one side of a second substrate of the color film substrate;
and forming a color film planarization layer covering the display area and the non-display area on the black matrix, the color resistance layer and the exposed second substrate.
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| CN202010968604.0A CN112133708B (en) | 2018-09-30 | 2018-09-30 | Display panel, display device and manufacturing method of display panel |
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| CN201811162738.2A CN109378316B (en) | 2018-09-30 | 2018-09-30 | Display panel, display device and manufacturing method of display panel |
| CN202010968604.0A CN112133708B (en) | 2018-09-30 | 2018-09-30 | Display panel, display device and manufacturing method of display panel |
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| CN110767710B (en) * | 2019-02-28 | 2022-04-15 | 云谷（固安）科技有限公司 | Display substrate, display panel and display device |
| CN110109279B (en) * | 2019-04-22 | 2021-04-02 | 武汉华星光电技术有限公司 | Array substrate |
| EP3931877A1 (en) * | 2019-04-23 | 2022-01-05 | Apple Inc. | Methods and configurations for improving the performance of sensors under a display |
| CN110211972B (en) * | 2019-05-23 | 2021-02-02 | 武汉华星光电半导体显示技术有限公司 | Array substrate and display device |
| CN110571253A (en) | 2019-08-29 | 2019-12-13 | 武汉华星光电半导体显示技术有限公司 | display panel and mask plate |
| CN110808267B (en) * | 2019-11-07 | 2022-10-04 | 昆山国显光电有限公司 | Display substrate, display panel and display device |
| CN110873985A (en) * | 2019-11-29 | 2020-03-10 | 维沃移动通信有限公司 | Display module and electronic equipment |
| CN110967857B (en) * | 2019-12-16 | 2022-05-31 | 武汉华星光电技术有限公司 | Liquid crystal display panel |
| CN113013177B (en) * | 2019-12-20 | 2024-05-07 | 京东方科技集团股份有限公司 | Display panel, manufacturing method thereof and display device |
| US11768551B2 (en) | 2020-01-20 | 2023-09-26 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Array substrate and display device |
| CN111209896B (en) * | 2020-02-14 | 2022-11-22 | 厦门天马微电子有限公司 | Array substrate, display panel and display device |
| CN111240121B (en) * | 2020-02-21 | 2024-05-28 | 京东方科技集团股份有限公司 | Transparent control device and display screen |
| CN111583818B (en) * | 2020-05-07 | 2021-07-06 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
| CN111650787B (en) * | 2020-06-11 | 2023-06-30 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method thereof and display device |
| CN111933675B (en) * | 2020-08-18 | 2023-07-11 | 维沃移动通信有限公司 | Display module, electronic equipment and preparation method of display module |
| CN113421891A (en) * | 2021-07-15 | 2021-09-21 | 合肥维信诺科技有限公司 | Array substrate and OLED display panel |
| CN115327809A (en) * | 2022-09-15 | 2022-11-11 | 厦门天马微电子有限公司 | Display panel and display device |
| CN117192848A (en) * | 2023-07-26 | 2023-12-08 | 重庆惠科金渝光电科技有限公司 | Display panel |
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| CN109378316A (en) | 2019-02-22 |
| CN112133708A (en) | 2020-12-25 |
| CN109378316B (en) | 2020-10-20 |
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