JP2007248903A - Liquid crystal display device and method for manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase density of COG technology in a liquid crystal display device which is driven by an in-plane switching mode and on which other electronic components are mounted by the COG(chip on glass) technology. <P>SOLUTION: A display panel 14 of the liquid crystal display device has a display part 16 and a connection terminal part 18 to which a horizontal driver LSI 30 is connected. In a transparent panel substrate 40 below the display part 16, a buffer layer 102, a TFT formation layer 110, a pixel electrode layer 160, an intermediate insulation layer 170 and a common electrode layer 180 having a slit 189, etc. are sequentially laminated on a lower glass substrate 100. At the connection terminal part 18, connection wirings 140, 141, 142 are arranged and an intermediate conductor layer is arranged on them. In the intermediate conductor layer, first conductor layers 162, 164 formed by the same process as that of the pixel electrode layer 160 and a second conductor layer 181 formed by the same process as that of the common electrode layer 180 are alternately arranged between the adjacent connection wiring. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a liquid crystal display device and a method for manufacturing the liquid crystal display device, and in particular, liquid crystal is driven by an electric field generated between a common electrode and a pixel electrode in a display unit in which liquid crystal is sandwiched between a pair of substrates facing each other. The present invention relates to a liquid crystal display device in which another electronic component is connected around the display unit, and a method for manufacturing the liquid crystal display device.

  In general, a liquid crystal display device that constitutes a display device such as a television or a graphic display is mainly of an active matrix type and driven by a vertical electric field. That is, this type of liquid crystal display device includes a pair of transparent glass substrates and a liquid crystal sealed between the glass substrates, and at least one of the glass substrates includes a thin film transistor and a pixel. An electrode is formed, and a color filter and a common electrode are formed on the other glass substrate. The liquid crystal is an electric field generated between the pixel electrode on the glass substrate on one side and the common electrode on the glass substrate on the other side by the drive circuit, that is, the in-plane direction of the glass substrate is defined as the lateral direction. It is driven by a vertical electric field perpendicular thereto.

  Liquid crystal display devices are required to have higher definition, smaller size, and wider viewing angle. In response to these demands, the present invention relates to a fusion of two technical fields. One is a lateral electric field driving method with respect to a wide viewing angle, and the other is a COG (Chip On Glass) technology for miniaturization.

  First, the lateral electric field driving method will be described. In recent years, as one means for achieving a wide viewing angle, an in-plane electric field, that is, a transverse electric field is generated with respect to a glass substrate, and the liquid crystal molecules are rotated in a plane parallel to the substrate by the transverse electric field. A technique for providing an optical switching function for changing the transmittance has been put into practical use.

  For example, Patent Document 1 describes an IPS mode (In Plane Switching Mode) liquid crystal display element that uses a parallel field parallel to the surface of a glass substrate, and Patent Document 2 further improves the IPS technology. A liquid crystal display device that improves the aperture ratio using FFS (Fringe-Field Switching) technology is described. Here, in the FFS technique, a pixel electrode is disposed on a common electrode through an intermediate insulating layer, a slit is provided in the pixel electrode, and the slit is used to reduce an electric field between the pixel electrode and the common electrode. Is generated. This electric field has a strong electric field component in the direction perpendicular to the substrate in the vicinity of the edge of the electrode as well as the lateral electric field, so that the liquid crystal molecules located above the electrode can also be driven. Therefore, if a transparent electrode is used, the electrode portion can also contribute to the display and the aperture ratio is improved. Note that the pixel electrode and the common electrode may be reversely arranged.

  Next, COG technology will be described. In an active matrix type liquid crystal display device, a data signal as a video signal is received from the outside and supplied to each pixel. For this purpose, a horizontal gate line and a vertical data line are provided on the plane of the liquid crystal display panel, and a corresponding pixel is selected by the corresponding gate line while supplying a video signal of the data line to each pixel. Control the supply of data signals. Therefore, it is necessary to control the supply of the data signal to the data line and the selection of the gate line. For this purpose, a horizontal driver and a vertical driver are provided. These drivers can be built in the liquid crystal display panel. Generally, however, the horizontal driver needs to control the operation of supplying the data signal to the data line of each column within one horizontal scanning period. In many cases, an integrated circuit different from the liquid crystal display panel is used. Here, the COG technique is used as a technique for mounting the horizontal driver on the glass substrate of the liquid crystal display panel.

  The COG technique is a technique for connecting a connection wiring arranged on a glass substrate and a connection terminal of an electronic component. For example, an anisotropic conductive film (ACF) can be connected by placing and pressing between a connection wiring and a connection terminal. In this case, a contact hole is formed in the insulating film for protecting the connection wiring, a transparent conductive film is formed including the contact hole, and this transparent conductive film is used as an intermediate conductor layer. The connection is made with an ACF-connecting terminal structure. This transparent conductive film is the same as ITO (Indium Tin Oxide) used for the pixel electrode and the common electrode. For example, Patent Document 3 describes the use of a transparent conductive film for the terminal portion.

Japanese Patent Laid-Open No. 10-62767 JP 2002-296611 A JP-A-6-180460

  As described above, the use of the horizontal electric field method is useful because a wide viewing angle can be realized in a liquid crystal display device. In the process of realizing such a horizontal electric field type liquid crystal display device, it has been found that a new structure utilizing its characteristics is possible.

  For example, in the COG technology, the minimum dimension is determined so that the distance between adjacent terminal portions is not short-circuited when the same conductor layer is disposed. Therefore, in the prior art, the minimum dimension between the terminal portions of the COG is determined by the interval between adjacent connection wiring patterns in the terminal portion or the interval between adjacent transparent conductive film patterns. By the way, in the horizontal electric field method, a pixel electrode layer and a common electrode layer are disposed via an intermediate insulating film, and both of these are transparent conductive film layers. Therefore, the degree of freedom of use of the transparent conductive film layer is increased as compared with the prior art, and this is expected to increase the density of COG technology packaging.

  An object of the present invention is to provide a liquid crystal display device and a liquid crystal display device that can increase the degree of freedom in using a transparent conductive film layer in a liquid crystal display device that is driven by a lateral electric field method and is mounted with other electronic components by COG technology. It is to provide a manufacturing method. Another object of the present invention is to provide a liquid crystal display device that is driven by a transverse electric field method and that mounts other electronic components using the COG technology, and that enables high-density mounting of the COG technology, and a method of manufacturing the liquid crystal display device Is to provide. Another object of the present invention is to provide a liquid crystal display device that can be miniaturized and a method for manufacturing the liquid crystal display device in a liquid crystal display device that is driven by a lateral electric field method and that is mounted with other electronic components using COG technology. That is. The following means contribute to at least one of the above objects.

  In the liquid crystal display device according to the present invention, a liquid crystal is sealed between a lower substrate and an upper substrate, a pixel electrode layer and a common electrode layer are disposed on the lower substrate with an intermediate insulating layer interposed therebetween, and the pixel electrode layer A liquid crystal display having a display unit for driving and displaying the liquid crystal with an electric field between the common electrode layer and a plurality of terminal units arranged in order to connect another electronic component around the display unit Each of the terminal units is connected to the display unit and is formed of a conductor, a wiring protective film layer covering the connection wiring, and the terminal unit provided in the terminal unit. An opening portion of a wiring protective film layer; and an intermediate conductor layer covering the connection wiring in the opening portion, wherein at least one of the terminal portions is formed in the same step as the pixel electrode layer in the intermediate conductor layer. Using the formed first conductor layer, at least other terminal portions One is characterized by using a second conductive layer formed in the same step as the common electrode layer.

  In the liquid crystal display device according to the present invention, it is preferable that the first conductor layer and the second conductor layer are alternately used between the adjacent terminal portions.

  In the liquid crystal display device according to the present invention, the first conductor layer of the terminal portion and the second conductor layer of the terminal portion are insulating layers formed in the same process as the intermediate insulating layer. It is preferable that they are separated.

  In the liquid crystal display device according to the present invention, between the adjacent terminal portions, the minimum distance in the planar arrangement of the first conductor layer and the second conductor layer is the same conductor arranged in a plane. It is preferably shorter than the minimum spacing sometimes used.

  In the liquid crystal display device according to the present invention, it is preferable that the pixel electrode layer and the common electrode layer are ITO layers.

  Further, in the method for manufacturing a liquid crystal display device according to the present invention, a liquid crystal is sealed between a lower substrate and an upper substrate, and a pixel electrode layer and a common electrode layer are disposed on the lower substrate with an insulating layer interposed therebetween, A liquid crystal having a display unit for driving the liquid crystal by an electric field between the pixel electrode layer and the common electrode layer, and a plurality of terminal units arranged in order to connect another electronic component around the display unit A method for manufacturing a display device, comprising: a first conductor layer disposed on a connection wiring connected to the display unit in a part of terminal portions of the plurality of terminal units; and the display unit A first conductor forming step for forming the pixel electrode layer in the same step, and a first conductor layer stacked on a connection wiring connected to the display portion in another terminal portion of the plurality of terminal portions. A second conductor layer and the common electrode layer of the display section are formed in the same step; Characterized in that it comprises a and a collector formation process.

  In addition, the liquid crystal display device according to the present invention includes an insulating layer forming step of forming the insulating layer separating the first conductive layer and the second conductive layer and the intermediate insulating layer in the same step. It is preferable.

  With the above structure, at least one of the terminal portions of the liquid crystal display device uses the first conductor layer formed in the same process as the pixel electrode layer as the intermediate conductor layer, and at least one of the other terminal portions is a common electrode. A second conductor layer formed in the same process as the layer is used. Therefore, when the pixel electrode layer and the display electrode layer are transparent conductive film layers, the degree of freedom in selecting the transparent conductive film layer in the terminal portion is increased.

  In addition, the first conductor layer and the second conductor layer are alternately used between the adjacent terminal portions. Since the first conductor layer and the second conductor layer are formed in different steps, an insulating film can be disposed between them, and can be separated in three dimensions, so that between the intermediate conductor layers in the terminal portion There is no limitation on the minimum planar dimension. Therefore, the density can be increased in the COG technology, and the liquid crystal display device can be downsized.

  Further, the first conductor layer of the terminal portion and the second conductor layer of the terminal portion are separated by an insulating layer formed in the same process as the intermediate insulating layer, so that the process is simple. In addition, the three-dimensional separation between the intermediate conductor layers in the terminal portion eliminates the limitation on the minimum planar dimension between the intermediate conductor layers in the terminal portion. Therefore, the density can be increased in the COG technology, and the liquid crystal display device can be downsized.

  In addition, between adjacent terminal portions, the minimum distance in the planar arrangement of the first conductor layer and the second conductor layer is shorter than the minimum distance used when the same conductor is arranged in a plane. Therefore, the density can be increased in the COG technology, and the liquid crystal display device can be downsized.

  The pixel electrode layer and the common electrode layer are ITO layers. As the transparent conductive film layer, there is an IZO layer (Indium Zinc Oxide) in addition to the ITO layer, but it is recognized that the ITO layer is superior in mountability due to the difference in material. Therefore, better implementation can be performed.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, the liquid crystal display device will be described as an active matrix type using TFT (Thin Film Transistor) and using FFS technology, but the liquid crystal is driven by a driving electric field generated by the first electrode and the second electrode. Any liquid crystal display device having an insulating layer in the path of the driving electric field can be generally implemented by modifying the following embodiments. For example, a switching element other than a TFT, such as a diode element, may be used as the switching element. Moreover, the dimension etc. which are demonstrated below are an example, Comprising: The dimension other than that may be sufficient.

  As is well known, an active matrix type liquid crystal display panel has a plurality of gate lines and a plurality of data lines arranged vertically and horizontally on one substrate of two transparent panel substrates sandwiching liquid crystal. Each pixel is arranged in each of the grids divided by the lines. The gate terminal of the TFT element of each pixel is connected to one of the gate lines, the drain terminal is connected to one of the data lines, and the source terminal is connected to a pixel electrode provided in each pixel. This structure is the same in the FFS system, but a common line is further arranged to supply a common potential to each pixel.

  FIG. 1 is a schematic configuration diagram of an FFS mode liquid crystal display device 10. The liquid crystal display device 10 includes a display control unit 12, a display panel 14, and the like. The display control unit 12 is a circuit having a function of performing control for causing the display panel 14 to perform desired display. The display panel 14 includes a display unit 16 that is sealed by sandwiching liquid crystal between a pair of transparent panel substrates, and peripheral elements. As peripheral elements of the display unit 16, there are a connection terminal unit 18 on which a horizontal driver LSI 30 is mounted, a vertical driver circuit 20, and the like.

  The display unit 16 is selected by the vertical driver circuit 20 and is supplied with data signals by a plurality of gate lines 22 arranged in the horizontal direction in FIG. 1 and a horizontal driver LSI 30 and is arranged in the vertical direction in FIG. The data line 24 is configured to include a plurality of pixels 23 that are specified by each gate line and each data line and arranged in a matrix form to which a data signal is supplied.

  Each gate line 22 is connected to the vertical driver circuit 20, and each data line 24 is connected to the horizontal driver LSI 30 via the connection terminal portion 18. The display control unit 12 is connected to the horizontal driver LSI 30 and the vertical driver circuit 20, and supplies a common potential to the display panel 14 through the common line 26.

  In such a structure, a specific gate line 22 and a specific data line 24 are selected, an on signal of the TFT is applied to the gate line 22, and an image data signal is applied to the data line 24. And the TFT of the pixel 23 at the intersection of the data line 24 is turned on, the drain terminal to which the data line 24 is connected and the source terminal connected to the pixel electrode become conductive, and the pixel electrode is an image signal. A data signal is provided. Since the common line 26 is arranged so as to cover all the pixels and is connected to the common electrode layer having the slit, the horizontal electric field generated between the common electrode layer and each pixel electrode by using the slit, The liquid crystal is driven.

  FIG. 2 is a schematic cross-sectional view of the display panel 14 showing the display unit 16 and the connection terminal unit 18. Here, a cross-sectional view corresponding to one pixel is shown on the display unit 16, and connection terminals 140 of the horizontal driver LSI 30 and connection lines 140 and 141 of each data line on the display panel 14 side are connected to the connection terminal unit 18. , 142 are shown in cross-section.

  As shown in FIG. 2, in the display unit 16 of the lower transparent panel substrate 40, a buffer layer 102, a TFT formation layer 110, a pixel electrode layer 160, an intermediate insulating layer 170, a slit are formed on the lower glass substrate 100. A common electrode layer 180 having 189, an alignment film 190, and the like are sequentially stacked. On the upper transparent panel substrate 50, a color filter 54, an alignment film 56, and the like are laminated on an upper glass substrate 52. Then, the lower transparent panel substrate 40 and the upper transparent panel substrate 50 are laminated via the seal member 62. The liquid crystal 60 is disposed between the facing alignment films 190 and 56 in a space sealed by the seal member 62. This stacking form is an example, and other stacking elements may be included, and the stacking order may be changed according to the method or application of the liquid crystal display.

  As shown in FIG. 2, the lower transparent panel substrate 40 is larger than the upper transparent panel substrate 50, and the connection terminal portion 18 is disposed on the protruding portion. The connection terminal portion 18 is disposed by being stacked on the connection wirings 140, 141, 142, etc., which are formed by extending the plurality of data lines of the display unit 16, and the connection wirings 140, 141, 142, etc. An intermediate conductor layer and an ACF 34 are included. FIG. 2 shows a state in which a first conductor layer 162, a second conductor layer 181 and a first conductor layer 164 are stacked on three adjacent connection wirings 140, 141 and 142, respectively. As will be described later, the first conductor layers 162 and 164 are formed in the same process as the pixel electrode layer 160, and the second conductor layer 181 is formed in the same process as the common electrode layer 180. In this manner, each terminal 32 of the horizontal driver LSI 30 and each data line are connected by the COG technique according to the structure of the connection terminal of each terminal 32 -ACF 34 -intermediate conductor layer-each data line of the horizontal driver LSI 30 and the horizontal driver LSI 30 A data signal that is an image signal is supplied from the driver LSI 30 to each data line.

  FIG. 3 is a detailed cross-sectional view of the display unit 16 and the connection terminal unit 18 with respect to the lower transparent panel substrate 40. Here, typically, a cross-sectional view of one pixel and a detailed cross-sectional view of two adjacent terminal portions are shown. Steps such as laminated insulating films are omitted, and the surface of each insulating film is shown as being flat.

In the lower transparent panel substrate 40 in FIG. 3, the lower glass substrate 100 is a glass plate having components suitable for a liquid crystal panel, temperature characteristics, and the like. The buffer layer 102 between the lower glass substrate 100 and the TFT formation layer 110 forms the TFT formation layer 110 including the semiconductor layer 112 on the lower glass substrate 100 with good adhesion, and prevents diffusion of impurities. Provided. As the buffer layer 102, a composite insulating film in which an oxide film (SiO ₂ ) and a nitride film (SiN _x ) are stacked can be used.

  The TFT formation layer 110 formed on the buffer layer 102 includes a semiconductor layer 112 and a gate insulating film layer 114 for forming a TFT element for each pixel. As the semiconductor layer 112, an amorphous silicon film is formed by a plasma CVD technique or the like, and is crystallized by a laser technique or the like to form a so-called low-temperature polysilicon, and is patterned into an appropriate shape to form a polysilicon island. Using a mask, a source / drain of a TFT doped with an appropriate impurity can be used. As the semiconductor layer 112, a high-temperature polysilicon layer or an amorphous silicon layer may be used in addition to the low-temperature polysilicon layer.

  The gate insulating film layer 114 is an insulating film formed on the semiconductor layer 112, and in particular in the TFT element, is also an element constituting a MIS structure of a gate electrode-gate insulating film-carrier region. Since the gate insulating film layer 114 is formed over the entire surface of the lower glass substrate 100, it is also formed on the buffer layer 102 of the connection terminal portion 18. As the gate insulating film layer 114, an oxide film, a nitride film, a composite insulating film combining them, or the like by a CVD method or the like can be used.

  The molybdenum (Mo) layer on the gate insulating film layer 114 is etched into a predetermined pattern and formed as the gate line 22, the common line 26, and the lower connection wirings 126 and 127 in the connection terminal portion 18. The gate line 22 functions as a gate electrode on the semiconductor layer 112. Such a molybdenum layer can be formed by sputtering.

  The interlayer insulating layer 128 is an insulating film having a function of insulating between the molybdenum layer and the next wiring layer. As the interlayer insulating layer 128, an oxide film, a nitride film, or a composite insulating film that combines them can be used by a plasma CVD method. The interlayer insulating layer 128 is also formed over the entire surface of the lower glass substrate 100.

  Contact holes are opened in the interlayer insulating layer 128. That is, contact holes are opened at locations corresponding to the source and drain of the TFT element, locations corresponding to the common line, and locations corresponding to the lower connection wirings 126 and 127 in the connection terminal portion 18. In FIG. 3, only the contact hole 129 at the location corresponding to the drain of the TFT element is provided with a reference numeral.

  The wiring layer formed thereafter is a conductor layer for forming the source terminal 130, the data line 24, the common terminal 134, and the upper connection wirings 136 and 137 in the connection terminal portion 18 on the interlayer insulating layer 128. This wiring layer is formed through a contact hole opened in the interlayer insulating layer 128, a location corresponding to the source and drain of the TFT element, a location corresponding to the common line, and a location corresponding to the lower connection wiring 126 and 127 in the connection terminal portion 18. Connected to each. Thereafter, it is formed in a predetermined pattern, and is separated into the source terminal 130, the data line 24, the common terminal 134, and the upper connection wirings 136 and 137 in the connection terminal portion 18 as described above. Here, the drain is connected to the data line 24. However, since the drain and the source are compatible in the TFT element, the one connected to the data line 24 may be called the source.

  However, since the upper connection wirings 136 and 137 are extensions of the corresponding data lines 24, the data lines 24 become the upper connection wirings 136 and 137 at the extended ends as long as the upper connection wirings 136 and 137 are extended. In the connection terminal portion 18, the lower connection wirings 126 and 127 and the upper connection wirings 136 and 137 are laminated to form connection wirings 140 and 141 having a two-layer structure.

  As the wiring layer, a molybdenum (Mo) / aluminum-neodymium (Al—Nd) / molybdenum (Mo) layer stacked by a sputtering method can be used. In addition to this, a titanium (Ti) / aluminum (Al) / titanium (Ti) layer may be used, and a single layer, or a two-layer or four-layer conductor film of a material constituting these laminated films may be used. It may be used.

The protective film layer 150 formed on the wiring layer is an insulating film for protecting the upper connection wiring 136 and 137 in the source terminal 130, the data line 24, the common terminal 134, and the connection terminal portion 18. As a function. In particular, since the next planarization film 152 is removed from the connection terminal portion 18, the protective film layer 150 becomes a wiring protective layer that covers the connection wirings 140 and 141. Therefore, the protective film layer 150 is opened before the first conductor layer 162 is formed on the connection wiring 140 and the second conductor layer 181 is formed on the connection wiring 141 in a later step. . As the protective film layer 150, a nitride film (SiN _x ) or the like can be used.

  The planarization film 152 is an insulating film formed on the protective film layer 150 in order to planarize the surface that has been uneven in the previous steps. As the planarization film 152, an organic film formed by a spin coating method, for example, an acrylic resin film can be used. Since the planarization film 152 is an organic film, it is softer and has a lower heat resistant temperature than inorganic films such as oxide films, nitride films, and composite insulating films thereof. In the planarizing film 152, a contact hole 153 is opened at a position corresponding to the source terminal 130. Further, the planarizing film 152 is removed from the connection terminal portion 18.

  The ITO layer formed on the planarization film 152 functions as a pixel electrode layer 160 in each pixel in the display unit 16 by appropriate patterning, and in the connection terminal unit 18 in advance on the connection wiring 140. It functions as the first conductor layer 162 laminated so as to cover the opened opening. Since the pixel electrode layer 160 covers the contact hole opened in the planarization film 152 and is connected to the source terminal, the pixel electrode layer 160 is connected to the data line 24 when the TFT element is turned on. A data signal, which is an image signal, is connected to the drain. The ITO layer is provided with an opening at a location corresponding to the common terminal 134. This opening is for preventing short circuit with the pixel electrode layer 160 when connecting the common electrode layer 180 formed on the intermediate insulating layer 170 and the common terminal, as will be described later. As the ITO layer, a film formed by sputtering can be used.

  The ITO layer formed on the planarizing film 152 is formed on every other connection wiring in the connection terminal portion 18 between the adjacent terminal portions, and becomes the first conductor layer. That is, the plurality of arranged terminal portions are divided into two groups every other adjacent terminal portion, and each of the plurality of terminal portions belonging to the first group has an upper surface of the planarizing film 152. A first conductor layer is formed by using the ITO layer formed in the above, and becomes an intermediate conductor layer between the connection wiring and the ACF. On the other hand, each of the plurality of terminal portions belonging to the second group is formed with a second conductor layer using an ITO layer formed on an intermediate insulating layer 170 described later, and the connection wiring and the ACF are connected to each other. It becomes an intermediate conductor layer in between. Accordingly, the first conductor layer and the second conductor layer are alternately formed between the adjacent terminal portions in the plurality of arranged terminal portions. For example, in FIG. 2, the first conductor layer 162, the second conductor layer 181 and the first conductor layer 164 are formed in the order of the connection wirings 140, 141 and 142 arranged in alignment.

  The intermediate insulating layer 170 is an insulating film provided between the common electrode layer 180 and the pixel electrode layer 160 formed in the next step. A contact hole 171 is opened in the intermediate insulating layer 170 at a location corresponding to the common terminal 134. Further, in the connection terminal portion 18, a corresponding portion is opened on the connection wiring 141 where the first conductor layer 162 is not laminated. As the intermediate insulating layer 170, an oxide film, a nitride film formed by a low temperature CVD method, or a composite insulating film combining them can be used.

  The ITO layer formed on the intermediate insulating layer 170 functions as a common electrode layer 180 having a slit 189 in the display unit 16 by appropriate patterning. In the connection terminal unit 18, the ITO layer is formed on the connection wiring 141. It functions as a second conductor layer 181 that is laminated to cover the opening that has been opened in advance. Since the common electrode layer 180 covers a contact hole or the like opened in the intermediate insulating layer 170 and is connected to a common terminal, the common potential from the common line 26 is supplied to the common electrode layer 180. As the ITO layer, a film formed by sputtering can be used.

  The ITO layer formed on the intermediate insulating layer 170 is formed on every other connection wiring in the connection terminal portion 18 between the adjacent terminal portions, and becomes the second conductor layer. As described above, the plurality of arranged terminal portions are divided into two groups every other one, but each of the plurality of terminal portions belonging to the second group has the intermediate insulating layer 170. A second conductor layer is formed using the ITO layer formed thereon, and becomes an intermediate conductor layer between the connection wiring and the ACF. In this way, the first conductor layer and the second conductor layer are alternately formed between the adjacent terminal portions in the plurality of terminal portions arranged in alignment.

  In the connection terminal portion 18, the first conductor layer 162 and the second conductor layer 181 are three-dimensionally separated via the intermediate insulating layer 170, and therefore when the same conductor layer is patterned. It is not necessary to apply the design rule for the minimum dimension of the distance between adjacent conductor layers. For example, in FIG. 3, one end a of the first conductor layer 162 and the other end b of the second conductor layer 181 are in the same position in the plane, that is, the plane interval is zero. Even in this case, the first conductor layer 162 and the second conductor layer 181 are sufficiently electrically separated by the intermediate insulating layer 170. In some cases, the one end a of the first conductor layer 162 and the other end b of the second conductor layer 181 may overlap in a planar arrangement. In this way, since the first conductor layer 162 and the second conductor layer 181 can be arranged close to each other in the adjacent terminal portion, the distance between the adjacent connection wiring 140 and the connection wiring 141 can be reduced. It becomes possible to perform high-density arrangement in the COG technology.

  The alignment film 190 is an insulating film formed on the common electrode layer 180 and subjected to a predetermined alignment by rubbing or the like. In the connection terminal portion 18, the alignment film 190 is removed, and portions of the first conductor layer 162 and the second conductor layer 181 are opened for connection.

  In this way, when the lower transparent panel substrate 40 is formed, the liquid crystal 60 is sealed between the alignment-processed upper transparent panel substrate 50 and the display panel 14 is completed. In the display unit 16, as described above, the common electrode layer 180 provided with the slit 189 is formed under the intermediate insulating layer 170 as described above. By using the slit 189, display control is performed. The liquid crystal 60 can be driven by the FFS technique by generating an electric field between the pixel electrode layer 160 and the common electrode layer 180 by the unit 12. Note that the vertical relationship between the pixel electrode layer and the common electrode layer arranged via the intermediate insulating layer 170 may be reversed.

  FIG. 4 is a partial plan view of the display unit 16 of the lower transparent panel substrate 40, and shows a portion corresponding to about one pixel. FIG. 5 is an enlarged view of the pixel electrode layer 160 and the common electrode layer 180. In the following description, the symbols described in FIGS. 1 to 3 are used. Further, in the plan view, since the pixel electrode layer 160 and the common electrode layer 180 overlap with each other, in order to show these regions, only the region of the pixel electrode layer 160 is hatched in FIG. 4, and only the common electrode layer 180 is shown in FIG. Is hatched in a direction different from that in FIG. As shown in FIG. 4, the gate lines 22 are arranged in the horizontal direction on the paper surface, and the data lines 24 are arranged in the vertical direction on the paper surface. Further, the common lines 26 are arranged in the horizontal direction on the paper surface. The gate line 22 is disposed so as to cross the semiconductor layer 112 forming the TFT element, and an overlapping portion thereof becomes a channel region. The drain is connected to the data line 24 through the contact hole 129 on both sides of the channel region, and the source is It is connected to the pixel electrode layer 160 through the contact hole 153. The common electrode layer 180 is disposed on the entire surface and is connected to the common line 26 through the contact hole 171. The common electrode layer 180 is provided with a plurality of slits 189, that is, openings, in portions corresponding to the pixel electrode layer 160.

  FIG. 6 is a flowchart showing a procedure for manufacturing the lower transparent panel substrate 40. Here, the description will be made with reference to the cross-sectional views of FIGS. 7 to 10, focusing on which portion of the display portion 16 and which portion of the connection terminal portion 18 are formed in the same process. In the following, the same elements as those described in FIGS. 1 to 3 are denoted by the same reference numerals, and detailed description thereof is omitted.

  First, a lower glass substrate 100 suitable for a liquid crystal panel is prepared, and a buffer layer 102 is formed thereon (S10). The buffer layer 102 is formed over the entire surface of the lower glass substrate 100. Then, the semiconductor layer 112 is formed thereon (S12). The semiconductor layer 112 is formed on the display unit 16 and is not formed on the connection terminal unit 18. As described with reference to FIG. 2, since the vertical driver circuit 20 is formed on the lower glass substrate 100, the semiconductor layer 112 is also formed there. Thereafter, a gate insulating film layer 114 is formed (S14). The gate insulating film layer 114 is also formed over the entire surface of the lower glass substrate 100.

  Next, a molybdenum (Mo) layer is formed over the gate insulating film layer 114. The molybdenum layer is also formed over the entire surface of the lower glass substrate 100, but is then etched into a predetermined pattern to form the gate line 22, the common line 26, and the lower connection wirings 126 and 127 in the connection terminal portion 18. (S16).

  This is shown in FIG. Here, a state in which the gate line 22 and the common line 26 are formed in the display unit 16 and the lower connection wirings 126 and 127 are formed in the connection terminal unit 18 is shown. As described above, the portion where the gate line 22 crosses the semiconductor layer 112 functions as the gate electrode of the TFT element. When the liquid crystal display device 10 is completed, the common line 26 is connected to the common potential output terminal of the display control unit 12 by an appropriate connection method after the extension.

  Next, an interlayer insulating layer 128 is formed (S18). The interlayer insulating layer 128 is also formed over the entire surface of the lower glass substrate 100. Then, contact holes are opened at locations corresponding to the source and drain of the TFT element, locations corresponding to the common line, and locations corresponding to the lower connection wirings 126 and 127 in the connection terminal portion 18 (S20). Thereafter, a wiring layer is formed. Specifically, the molybdenum (Mo) / aluminum-neodymium (Al—Nd) / molybdenum (Mo) layer as the wiring layer material covers the contact hole over the entire surface of the lower glass substrate 100 as described above. A film is formed. Then, by etching into a predetermined pattern, the source terminal 130, the data line 24, the common terminal 134, and the upper connection wirings 136 and 137 in the connection terminal portion 18 are formed on the interlayer insulating layer 128 (S22).

  This is shown in FIG. Here, the source terminal 130, the data line 24, and the common terminal 134 are formed in the display portion 16 so as to cover the contact hole opened in the interlayer insulating layer 128, and the upper connection wirings 136 and 137 are formed in the connection terminal portion 18. The state of being done is shown. In FIG. 8, only the contact hole 129 for the data line 24 is provided with a reference numeral. The upper connection wirings 136 and 137 correspond to the end portions of the data lines 24 in the display unit 16 that are extended to the connection terminal unit 18, respectively. In FIG. 8, the data lines 24 and the upper connection wirings 136 and 137 seem to be separated from each other, but actually, each data line 24 is connected to the upper connection wirings 136 and 137 and the like.

  Next, the protective film layer 150 is formed (S24). The protective film layer 150 is also formed over the entire surface of the lower glass substrate 100. Thereafter, a planarizing film 152 is formed (S26). The planarization film 152 is also formed over the entire surface of the lower glass substrate 100. Then, contact holes are formed in these films (S28). In the display unit 16, a contact hole 153 is opened at a location corresponding to the source terminal 130. Further, in the connection terminal portion 18, the planarization film 152 is entirely removed, and thereafter, a portion corresponding to the connection wiring 140 in the protective film layer 150 is opened.

  Then, an ITO layer is formed over the entire surface of the lower glass substrate 100. Then, it is etched into a predetermined pattern. Thereby, in the display unit 16, the pixel electrode layer 160 is formed on the planarization film 152 while covering the contact hole 153 opened in the planarization film 152 and the protective film layer 150. Further, in the connection terminal portion 18, the first conductor layer 162 is formed on the connection wiring 140 covering the opening formed in the protective film layer 150 and partially covering the protective film layer 150 (S 30). The ITO layer is provided with an opening at a position corresponding to the common terminal 134 in the pixel electrode layer 160 of the display unit 16. This is shown in FIG.

  Then, the intermediate insulating layer 170 is formed over the entire surface of the lower glass substrate 100 (S32). Thereafter, a contact hole 171 is opened at a position corresponding to the common terminal 134 in the display unit 16. Further, in the connection terminal portion 18, a corresponding portion is opened on the connection wiring 141 where the first conductor layer 162 is not laminated (S34).

  Next, an ITO layer is formed over the entire surface of the lower glass substrate 100. Then, it is etched into a predetermined pattern. Accordingly, in the display unit 16, the common electrode layer 180 having the slit 189 is formed on the intermediate insulating layer 170 while covering the contact hole 171 opened in the intermediate insulating layer 170, the planarization film 152, and the protective film layer 150. It is formed. Further, in the connection terminal portion 18, the second conductor layer 181 is formed on the connection wiring 141 so as to cover the openings opened in the intermediate insulating layer 170 and the protective film layer 150 and partially on the intermediate insulating layer 170. (S36). Thereafter, the intermediate insulating layer 170 is opened corresponding to the first conductor layer 162. This is shown in FIG. Thereafter, an alignment film 190 is formed on the display portion 16 (S38), and a predetermined alignment process is performed by rubbing or the like, so that the lower transparent panel substrate 40 is obtained.

  In connection with the operation of the liquid crystal display device 10 having the above-described configuration, the state of driving the horizontal electric field of the display unit 16 will be described with reference to FIG.

  When the display is to be performed due to the difference in transmittance of the liquid crystal 60, the display control unit 12 selects the gate line 22 and the data line 24 for a desired pixel, and turns on the TFT element that is a switching element of the pixel. . Accordingly, a predetermined drive signal is applied between the common electrode layer 180 and the pixel electrode layer 160 of the pixel.

  This is shown in the FFS technique schematic diagram of FIG. In FIG. 11, the alignment film is not shown. Here, a case where a negative potential is applied to the pixel electrode layer 160 and a positive potential is applied to the common electrode layer 180 is shown. The electric field 198 generated between the pixel electrode layer 160 and the common electrode layer 180 has a horizontal electric field component parallel to the surface of the glass substrate and the edge of the common electrode layer 180, that is, the slit 189 that is an electrode opening. The edge has a strong electric field component also in a direction perpendicular to the glass substrate surface. As a result, the liquid crystal molecules 61 are not only located between the common electrode layers 180 but also those located above the common electrode layer 180 are rotationally driven in the plane of the glass substrate by the electric field 198, Partial liquid crystal molecules 61 can also contribute to the display.

  As described above, a horizontal electric field can be generated by the pixel electrode layer 160 which is two transparent conductor layers arranged with the intermediate insulating layer 170 interposed therebetween and the common electrode layer 180 having the slit 189, thereby the liquid crystal The molecules can be driven to widen the viewing angle of the liquid crystal display device 10.

  FIG. 12 illustrates that in the connection terminal portion 18, adjacent connection wirings can be narrowed by using these two types of transparent conductor layers arranged with the intermediate insulating layer 170 interposed therebetween as intermediate conductor layers. It is a schematic diagram to do. Here, the two types indicate that the three-dimensional arrangement is different. FIG. 12A shows the state of adjacent terminal portions when only one type of intermediate conductor layer is used. Here, a case where the second conductor layer is used as an intermediate conductor layer is shown. Of course, the first conductor layer may be used. FIG. 12B shows a state in which the first conductor layer and the second conductor layer are alternately used between adjacent terminal portions.

  In FIG. 12A, the second conductor layers 182 and 181 are disposed on the adjacent connection wirings 140 and 141, respectively. Both the second conductor layers 182 and 181 are simultaneously formed in the same process as the formation of the common electrode layer. Therefore, since the same conductor is patterned in the same process, it is necessary to prevent adjacent conductor patterns from being short-circuited to each other. Therefore, as shown in FIG. 12A, it is necessary to provide a sufficient distance s between the one end portion a of the second conductor layer 182 and the other end portion b of the second conductor layer 181. There is. The size of the interval s is determined by the patterning process capability and the like, for example, about several μm to 10 μm may be required.

  In FIG. 12B, different types of intermediate conductor layers are arranged on the adjacent connection wirings 140 and 141, respectively. That is, when the first conductor layer 162 is used on the connection wiring 140, the second conductor layer 181 is disposed on the connection wiring 141 adjacent thereto. Although not shown in FIG. 12A, when there is a connection wiring next to the connection wiring 141, the first conductor layer is used on the connection wiring. As described above, the first conductor layer 162 is formed in the same process as that for forming the pixel electrode layer 160, whereas the second conductor layer 181 is formed in the intermediate insulating layer 170 after the pixel electrode formation process. After the formation process, the common electrode layer is formed at the same time. Therefore, the first conductor layer 162 and the second conductor layer 181 are made of the same ITO, but are three-dimensionally separated through the intermediate insulating layer 170. Therefore, as shown in FIG. 12B, the planar interval between the one end a of the first conductor layer 162 and the other end b of the second conductor layer 181 is zero. Even if it exists, it is electrically insulated and separated and there is no fear of short circuit. Further, even if the one end portion a of the first conductor layer 162 may overlap the other end portion b of the second conductor layer 181 in the planar arrangement, the first conductor layer 162 is electrically insulated and separated sufficiently. There is no risk of short circuit.

  Thus, by effectively using the two types of transparent conductor layers that are three-dimensionally separated via the intermediate insulating layer 170, the planar spacing between the adjacent connection wirings 140 and 141 is further narrowed. be able to. That is, it is possible to reduce the pitch of the connection wiring in a planar arrangement, and it is possible to realize high density in the COG technology.

1 is a schematic configuration diagram of an FFS mode liquid crystal display device according to an embodiment of the present invention. In embodiment which concerns on this invention, it is a schematic sectional drawing of the display panel which shows a display part and a connection terminal part. In embodiment which concerns on this invention, it is a detailed sectional view of a display part and a connection terminal part about a lower transparent panel substrate. In embodiment which concerns on this invention, it is a partial top view of the display part of a lower transparent panel board | substrate. FIG. 5 is a partially enlarged view of FIG. 4. In embodiment concerning this invention, it is a flowchart which shows the procedure when manufacturing a lower transparent panel board | substrate. In embodiment which concerns on this invention, it is a figure which shows the mode of the middle process which manufactures a lower transparent panel board | substrate. In embodiment which concerns on this invention, it is a figure which shows the mode of the middle process which manufactures a lower transparent panel board | substrate. In embodiment which concerns on this invention, it is a figure which shows the mode of the middle process which manufactures a lower transparent panel board | substrate. In embodiment which concerns on this invention, it is a figure which shows the mode of the middle process which manufactures a lower transparent panel board | substrate. It is a FFS technique schematic diagram. In embodiment which concerns on this invention, it is a schematic diagram which shows a mode that the density increase of a COG technique is achieved.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 Liquid crystal display device, 12 Display control part, 14 Display panel, 16 Display part, 18 Connection terminal part, 19 Terminal part, 20 Vertical driver circuit, 22 Gate line, 23 Pixel, 24 Data line, 26 Common line, 30 Horizontal driver LSI, 32 terminals, 34 ACF, 40 Lower transparent panel substrate, 50 Upper transparent panel substrate, 52 Upper glass substrate, 54 Color filter, 56, 190 Alignment film, 60 Liquid crystal, 61 Liquid crystal molecule, 62 Seal member, 100 Lower glass substrate, 102 buffer layer, 110 TFT forming layer, 112 semiconductor layer, 114 gate insulating film layer, 126, 127 lower connection wiring, 128 interlayer insulating layer, 129, 153, 171 contact hole, 130 source terminal, 134 common terminal 136, 137 Upper connection wiring, 14 , 141, 142 connection wiring, 150 protective film layer, 152 planarization film, 160 pixel electrode layer, 162, 164 first conductor layer, 170 intermediate insulating layer, 180 common electrode layer, 182, 181 second conductor layer, 189 slit, 198 electric field.

Claims (7)

A liquid crystal is sealed between the lower substrate and the upper substrate, and a pixel electrode layer and a common electrode layer are disposed on the lower substrate with an intermediate insulating layer interposed therebetween, and between the pixel electrode layer and the common electrode layer A liquid crystal display device having a display unit that drives and displays the liquid crystal with an electric field, and a plurality of terminal units that are arranged to connect another electronic component around the display unit,
Each of the terminal portions is
A connection wiring connected to the display unit and formed of a conductor;
A wiring protective film layer covering the connection wiring;
An opening of the wiring protective film layer provided in the terminal portion;
An intermediate conductor layer covering the connection wiring in the opening;
Including
In the intermediate conductor layer, at least one of the terminal parts uses a first conductor layer formed in the same process as the pixel electrode layer, and at least one of the other terminal parts is the same process as the common electrode layer. A liquid crystal display device using the second conductor layer formed in (1). The liquid crystal display device according to claim 1.
A liquid crystal display device, wherein the first conductor layer and the second conductor layer are alternately used between the adjacent terminal portions. The liquid crystal display device according to claim 2,
The liquid crystal display characterized in that the first conductor layer of the terminal portion and the second conductor layer of the terminal portion are separated by an insulating layer formed in the same process as the intermediate insulating layer. apparatus. The liquid crystal display device according to claim 3.
Between the adjacent terminal portions, the minimum interval in the planar arrangement of the first conductor layer and the second conductor layer is shorter than the minimum interval used when arranging the same conductor in a plane. A characteristic liquid crystal display device. The liquid crystal display device according to claim 1.
The liquid crystal display device, wherein the pixel electrode layer and the common electrode layer are ITO layers. A liquid crystal is sealed between the lower substrate and the upper substrate, a pixel electrode layer and a common electrode layer are disposed on the lower substrate with an insulating layer interposed therebetween, and an electric field between the pixel electrode layer and the common electrode layer A method for manufacturing a liquid crystal display device, comprising: a display unit for driving the liquid crystal; and a plurality of terminal units arranged in order to connect another electronic component around the display unit,
A first conductor layer disposed in a stacked manner on a connection wiring connected to the display portion in a part of the plurality of terminal portions and the pixel electrode layer of the display portion are formed in the same process. A first conductor forming step,
The second conductor layer disposed on the connection wiring connected to the display unit in the other part of the plurality of terminal units and the common electrode layer of the display unit in the same step A second conductor forming step formed by:
A method of manufacturing a liquid crystal display device comprising: The liquid crystal display device according to claim 7.
A method of manufacturing a liquid crystal display device, comprising: an insulating layer forming step of forming the insulating layer separating the first conductive layer and the second conductive layer and the intermediate insulating layer in the same step. .

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