KR102499636B1 - Semiconductor device comprising retset retention flip-flop - Google Patents

Abstract

A semiconductor device is provided. The semiconductor device includes a master latch that stores an input data signal using a local power supply voltage and a clock signal and outputs the data signal as a first output signal, and a global power supply voltage different from the local power supply voltage, a clock signal, and a retention signal. A slave latch that stores one output signal and outputs it as a second output signal, receives one signal and another one of a retention signal, a clock signal, and a reset signal, and performs a first logic operation to generate a second output signal. A first logic gate outputting 1 control signal, and a second control signal generated by receiving the first control signal, the other one of a retention signal, a clock signal, and a reset signal, and performing a second logic operation into a master latch and a second logic gate provided to at least one of the slave latch and the slave latch.

Description

Semiconductor device comprising retset retention flip-flop

The present invention relates to a semiconductor device including a retention reset flip-flop.

For low-power semiconductor chip design, a power gating technology that reduces leakage current is widely used. In order to use this power gating technique, the data in the flip-flop must be moved to another place when the power is cut off. method is being used.

To implement a reset function in such a retention flip-flop, a separate circuit or logic is required, and such a separate circuit or logic may increase the size of the retention flip-flop and increase power consumption. Therefore, there is a need for research on low-power, small retention flip-flops.

A technical problem to be solved by the present invention is to provide a semiconductor device capable of miniaturizing a product size and reducing power consumption.

The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

In order to achieve the above technical problem, a semiconductor device according to some embodiments of the present disclosure includes a master latch storing an input data signal using a local power supply voltage and a clock signal and outputting the data signal as a first output signal; a local power supply voltage; A slave latch that stores the first output signal using another global power supply voltage, clock signal, and retention signal and outputs the first output signal as a second output signal; A first logic gate that receives a signal and outputs a first control signal generated by performing a first logic operation, receives the other one of a retention signal, a clock signal, and a reset signal, and the first control signal; and a second logic gate providing a second control signal generated by performing two logic operations to at least one of the master latch and the slave latch.

In some embodiments, the slave latch performs a reset operation to fix the second output signal to a predetermined signal level when the reset signal is activated, and adjusts the signal level of the data signal when the reset signal is deactivated. Based on this, it is possible to determine the signal level of the second output signal.

In some embodiments, the first logical operation and the second logical operation may be different from each other.

In some embodiments, the first logical operation may include an OR operation, and the second logical operation may include a NAND operation.

In some embodiments, the first logic gate may receive the reset signal and the clock signal, perform an OR operation, and provide the resultant first control signal to the second logic gate.

In some embodiments, the second logic gate receives the retention signal and the first control signal, performs a NAND operation, and transmits the second control signal generated as a result to at least one of the master latch and the slave latch. It can include NAND gates providing one.

In some embodiments, the global power supply voltage may be provided to the first logic gate and the second logic gate.

In some embodiments, the method may further include a third logic gate receiving the reset signal and the second output signal and performing a third logic operation different from the first and second logic operations.

In some embodiments, the third logical operation may include a NOR operation.

In some embodiments, while the retention signal is activated and the slave latch performs a retention operation, when the reset signal is activated, the slave latch may perform a reset operation.

In order to achieve the above object, a semiconductor device according to some embodiments of the present disclosure may include a first line to which a global power supply voltage is applied, a second line separated from the first line and to which a local power supply voltage is applied, and the second line connected to a first operating circuit that uses the local power supply voltage, a first power gating circuit that determines whether or not to apply the local power supply voltage to the first operating circuit, and connected to the first line and the second line; A first retention reset flip-flop, wherein the first retention reset flip-flop is connected to the second line and stores a data signal input using a clock signal, a retention signal, and a reset signal. and a master latch for outputting it as a first output signal, connected to the first line, storing the first output signal using the clock signal, retention signal, and reset signal and outputting it as a second output signal A slave latch and a logic gate receiving the retention signal, the clock signal, and the reset signal and providing a control signal generated by performing a logic operation to at least one of the master latch and the slave latch.

In some embodiments, the logic gate may be connected to the first line.

In some embodiments, the logic gates include a first logic gate to perform a first logic operation and a second logic connected to an output of the first logic gate and to perform a second logic operation different from the first logic operation. Can contain gates.

In some embodiments, the first logic gate includes an OR gate for performing an OR operation on the reset signal and the clock signal, and the second logic gate NAND gate for performing a NAND operation on an output of the OR gate and the retention signal. can include

In some embodiments, the slave latch may include an inverter controlled by the control signal to invert the first output signal.

In some embodiments, a third line separated from the second line and to which the local power voltage is applied, a second operating circuit connected to the third line and using the local power voltage, and the local power supply voltage to the second operating circuit. The device may further include a second power gating circuit that determines whether a power supply voltage is applied, and a second retention reset flip-flop connected to the first line and the third line.

In order to achieve the above technical problem, a semiconductor device according to some embodiments of the present disclosure includes a master latch that stores a data signal input using a local power supply voltage and outputs the data signal as a first output signal, and a global power supply voltage different from the local power supply voltage. A slave latch that stores the first output signal using a power supply voltage and outputs it as a second output signal, receives first to third signals and provides the global power supply voltage to at least one of the master latch and the slave latch A logic gate comprising: a first transistor gated with the first signal to provide the global power supply voltage to a first node; and a first transistor gated with the first signal to provide a ground voltage to the first node. a second transistor gated with the second and third signals to provide the global power supply voltage to the first node; and a third transistor gated with the second and third signals to provide the first node with the ground. and a fourth transistor providing voltage.

In some embodiments, the third transistor includes a fifth transistor and a sixth transistor connected in series between the global power supply voltage and the first node, and the fifth transistor is gated with the second signal. , the sixth transistor may be gated with the third signal.

In some embodiments, the fourth transistor includes a fifth transistor and a sixth transistor connected in parallel between the ground voltage and the first node, the fifth transistor being gated with the second signal, The sixth transistor may be gated with the third signal.

In some embodiments, when the first signal is activated, the slave latch performs a retention operation, and when the second signal is activated, the slave latch performs a reset operation, and the first and second signals are If not activated, the slave latch may output a second output signal based on the third signal.

In order to achieve the above technical problem, a semiconductor device according to some embodiments of the present disclosure includes a master latch configured to store an input data signal using a local power supply voltage and a clock signal and output the data signal as a first output signal; and the local power supply voltage A slave latch storing the first output signal and outputting it as a second output signal using a global power supply voltage different from , the clock signal, and the retention signal, and inputting the retention signal, the clock signal, and the reset signal A first logic gate that receives and performs a first logic operation and provides a first control signal generated by performing a first logic operation to at least one of the master latch and the slave latch; and a second logic gate that receives the second output signal and the reset signal and performs a second logic operation. It may include a second logic gate that performs.

In some embodiments, the second logic operation may include a NOR operation, and the second logic gate may include a NOR gate.

In some embodiments, the first logical operation and the second logical operation may be different from each other.

In some embodiments, the first logic gate may include a third logic gate performing a third logic operation on the clock signal and the reset signal, and a fourth logic gate performing a fourth logic operation on an output of the third logic gate and the retention signal. It can contain 4 logic gates.

In some embodiments, the third logical operation and the fourth logical operation may be different from each other.

In some embodiments, the second logic gate may include a NOR gate, the third logic gate may include an OR gate, and the fourth logic gate may include a NAND gate.

In some embodiments, the master latch may include a third logic gate that receives the input data signal and the reset signal and performs a third logic operation.

In some embodiments, the second logical operation and the third logical operation may be identical to each other.

Details of other embodiments are included in the detailed description and drawings.

1 is a conceptual block diagram of a semiconductor device according to some embodiments of the inventive concept.
FIG. 2 is a block diagram of the retention reset flip-flop of FIG. 1;
3 is a block diagram of the logic gate of FIG. 2;
4 is a circuit diagram of a retention reset flip-flop in accordance with some embodiments of the present invention.
5 and 6 are circuit diagrams of the inverter of FIG. 4 .
7 to 10 are circuit diagrams of the logic gates of FIG. 4 .
11 to 13 are views for explaining the operation of a retention reset flip-flop according to some embodiments of the present invention.
14 is a circuit diagram of a retention reset flip-flop in accordance with some embodiments of the invention.

Advantages and features of the present invention, and methods of achieving them, will become clear with reference to the detailed description of the following embodiments taken in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only these embodiments make the disclosure of the present invention complete, and common knowledge in the art to which the present invention belongs. It is provided to fully inform the holder of the scope of the invention, and the present invention is only defined by the scope of the claims. The sizes and relative sizes of components shown in the drawings may be exaggerated for clarity of explanation. Like reference numbers designate like elements throughout the specification, and “and/or” includes each and every combination of one or more of the recited items.

An element is said to be "connected to" or "coupled to" another element when it is directly connected or coupled to another element or intervening with another element. include all cases. On the other hand, when one element is referred to as “directly connected to” or “directly coupled to” another element, it indicates that another element is not intervened.

Terminology used herein is for describing the embodiments and is not intended to limit the present invention. In this specification, singular forms also include plural forms unless specifically stated otherwise in a phrase. As used herein, "comprises" and/or "comprising" does not exclude the presence or addition of one or more other elements other than the recited elements.

Although first, second, etc. are used to describe various elements or components, these elements or components are not limited by these terms, of course. These terms are only used to distinguish one element or component from another. Accordingly, it goes without saying that the first element or component mentioned below may also be the second element or component within the technical spirit of the present invention.

Unless otherwise defined, all terms (including technical and scientific terms) used in this specification may be used in a meaning commonly understood by those of ordinary skill in the art to which the present invention belongs. In addition, terms defined in commonly used dictionaries are not interpreted ideally or excessively unless explicitly specifically defined.

1 is a conceptual block diagram of a semiconductor device according to some embodiments of the inventive concept.

Referring to FIG. 1 , the semiconductor device may include a retention reset flip-flop 1 , an operating circuit 98 and a power gating circuit 99 .

The power gating circuit 99 may be connected to the global power supply voltage line 91 and the ground line 93 . The power gating circuit 99 may determine whether to apply the local power supply voltage VDDL to the operating circuit 98 .

Specifically, the power gating circuit 99 determines on/off of the local power supply voltage line 92 using the global power supply voltage VDDG, thereby providing the local power supply voltage to the operating circuit 98. (VDDL) can be determined.

When the power gating circuit 99 applies the local power supply voltage VDDL to the operating circuit 98, the operating circuit 98 is driven using the local power supply voltage VDDL, and the power gating circuit 99 operates as a local power supply. If the voltage VDDL is not applied to the operating circuit 98, the operating circuit 98 may not be driven.

In this embodiment, the operating circuit 98 connected to the local power supply voltage line 92 and the ground line 93 may include all circuits driven using the local power supply voltage VDDL. In some embodiments, these operating circuits 98 may be used to perform operations based on data signals.

The retention reset flip-flop 1 may be connected to a global power supply voltage line 91 , a local power supply voltage line 92 , and a ground line 93 . The retention reset flip-flop 1 may serve to preserve data when the power gating circuit 99 cuts off the local power supply voltage VDDL.

Specifically, the retention reset flip-flop 1 operates as a normal reset flip-flop while the power gating circuit 99 applies the local power supply voltage VDDL, and then the power gating circuit 99 operates as a local power supply voltage. When (VDDL) is blocked, it can play a role of preserving stored data using the global power supply voltage (VDDG).

According to the present embodiment, the retention reset flip-flop 1 uses the local power supply voltage VDDL and the global power supply voltage VDDG while the power gating circuit 99 applies the local power supply voltage VDDL. , operates as a normal reset flip-flop, and while the power gating circuit 99 blocks the local power supply voltage VDDL, the retention operation may be performed using the global power supply voltage VDDG. In some embodiments, the data stored by the retention reset flip-flop 1 while the power gating circuit 99 blocks the local supply voltage (VDDL) If is applied again, it may be data necessary for the operation of the operating circuit 98.

The local power supply voltage line 92 and the global power supply voltage line 91 may be disposed separately as shown. The local power supply voltage VDDL may be provided to the local power supply voltage line 92 , and the global power supply voltage VDDG may be provided to the global power supply voltage line 91 .

The global power supply voltage line 91 may be disposed further away from the retention reset flip-flop 1 than the local power supply voltage line 92 . Therefore, in some cases, even if the magnitude of the global power supply voltage VDDG applied to the global power supply voltage line 91 and the magnitude of the local power supply voltage VDDL applied to the local power supply voltage line 92 are the same, the retention The magnitude of the voltage provided to the reset flip-flop 1 may be different. That is, the level of the global power supply voltage VDDG measured by the retention reset flip-flop 1 may be smaller than the level of the local power supply voltage VDDL.

In some embodiments, the semiconductor device may include a plurality of local power supply voltage lines 92 and a ground line 93 as shown. In this case, different retention reset flip-flops 1 and operating circuits 98 may be connected to each local power supply voltage line 92 . In addition, as illustrated, a plurality of power gating circuits 99 for determining on/off of each local power supply voltage line 92 may be disposed.

FIG. 2 is a block diagram of the retention reset flip-flop of FIG. 1; 3 is a block diagram of the logic gate of FIG. 2;

Referring first to FIG. 2 , the retention reset flip-flop 1 may include a master latch 10 , a slave latch 20 , a scan mux 30 and a logic gate 80 .

The scan mux 30 receives a data signal D, a scan enable signal SE, and a scan input signal SI, and receives one of the data signal D and the scan input signal SI according to a control signal. can output Specifically, when the scan enable signal SE is activated (eg, when the scan enable signal SE of logic high (H) is provided), the scan mux 30 receives a scan input signal ( SI), and when the scan enable signal SE is not activated (for example, when the scan enable signal SE of logic low L is provided), the data signal D can be output. there is.

When the scan input signal SI is output from the scan mux 30, the master latch 10 and the slave latch 20 perform a scan operation of latching and outputting the scan input signal SI, and the scan mux 30 ), the master latch 10 and the slave latch 20 may perform a normal flip-flop operation of latching and outputting the data signal D.

The scan mux 30 may be implemented using, for example, a multiplexer, but the technical idea of the present invention is not limited thereto.

The master latch 10 may store the input data signal D using a local power voltage (VDDL in FIG. 1 ) and output it as a first output signal OS1 . Specifically, the master latch 10 stores the input data signal D using a local power supply voltage (VDDL in FIG. 1) based on the clock signal CK, and outputs it as the first output signal OS1. can do. A specific operation of the master latch 10 will be described later.

The slave latch 10 may perform different operations depending on whether the retention signal RETN is activated.

First, when the retention signal RETN is not activated (for example, when the retention signal RETN is logic high (H) is provided), the slave latch 20 outputs a local power supply voltage (VDDL in FIG. 1). The first output signal OS1 output from the master latch 10 may be stored using and output as the second output signal OS2. Specifically, the slave latch 20 stores the first output signal OS1 using a local power supply voltage (VDDL in FIG. 1) based on the clock signal CK, and outputs the first output signal OS1 as the second output signal OS2. A normal flip-flop operation may be performed.

Thereafter, the second output signal OS2 may be inverted by, for example, an inverter and provided to the output terminal Q, but the technical idea of the present invention is not limited thereto.

In this embodiment, a state in which the retention signal RETN is a logic high (H) is defined as a non-activated state, and a state in which the retention signal RETN is a logic low (L) is defined as an active state. However, the technical spirit of the present invention is not limited to these examples. In some other embodiments of the present invention, a state in which the retention signal RET is a logic low (L) is defined as a non-activated state, and a state in which the retention signal RET is a logic high (H) is defined as an active state can also be defined as

Meanwhile, when the retention signal RETN is activated (for example, when the retention signal RETN is logic low (L) is provided), the slave latch 20 outputs the global power supply voltage (VDDG in FIG. 1). You can perform a retention operation that maintains the stored data by using A detailed operation of the slave latch 20 will also be described later.

Meanwhile, the master latch 10 and the slave latch 20 may perform a reset operation depending on whether the reset signal R is activated.

Specifically, when the reset signal R is not activated (for example, when the reset signal R is logic low L), the master latch 10 and the slave latch 20 generate a clock signal CK ), it is possible to perform a normal flip-flop operation of storing the input data signal D based on and then outputting it as the second output signal OS2. On the other hand, when the reset signal R is activated (for example, when the reset signal R is logic high (H) is provided), the master latch 10 and the slave latch 20 are input data signals D ), a reset operation for outputting the second output signal OS2 of logic low L may be performed.

The logic gate 80 may serve to generate the second control signal CS2 so that the master latch 10 and the slave latch 20 may perform the aforementioned retention and reset operations. That is, in the retention reset flip-flop 1 according to the present embodiment, due to the second control signal CS2 generated by the logic gate 80 and provided to the master latch 10 and the slave latch 20, The master latch 10 and the slave latch 20 can smoothly perform a retention operation and a reset operation. That is, since the circuit required for the master latch 10 and the slave latch 20 to perform the retention operation and the reset operation is implemented very simply, the size of the retention reset flip-flop 1 can be miniaturized. , and further, a semiconductor device including the same may also be miniaturized. In addition, this configuration can also reduce power consumption during flip-flop operation.

The logic gate 80 according to the present embodiment receives the reset signal R, the clock signal CK, and the retention signal RETN and performs a logic operation to generate the second control signal CS. can Hereinafter, an example of the logic gate 80 according to the present embodiment will be described with reference to FIG. 3 .

Referring to FIG. 3 , the logic gate 80 may include a first logic gate LG1 and a second logic gate LG2.

The first logic gate LG1 may be, for example, an OR gate that performs an OR operation. Specifically, the first logic gate LG1 may receive the reset signal R and the clock signal CK, perform an OR operation according to the signal level, and output the result as the first control signal CS1. there is.

The second logic gate LG2 may be, for example, a NAND gate that performs a NAND operation. Specifically, the second logic gate LG2 receives the first control signal CS1 output from the first logic gate LG1 and the retention signal RETN, performs a NAND operation according to the signal level, and The result may be output as the second control signal CS2. The second control signal CS2 thus output may be provided to at least one of the master latch ( 10 in FIG. 2 ) and the slave latch ( 20 in FIG. 2 ).

In FIG. 3 , as an example of the logic gate 80 according to the present embodiment, an OR gate performing an OR operation between a reset signal R and a clock signal CK, and an output CS1 and a retention signal RETN of the OR gate ), but the technical idea of the present invention is not limited thereto. If necessary, the internal configuration of the logic gate 80 may be modified and implemented into a different configuration.

4 is a circuit diagram of a retention reset flip-flop in accordance with some embodiments of the present invention. 5 and 6 are circuit diagrams of the inverter of FIG. 4 .

Referring to FIG. 4 , the retention reset flip-flop 1 may include a master latch 10 , a slave latch 20 , a scan mux 30 and a logic gate 80 .

The scan mux 30 may include, for example, a plurality of inverters I1 to I3.

The inverter I2 may invert and output the scan enable signal SE. The inverter I1 is controlled by the output of the inverter I1 and the scan enable signal SE to invert and output the data signal D. The inverter I3 is controlled by the output of the inverter I1 and the scan enable signal SE, so that the scan input signal SI can be inverted and output.

Accordingly, the voltage level of the node A may be determined according to the signal level of the scan enable signal SE. For example, when the scan enable signal SE is activated (SE=H), the voltage level of the node A may vary according to the signal level of the scan input signal SI. That is, the scan input signal SI may be input to the master latch 10 .

Also, when the scan enable signal SE is inactivated (SE=L), the voltage level of the node A may vary according to the signal level of the data signal D. That is, the data signal D may be input to the master latch 10 .

The master latch 10 may include a transfer gate TG1, an inverter I5, and a third logic gate LG3.

The transfer gate TG1 is controlled by the voltage level of the node E and the voltage level of the node D to provide the voltage of the node A to the node T.

The third logic gate LG3 may perform a NOR operation on the voltage level of the node T and the reset signal R and provide the result to the node B. When the reset signal R is not activated (for example, when the reset signal R is logic low L), the third logic gate LG3 inverts the voltage level of the node T to It can serve as an inverter provided to (B). When the reset signal R is activated (for example, when the reset signal R is logic high (H) is provided), the third logic gate LG3 operates regardless of the voltage level of the node T, The voltage level of (B) can be determined as logic low (L). A specific operation for this will be described later.

The inverter I5 is controlled by the voltage level of the node E and the voltage level of the node D, so that the voltage level of the node B may be inverted and transmitted to the node T.

The slave latch 20 may include a plurality of inverters I6 to I9.

The inverter I6 may invert the voltage level of the node B by controlling the voltage level of the node D and the voltage level of the node E, and provide the inverted voltage level to the node C. Inverter I7 may invert the voltage level of node C and provide it to node E. The inverter (I8) inverts the voltage level of the node (C) and provides it to the inverter (I9), the inverter (I9) is controlled by the voltage level of the node (E) and the voltage level of the node (D), the inverter ( The output of I8) can be inverted and provided to node C.

The logic gate 80 may include a first logic gate LG1 and a second logic gate LG2.

The first logic gate LG1 may receive the reset signal R and the clock signal CK, and perform an OR operation according to the signal level to determine the voltage level of the node F.

The second logic gate LG2 may receive the voltage level of the node F and the retention signal RETN, and determine the voltage level of the node D by performing a NAND operation according to the voltage level or the signal level.

The inverter I10 may invert the voltage level of the node C and provide the inverted voltage level to the output terminal Q. In some other embodiments of the present invention, the inverter I10 may be omitted as needed.

The global power supply voltage VDDG is provided to the inverters I8 and I9 of the retention reset flip-flop 1 and to the first and second logic gates LG1 and LG2, and to the other elements. A local power supply voltage (VDDL) may be provided. In other words, the inverters I8 and I9 of the retention reset flip-flop 1 and the first and second logic gates LG1 and LG2 are driven using the global power supply voltage VDDG. Other elements may be driven using the local power supply voltage (VDDL).

For example, referring to FIG. 5 , the inverter I6 may include transistors MP1 , MP2 , MN1 , and MN2 connected in series between the local power supply voltage VDDL and the ground voltage.

Specifically, the inverter I6 includes a transistor MP1 that is gated on the voltage level of node D and transfers the local power supply voltage VDDL to node C, and a transistor MP1 that is gated on the voltage level of node B and transmits the local power supply voltage VDDL to node C. A transistor MP2 that transfers the power supply voltage VDDL to node C, a transistor MN1 that is gated on the voltage level of node B and provides a ground voltage to node C, and a node E It may include a transistor MN2 gated to a voltage level to provide a ground voltage to node C.

Here, the meaning of the term providing the ground voltage to the node (C) means that the node (C) is grounded, and a predetermined voltage (eg, VSS) lower than the local power supply voltage (VDDL) to the node (C). may include all cases where a is provided. Hereinafter, in this specification, the expression of providing a ground voltage to a specific node should be understood to include all of these meanings.

Although FIG. 5 shows only the inverter I6 as an example of a device driven using the local power supply voltage VDDL, the other devices using the local power supply voltage VDDL also use a local power supply voltage in a similar manner. (VDDL).

For example, referring to FIG. 6 , the inverter I9 may include transistors MP3 , MP4 , MN3 , and MN4 connected in series between the global power supply voltage VDDG and the ground voltage.

Specifically, the inverter I9 includes a transistor MP3 that is gated on the voltage level of the node E and transfers the global power supply voltage VDDG to the node C, and an output of the inverter I8 (actual node C is the result of inverting the voltage level of ) and the transistor MP4 that transfers the global power supply voltage VDDG to the node C, and the output of the inverter I8 are gated and the node C has a ground voltage and a transistor MN4 that is gated on the voltage level of the node D and provides a ground voltage to the node C.

Although FIG. 6 shows only the inverter I9 as an example of a device driven using the global power supply voltage VDDG, the other devices using the global power supply voltage VDDG use a similar method to obtain the global power voltage. (VDDG).

Meanwhile, the logic gate 80 shown in FIG. 4 may be variously implemented by combining a plurality of transistors. Hereinafter, this will be described in more detail with reference to FIGS. 7 to 10 .

7 to 10 are circuit diagrams of the logic gates of FIG. 4 .

Hereinafter, with reference to FIGS. 7 and 8, an example and another example of implementing a logic gate 80 by combining a plurality of transistors will be described first, and with reference to FIGS. 9 and 10, modified implementations Explain.

Referring first to FIG. 7 , the logic gate 80 may include a plurality of transistors MP11 to MP13 and MN11 to MN13 gated by a clock signal CK, a reset signal R, and a retention signal RETN. can

The transistor MP11 is gated on the clock signal CK to provide the global power supply voltage VDDG to the node D, and the transistor MP12 is gated on the reset signal R to provide the global power supply voltage VDDG. It can be provided to node (D). As shown, the transistors MP11 and MP12 may be connected in series between the global power supply voltage VDDG and the node D.

Transistor MP13 may be gated on retention signal RETN to provide global power supply voltage VDDG to node D. As illustrated, the transistors MP11, MP12, and MP13 may be connected in parallel between the global power supply voltage VDDG and the node D.

Transistor MN12 may be gated on clock signal CK to provide a ground voltage to node D, and transistor MN11 may be gated on reset signal R to provide ground voltage to node D. there is. As shown, the transistors MN12 and MN11 may be connected in parallel between the ground voltage and the node D.

Transistor MN13 may be gated on retention signal RETN to provide a ground voltage to node D. As illustrated, the transistors MN12, MN11, and MN13 may be connected in series between the ground voltage and the node D.

Referring next to FIG. 8 , the logic gate 80 may include a plurality of transistors MP14 to MP16 and MN14 to MN16 gated by a clock signal CK, a reset signal R, and a retention signal RETN. can

The transistor MP15 is gated on the clock signal CK to provide the global power supply voltage VDDG to the node D, and the transistor MP14 is gated on the reset signal R to provide the global power supply voltage VDDG. It can be provided to node (D). As shown, the transistors MP15 and MP14 may be connected in series between the global power supply voltage VDDG and the node D.

Transistor MP16 may be gated on retention signal RETN to provide global power supply voltage VDDG to node D. As illustrated, the transistors MP14, MP15, and MP16 may be connected in parallel to each other between the global power supply voltage VDDG and the node D.

Transistor MN14 can be gated on clock signal CK to provide a ground voltage to node D, and transistor MN15 can be gated to reset signal R to provide ground voltage to node D. there is. Transistors MN14 and MN15 may be connected in parallel to each other between the ground voltage and the node D, as shown.

Transistor MN16 may be gated on retention signal RETN to provide a ground voltage to node D. As shown, the transistors MN14, MN15, and MN16 may be serially connected to each other between the ground voltage and the node D.

FIG. 9 is a modified example of the implementation described above with reference to FIG. 7 . Compared to the embodiment described with reference to FIG. 7 , the positions of the transistors MN11 to MN13 are modified. Specifically, in the implementation described with reference to FIG. 7 above, one end of the transistors MN11 and MN12 connected in parallel to each other is directly connected to the node D between the node D and the ground voltage, but in this case, the transistor One end of (MN13) is directly connected to node D.

FIG. 10 is a modified example of the implementation described above with reference to FIG. 8 . Likewise, compared to the implementation described with reference to FIG. 8 , the positions of the transistors MN14 to MN16 are modified. Specifically, in the implementation described with reference to FIG. 8 above, one end of the transistors MN14 and MN15 connected in parallel to each other is directly connected to the node D between the node D and the ground voltage, but in this case, the transistor One end of (MN16) is directly connected to node D.

11 to 13 are views for explaining the operation of a retention reset flip-flop according to some embodiments of the present invention.

First, in the retention reset flip-flop shown in FIG. 4, the voltage level of each node D, E, and F according to the signal levels of the reset signal R, the clock signal CK, and the retention signal RETN. Summarizing is shown in Table 1 below.

case R C.K. RETN F-node D-node Enode One 0 0 0 0 One 0 2 0 0 One 0 One 0 3 0 One 0 One One 0 4 0 One One One 0 One 5 One 0 0 One One 0 6 One 0 One One 0 One 7 One One 0 One One 0 8 One One One One 0 One

(Here, 1 represents a state in which the signal (voltage) level is logic high (H), and 0 represents a state in which the signal (voltage) level is logic low (L))

Hereinafter, a case in which the retention reset flip-flop 1 operates as a normal flip-flop will be described with reference to Table 1 and FIG. 11 first.

First, when the retention reset flip-flop 1 operates as a normal flip-flop, both the retention signal RETN and the reset signal R are inactivated. In this embodiment, the case in which the retention signal RETN is inactivated is defined as the case in which the signal level of the retention signal RETN is logic high (H), and the case in which the reset signal R is inactivated is defined as the case in which the reset signal ( Since the signal level of R) is defined as a case where the signal level is logic low (L), cases 2 and 4 in Table 1 correspond to this case.

Referring to Table 1, in cases 2 and 4, the signal level of the clock signal CK and the voltage level of the node D are opposite to each other. That is, when the signal level of the clock signal CK is logic high (H), the voltage level of the node D becomes logic low (L), and the signal level of the clock signal CK is logic low (L). In this case, the voltage level of node D becomes logic high (H). That is, the logic gate 80 performs an inverter function as shown in FIG. 11 . More specifically, since the voltage level of the node (F in FIG. 4 ) is the same as the signal level of the clock signal CK, the second logic gate LG2 can perform an inverter function.

Meanwhile, since the reset signal R is deactivated, the third logic gate (LG3 in FIG. 4 ) performing the NOR operation included in the master latch 10 operates only in cases 11 and 12 of Table 2 below.

case R T-node LG3 (NOR gate) output = B node 11 0 0 One 12 0 One 0 13 One 0 0 14 One One 0

(Here, 1 represents a state in which the signal (voltage) level is logic high (H), and 0 represents a state in which the signal (voltage) level is logic low (L))

Referring to Table 2, in cases 11 and 12, the voltage level of the node T and the voltage level of the node B are opposite to each other. That is, when the voltage level of node T is logic high (H), the voltage level of node B becomes logic low (L), and when the voltage level of node T is logic low (L), The voltage level of node B becomes logic high (H). That is, the third logic gate LG3 performs an inverter function as shown in FIG. 11 .

Accordingly, the retention reset flip-flop 1 performs a normal flip-flop operation of latching and outputting the data signal D or the scan input signal SI based on the clock signal CK.

Next, referring to Table 1 and FIG. 12, a case in which the retention reset flip-flop 1 performs a retention operation will be described.

When the retention reset flip-flop 1 performs a retention operation, the retention signal RETN is activated and the reset signal R is deactivated. In this embodiment, the case where the retention signal RETN is activated is defined as the case where the signal level of the retention signal RETN is logic low (L), and the case where the reset signal R is inactivated is defined as the reset signal ( Since the signal level of R) is defined as a case where the signal level is logic low (L), cases 1 and 3 in Table 1 correspond to this case.

Referring to Table 1, in cases 1 and 3, the voltage level of the node D always maintains a logic high (H) state regardless of the signal level of the clock signal CK. That is, the logic gate 80 performs a function of continuously providing the global power supply voltage VDDG to the node D as shown in FIG. 12 .

Meanwhile, in cases 1 and 3 of Table 1, the voltage level of node E is always maintained at logic low (L) by inverter I7, so inverter (I6 in FIG. 4) does not operate. Therefore, the data stored in the master latch 10 is not transferred to the slave latch 20, and the slatch latch 20 performs a retention operation for preserving data using the global power supply voltage VDDG.

Next, referring to Tables 1 and 2 and FIG. 13, a case in which the retention reset flip-flop 1 performs a reset operation will be described.

First, when the retention reset flip-flop 1 performs a reset operation, the retention signal RETN is deactivated and the reset signal R is activated. In this embodiment, a case in which the retention signal RETN is inactivated is defined as a case in which the signal level of the retention signal RETN is a logic high (H), and a case in which the reset signal R is activated is defined as a case in which the reset signal ( Since the signal level of R) is defined as a case where the signal level is logic high (H), cases 6 and 8 in Table 1 correspond to this case.

Referring to Table 1, in cases 6 and 8, the voltage level of the node D always maintains a logic low (L) state regardless of the signal level of the clock signal CK. That is, the logic gate 80 continuously provides a ground voltage to the node D as shown in FIG. 13 .

Meanwhile, since the reset signal R is activated, the third logic gate (LG3 in FIG. 4 ) performing the NOR operation included in the master latch 10 operates only in cases 13 and 14 of Table 2.

Referring to Table 2, in cases 13 and 14, the voltage level of node B always maintains logic low L regardless of the voltage level of node T. That is, the third logic gate LG3 continuously provides a ground voltage to the node B as shown in FIG. 13 .

Accordingly, the retention reset flip-flop 1 always outputs a logic low (L) signal to the output terminal Q regardless of the data latched in the master latch 10 and the slave latch 20. Reset operation do

As such, the retention reset flip-flop 1 according to the present embodiment reliably performs a normal flip-flop operation, a retention operation, and a reset operation by using the logic gate 80 occupying a relatively small area in the device. can do.

14 is a circuit diagram of a retention reset flip-flop in accordance with some embodiments of the invention. Hereinafter, differences from the above-described embodiment will be mainly described.

Referring to FIG. 14, the difference between the retention reset flip-flop 2 and the retention reset flip-flop 1 described above with reference to FIG. 4 is that the output terminal Q has an inverter (I10 in FIG. 4) instead of This is the point where the fourth logic gate LG4 is disposed.

The fourth logic gate LG4 may be a NOR gate that performs a NOR operation on the signal level of the reset signal R and the voltage level of the node C and outputs the result.

When the reset signal R is inactivated, as described above, the fourth logic gate LG4 performs an inverter function, so the retention reset flip-flop 2 performs a normal flip-flop operation and a retention operation. can do.

Also, since the fourth logic gate LG4 always provides a ground voltage to the output terminal Q when the reset signal R is activated, the retention reset flip-flop 2 can perform a reset operation.

In particular, in the retention reset flip-flop 2, when the reset signal R is activated, the fourth logic gate LG4 is grounded to the output terminal Q regardless of the signal level of the retention signal RETN. voltage is provided. That is, even when the retention reset flip-flop 2 is performing a retention operation (even when the retention signal RETN is activated), the reset operation is performed immediately when the reset signal R is activated. .

Although the embodiments of the present invention have been described with reference to the accompanying drawings, the present invention is not limited to the above embodiments and can be manufactured in a variety of different forms, and those skilled in the art in the art to which the present invention belongs A person will understand that the present invention may be embodied in other specific forms without changing the technical spirit or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not limiting.

1, 2: retention reset flip-flop
10: master latch
20: slave latch
80: logic gate

Claims (20)

a master latch for storing an input data signal using a local power supply voltage and a clock signal and outputting the data signal as a first output signal;
a slave latch storing the first output signal using a global power supply voltage different from the local power supply voltage, the clock signal, and a retention signal and outputting the first output signal as a second output signal;
a first logic gate that receives one signal and another one of the retention signal, the clock signal, and the reset signal, and outputs a first control signal generated by performing a first logic operation; and
A second control signal generated by receiving the other one of the retention signal, the clock signal, and the reset signal and the first control signal and performing a second logic operation is transmitted to at least one of the master latch and the slave latch. a second logic gate providing
The slave latch,
When the reset signal is activated, a reset operation is performed to fix the second output signal to a predetermined signal level;
and determining a signal level of the second output signal based on a signal level of the data signal when the reset signal is inactivated. delete According to claim 1,
The first logic operation and the second logic operation are different from each other. According to claim 3,
The first logical operation includes an OR operation,
The second logic operation includes a NAND operation. According to claim 1,
The first logic gate includes an OR gate receiving the reset signal and the clock signal, performing an OR operation, and providing the first control signal generated as a result to the second logic gate. According to claim 5,
The second logic gate receives the retention signal and the first control signal, performs a NAND operation, and provides the second control signal generated as a result to at least one of the master latch and the slave latch. A semiconductor device comprising a gate. According to claim 1,
The semiconductor device of claim 1 , wherein the global power supply voltage is provided to the first logic gate and the second logic gate. According to claim 1,
and a third logic gate receiving the reset signal and the second output signal and performing a third logic operation different from the first and second logic operations. According to claim 8,
The third logic operation includes a NOR operation. According to claim 1,
The semiconductor device of claim 1 , wherein the slave latch performs a reset operation when the reset signal is activated while the retention signal is activated and the slave latch performs a retention operation. a first line to which a global power supply voltage is applied;
a second line separated from the first line and to which a local power supply voltage is applied;
a first operating circuit connected to the second line and using the local power supply voltage;
a first power gating circuit determining whether to apply the local power supply voltage to the first operating circuit; and
a first retention reset flip-flop connected to the first line and the second line;
The first retention reset flip-flop,
a master latch connected to the second line, storing a data signal input using a clock signal, a retention signal, and a reset signal and outputting the data signal as a first output signal;
a slave latch connected to the first line, storing the first output signal using the clock signal, retention signal, and reset signal and outputting the first output signal as a second output signal;
and a logic gate receiving the retention signal, the clock signal, and the reset signal and providing a control signal generated by performing a logic operation to at least one of the master latch and the slave latch. According to claim 11,
The logic gate is connected to the first line. According to claim 11,
The logic gate is
a first logic gate for performing a first logic operation;
and a second logic gate connected to an output of the first logic gate and performing a second logic operation different from the first logic operation. According to claim 13,
The first logic gate includes an OR gate for performing an OR operation on the reset signal and the clock signal;
The second logic gate includes a NAND gate performing a NAND operation on an output of the OR gate and the retention signal. According to claim 11,
The slave latch,
and an inverter controlled by the control signal to invert the first output signal. a master latch for storing an input data signal using a local power supply voltage and outputting the stored data signal as a first output signal;
a slave latch storing the first output signal using a global power supply voltage different from the local power supply voltage and outputting the first output signal as a second output signal;
A logic gate receiving first to third signals and providing the global power supply voltage to at least one of the master latch and the slave latch;
The logic gate is
a first transistor gated by the first signal to provide the global power supply voltage to a first node;
a second transistor gated with the first signal to provide a ground voltage to the first node;
a third transistor gated with the second and third signals to provide the global power supply voltage to the first node;
and a fourth transistor gated with the second and third signals to provide the ground voltage to the first node. According to claim 16,
When the first signal is activated, the slave latch performs a retention operation;
When the second signal is activated, the slave latch performs a reset operation;
When the first and second signals are not activated, the slave latch outputs a second output signal based on the third signal. a master latch for storing an input data signal using a local power supply voltage and a clock signal and outputting the data signal as a first output signal;
a slave latch storing the first output signal using a global power supply voltage different from the local power supply voltage, the clock signal, and a retention signal and outputting the first output signal as a second output signal;
a first logic gate that receives the retention signal, the clock signal, and the reset signal and provides a first control signal generated by performing a first logic operation to at least one of the master latch and the slave latch; and
and a second logic gate receiving the second output signal and the reset signal and performing a second logic operation. According to claim 18,
The second logic operation includes a NOR operation, and the second logic gate includes a NOR gate. According to claim 18,
The master latch,
and a third logic gate receiving the input data signal and the reset signal and performing a third logic operation.

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