KR20090040519A - Apparatus for retention flip-flop - Google Patents

Apparatus for retention flip-flop Download PDF

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Publication number
KR20090040519A
KR20090040519A KR1020070105912A KR20070105912A KR20090040519A KR 20090040519 A KR20090040519 A KR 20090040519A KR 1020070105912 A KR1020070105912 A KR 1020070105912A KR 20070105912 A KR20070105912 A KR 20070105912A KR 20090040519 A KR20090040519 A KR 20090040519A
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KR
South Korea
Prior art keywords
latch
retention
inverter
flop
slave latch
Prior art date
Application number
KR1020070105912A
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Korean (ko)
Inventor
강원묵
Original Assignee
삼성전자주식회사
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Priority to KR1020070105912A priority Critical patent/KR20090040519A/en
Publication of KR20090040519A publication Critical patent/KR20090040519A/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0372—Bistable circuits of the master-slave type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3562—Bistable circuits of the master-slave type
    • H03K3/35625—Bistable circuits of the master-slave type using complementary field-effect transistors

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  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a retention flip-flop device, comprising: a master latch for transmitting a signal at an input terminal to a slave latch according to a control signal, and a signal transmitted from the master latch; And a retention latch for outputting to the output terminal and a retention latch for maintaining an existing value when the power is turned off, by sharing one cell included in the slave latch with a cell used in the retention latch, By reducing the number of cells operating compared to flip-flops, power consumption can be reduced and gains in terms of leakage current, performance and area can be increased.

Description

Retention Flip-Flop Device {APPARATUS FOR RETENTION FLIP-FLOP}

The present invention relates to a retention flip-flop device, and more particularly to a retention flip-flop device having a small area and low power overhead.

Recently, as the process of semiconductor circuits has been lowered to less than 100 nm, many companies have experienced problems in that the share of problems due to leakage current exceeds the share of problems due to dynamic power. Is working on low power design. The most commonly used low power design is MTCMOS (Multi-Threshold CMOS) technology. However, the MTCMOS technology has a problem in that the power is turned off in the sleep mode and the contents stored in the flip-flop are erased so that the MTCMOS is not restored to the previous state when the normal mode is switched back to the normal mode. Therefore, in the related art, various retention flip flops that store the previous state have been developed to restore the state before the power off.

The retention flip-flop provided in the related art basically includes a master latch 100 and a slave latch 102, the master latch 100 and a slave latch 102, as shown in FIG. 1. ), And a switch (104, 106), and a switch controller 108 to connect the power supply of the slave latch 102 is always on (ON) to use the technique to maintain the previous state.

However, in the flip-flop having the above structure, when the slave latch 102 is configured of cells having high processing speed in order to improve the processing speed, even when the master latch 100 is powered off, the leakage current is large. When the slave latch 102 is composed of cells with low leakage current to reduce the leakage current, the processing speed of the entire flip-flop is reduced, resulting in a problem of degrading performance.

Accordingly, in order to solve the problems of the leakage current and the processing speed, the slave latch 202 stage of the slave latch 202 is turned off when the power is turned off in addition to the master latch 200 and the slave latch 202 as shown in FIG. 2. A retention flip-flop has been provided having a retention latch 204 that retains the value. Here, even when the power is turned off, the retention latch 204 is continuously supplied with power, thereby maintaining the value of the slave latch 202 stage. The retention flip-flop of such a structure is divided into a part performing normal operation and a part performing retention, so that a good performance can be obtained in terms of both speed and leakage current. It must be provided separately to have the problem that the area increases.

Thus, conventionally, as shown in FIG. 3, a retention flip-flop that separates the slave latch 306 from the output path Q 302 has been provided. That is, as shown in FIG. 3, the data input from the input path D 300 is output to the output path Q 302 only through the master latch 304 without passing through the slave latch 306. Branches were provided with retention flip-flops. The retention flip-flop of FIG. 3 maintains the power of the master latch 304 and the slave latch 306, respectively, and turns on the power of the slave latch 306 when the master latch 304 is turned off. The previous data is kept as it is. This retention flip-flop has a reduction latch area that is not used as compared to the retention flip-flop shown in FIG. 2, thereby reducing an area, reducing the overall inverter, and gaining in terms of leakage current. There is a problem that a delay may occur internally because the three-state inverter driving the drive must simultaneously drive the output buffer and the slave latch.

The present invention was derived to solve the above problems, and an object of the present invention is to provide a retention flip-flop device.

Another object of the present invention is to provide a retention flip-flop device having high gain in terms of leakage current, performance, and area.

It is still another object of the present invention to provide a retention flip-flop device in which a slave latch and a retention latch share one cell.

According to an aspect of the present invention for achieving the above object, a retention flip-flop device is a master latch for transmitting a signal of an input terminal to a slave latch in accordance with a control signal, and from the master latch And a retention latch for storing the output signal of the slave latch by sharing the slave latch for outputting the transmitted signal to the output terminal and one cell included in the slave latch.

In the present invention, the slave latch and the retention latch share one cell in the retention flip-flop, thereby reducing the power consumption by reducing the number of cells operating as compared to the conventional retention flip-flop. The gain can be increased in terms of leakage current, performance and area.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In describing the present invention, when it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

Hereinafter, a retention flip-flop device in which a slave latch and a retention latch share one cell will be described. The tri-state inverter, which will be described below, is one of logic elements having three output states, and serves to transmit or cut a signal by opening and closing a circuit between an input terminal and an output terminal according to a control signal. do. At this time, when the circuit is opened by the control signal, the three-state inverter reverses the signal and outputs the same as the inverter.

Fig. 4 shows the construction of a retention flip-flop according to the present invention.

As shown in FIG. 4, the retention flip-flop includes a master latch 400, a slave latch 402, a retention latch 404, and two tri-state-inverters 416. 426). In this case, the slave latch 402 and the retention latch 404 share one cell, that is, the tri-state inverter 436. The master latch 400 and the slave latch 402 each include one tri-state inverter 420 and 436 and one inverter 418 and 432, and the retention latch 404 is the slave latch. And a three state inverter 436 included in 402 and a three state inverter 442 for the retention mode. Here, the retention latch 404 is composed of cells with low leakage current.

Referring to FIG. 4, first, the retention flip-flop is divided into cells that receive power from the VDD 450 and cells that receive power from the VDDC 448. Here, the VDD 450 is a power source for a normal operation mode, the VDDC 448 is a power source for a retention mode, and the VDDC 448 maintains a previous state while the VDD 450 is turned off. Always remain ON for retention mode.

The master latch 400, the two tri-state inverters 416 and 426, and the inverter 432 not shared with the retention latch 404 in the slave latch 402 are powered from the VDD 450. The retention latch 404 is supplied with power from the VDDC 448. That is, the three-state inverter 436 simultaneously included in the slave latch 402 and the retention latch 404 receives power from the VDDC 448.

 As described above, the retention latch 404 is supplied with power from the VDDC 448 which is always ON, thereby maintaining the previous state even when the power of the VDD 450 is turned off. .

The clock pulse signals C (412, 424 430, 440) and the CZs (414, 422, 428, 438) supplied to each of the three-state inverters are opposite in phase to each other and have the same frequency. When the power supply of the VDD 450 is turned off, the supply is stopped. The circuit for generating the clock pulse signals C and CZ used in the retention flip-flop is as shown in FIG. 3.

Referring to the basic operation of the retention flip-flop, the tri-state inverter 416, which receives the input signal from the input path D 410, receives the input signal in response to the clock pulse signals C 412 and CZ 414. Output to the inverter 418 of the master latch 400. That is, the tri-state inverter 416 receives the signal from the input path D 410 when the clock pulse signal C 412 is zero, and the master latch 400 enters the value D 410. It is delivered to the input of the three-state inverter 426. When the clock pulse signal C 412 becomes 1, the tri-state inverter 416 blocks the path of the signal entering the D 410 to the master latch 400. At this time, the tri-state inverter 426 outputs and transmits the signal received from the D 410 of the master latch 400 to the slave latch 402.

The slave latch 402 outputs the signal of the master latch 400 received through the inverter 432 to the output path Q 434. At this time, the signal output from the inverter 432 is output to the output path Q 434 and simultaneously to the three-state inverter 436 included in the slave latch 402 and the retention latch 404.

The three-state inverter 436 included in the slave latch 402 and the retention latch 404 simultaneously blocks or blocks the signal from the inverter 432 by the clock pulse signals C 440 and CZ 438. The output is output to the three-state inverter 442 of the inverter 432 and the retention latch 404. Here, the three-state inverter 436 simultaneously included in the slave latch 402 and the retention latch 404 receives power from the VDDC 448 to operate in both the normal operation mode and the retention mode. .

The tri-state inverter 442 of the retention latch 404 blocks or reverse-converts the signal input from the tri-state inverter by the control signals RET 446 and RETZ 444 for the retention mode control, and then converts the tri-state inverter 442 back to the tri-state inverter 442. Status output to inverter 436.

That is, the three-state inverter 442 is configured as shown in FIG. 5 to maintain previous data when the control signals RET 446 and 506 and RETZ 444 and 504 are signals for the retention mode. The signal input from the tri-state inverter 436 through the input path IN 500 is inversely converted and output to the output path OUT 502, and then output to the tri-state inverter 436. On the other hand, when the control signal RET (446, 506) and RETZ (444, 504) signal is not a signal for the retention mode, the three-state inverter 442 turns off the power from the three-state inverter 436 Cut off the input signal. At this time, since the power turns off the power of the three-state inverter 442, it is possible to reduce the loss of leakage current due to this device.

Here, the control signals RET 446 and RETZ 444 provide a signal for the retention mode to the tri-state inverter 442 when the VDD 450 is powered off to provide the tri-state inverter 442. ) Inverts the input signal and outputs the input signal. When the power of the VDD 450 is not turned off, the tri-state inverter 442 provides a signal for the normal operation mode to the tri-state inverter 442. By cutting off the power supply, the output of the input signal is cut off so that the normal operation mode is not affected.

As described above, the retention flip-flop according to the present invention can retain previous data through the retention latch driven by the VDDC even when the power supply of the VDD is turned off, and six cells operate in the normal operation mode, and the retention is performed. Since only two cells operate in the mode, power consumption can be reduced compared to a conventional retention flip flop in which seven cells operate in the normal operation mode.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined not only by the scope of the following claims, but also by the equivalents of the claims.

1 is a diagram illustrating a device for constructing a retention flip-flop in which a slave latch is always in an ON state according to the prior art;

2 is a view showing a device for constructing a retention flip-flop having a separate retention latch according to the prior art;

3 is a diagram illustrating a device for constructing a retention flip-flop in which a slave latch is separated from an output path according to the prior art;

4 illustrates a device for constructing a retention flip flop according to the present invention; and

5 shows the structure of a typical three-state inverter.

Claims (6)

In a retention flip-flop device, A master latch that delivers a signal from an input to a slave latch according to a control signal, The slave latch for outputting a signal transmitted from the master latch to an output terminal; And a retention latch that shares one cell included in the slave latch and stores an output signal of the slave latch. The method of claim 1, A first power supply for supplying power to a cell of said master latch and a cell of said slave latch not shared with a retention latch; And a second power source for supplying power to a cell shared with the retention latch among the cells of the slave latch and a cell of the retention latch. The method of claim 2, And the second power source is always in an ON state. The method of claim 1, The retention latch includes: a first tri-state inverter (tri-state-inverter) included in the slave latch and the retention latch to perform an operation in a normal operation mode and a retention mode; And a second tri-state inverter (tri-state-inverter) in which the power is supplied and operated only in the retention mode by the retention control signal, and does not operate by cutting off the power supply in the normal operation mode. Device. The method of claim 1, The master latch and the slave latch, Wherein each device comprises at least one tri-state inverter and an inverter The method of claim 1, The control signal is supplied in the normal operation mode, characterized in that not supplied in the retention mode.
KR1020070105912A 2007-10-22 2007-10-22 Apparatus for retention flip-flop KR20090040519A (en)

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8085076B2 (en) * 2008-07-03 2011-12-27 Broadcom Corporation Data retention flip flop for low power applications
US8552761B2 (en) 2010-11-08 2013-10-08 Samsung Electronics Co., Ltd. Flip-flop including keeper circuit
WO2013177759A1 (en) * 2012-05-30 2013-12-05 Qualcomm Incorporated. Reduced dynamic power d flip-flop
KR20160099433A (en) * 2015-02-11 2016-08-22 에스케이하이닉스 주식회사 Semiconductor device including retention circuit
KR20170090336A (en) * 2016-01-28 2017-08-07 삼성전자주식회사 Semiconductor device comprising retset retention flip-flop
US10404240B2 (en) 2016-01-28 2019-09-03 Samsung Electronics Co., Ltd. Semiconductor device comprising low power retention flip-flop
US10608615B2 (en) 2016-01-28 2020-03-31 Samsung Electronics Co., Ltd. Semiconductor device including retention reset flip-flop
KR20230021242A (en) * 2021-08-05 2023-02-14 주식회사 키파운드리 Low power retention flip-flop

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8085076B2 (en) * 2008-07-03 2011-12-27 Broadcom Corporation Data retention flip flop for low power applications
US8552761B2 (en) 2010-11-08 2013-10-08 Samsung Electronics Co., Ltd. Flip-flop including keeper circuit
WO2013177759A1 (en) * 2012-05-30 2013-12-05 Qualcomm Incorporated. Reduced dynamic power d flip-flop
KR20160099433A (en) * 2015-02-11 2016-08-22 에스케이하이닉스 주식회사 Semiconductor device including retention circuit
KR20170090336A (en) * 2016-01-28 2017-08-07 삼성전자주식회사 Semiconductor device comprising retset retention flip-flop
US10404240B2 (en) 2016-01-28 2019-09-03 Samsung Electronics Co., Ltd. Semiconductor device comprising low power retention flip-flop
US10608615B2 (en) 2016-01-28 2020-03-31 Samsung Electronics Co., Ltd. Semiconductor device including retention reset flip-flop
KR20230021242A (en) * 2021-08-05 2023-02-14 주식회사 키파운드리 Low power retention flip-flop
US11990909B2 (en) 2021-08-05 2024-05-21 Sk Keyfoundry Inc. Low power retention flip-flop

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