JP2006013816A - Flip-flop circuit and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To facilitate timing setting of an external control signal for holding data immediately before the power off of a combinational circuit to a flip-flop circuit. <P>SOLUTION: The flip-flop circuit supplies a master clock signal and a slave clock signal of reverse phases from one another to a master latch and a slave latch connected in series with the master latch, thereby shifting the data inputted to the master latch to the slave latch. The flip-flop circuit includes a means for fixing the signal levels of the master clock signal and the slave clock signal to the same value by inputting the external control signal. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a flip-flop circuit and a semiconductor device, and more particularly to a flip-flop circuit and a semiconductor device that are effective in reducing power consumption.

  In an electronic device such as a mobile phone using a battery as a power supply voltage source, it is required to improve the battery performance and reduce the power consumption of a semiconductor IC used in the electronic device in order to extend the battery life.

  In general, a semiconductor IC is composed of a combinational circuit that performs predetermined logical operation processing and a flip-flop circuit that holds data input to and output from the combinational circuit. In order to operate the semiconductor IC in a specific operation mode, Only the circuit that performs the logical operation processing corresponding to the operation mode needs to be operated. Therefore, when a power supply is provided for each of these circuits and the electronic device is operated in a specific operation mode, the power consumption of the electronic device is supplied by supplying power only to the corresponding circuit and cutting off the power of the other circuits. Can be reduced (Patent Document 1).

  However, if a common power source is used for the combinational circuit and the flip-flop circuit, even when the combinational circuit is powered off, the data of the flip-flop circuit connected to the combinational circuit is also destroyed. When the power is turned on again, the data must be initialized and the logical operation process must be started again. In order to avoid this, it is necessary to separate the power sources of the combinational circuit and the flip-flop circuit.

  FIG. 3 is a diagram showing a configuration of a semiconductor IC in which the power sources of the combinational circuit and the flip-flop circuit are separated. According to this configuration, since the power supply VDD2 of the flip-flop circuit 61 can be maintained even when the power supply VDD1 of the combinational circuit 60 is disconnected, the data of the flip-flop circuit 61 when the power supply VDD1 is disconnected is retained. If the data retained after the power supply VDD1 is turned on again is supplied to the combinational circuit 60, the logical operation processing in the combinational circuit 60 can be resumed without initializing the data.

  FIG. 4 shows a configuration of a conventional flip-flop circuit used for such a purpose. The flip-flop circuit includes a master latch 10, a slave latch 20 connected in series with the master latch 10, an output buffer unit 30, a clock generation unit 70, and an inverter 60 connected to the slave latch 20.

  The master latch 10 is composed of clocked inverters 11 and 12 and a NOR circuit 13, and the slave latch 20 is composed of clocked inverters 21 and 22 and a NOR circuit 23.

  The clock generation unit 70 includes a NOR circuit 71 and an inverter 72. When an external clock signal CK and an external control signal POFF (described later) are input, the clock generation unit 70 generates an internal clock signal CK 'and supplies it to the master latch 10 and the slave latch 20. Supply.

  Here, as shown in FIG. 5, the clocked inverter 11 is composed of a pMOS transistor and an nMOS transistor connected in series, and when the internal clock signal CK ′ supplied from the clock generator 70 is at the L level. The signal is turned on and the inverted signal xD of the input data D is output. When the internal clock signal CK ′ is at the H level, it is turned off. The other clocked inverters 12, 21, and 22 have the same configuration.

  From the above, in the flip-flop circuit shown in FIG. 4, when the internal clock signal CK ′ is at the L level, the inverters 11 and 12 of the master latch 10 are in the on state and the off state, respectively. Are in an off state and an on state, respectively, and data D inputted from the outside is taken into the master latch 10 and held. When the internal clock signal CK ′ changes from the L level to the H level, the inverters 11 and 12 of the master latch 10 change to the off state and the on state, respectively, and the inverters 21 and 22 of the slave latch 20 change to the on state and the off state, respectively. As a result, the data D held in the master latch 10 is shifted to the slave latch 20.

  That is, in the flip-flop circuit shown in FIG. 4, the data is shifted from the master latch 10 to the slave latch 20 at the clock edge when the internal clock signal CK ′ changes from the H level to the L level or from the L level to the H level. The data is output to the combinational circuit via the output buffer unit 30.

  The reset signal xR is input to the inverter 60 asynchronously with the external clock signal CK. The output of the inverter 60 is input to the NOR circuit 13 of the master latch 10 and the NOR circuit 23 of the slave latch 20, and resets the data of the master latch 10 and the slave latch 20 regardless of the external clock signal CK.

  The external control signal POFF is input to the clock generator 70 asynchronously with the external clock signal CK, and holds the data of the flip-flop circuit when the power supply VDD1 of the combinational circuit is disconnected as described below. The retained data is supplied to the combinational circuit when the power is turned on again.

  FIGS. 6A and 6B are timing diagrams of the flip-flop circuit. FIG. 6A shows a case where the external control signal POFF is input while the external clock signal CK is at the H level. Indicates a case where the external control signal POFF is input while the external clock signal CK is at the L level. The time when the external control signal POFF is input is T0, and the time when the combinational circuit is powered off is T1.

  First, in FIG. 6A, before the time T0, the external clock signal CK is supplied as it is to the flip-flop circuit as the internal clock signal CK ', and the data is shifted from the master latch 10 to the slave latch 20 at the clock edge. When the external control signal POFF is input at time T0 and the signal level changes from the L level to the H level, the external clock signal CK maintains the H level as it is, and the internal clock signal CK ′ similarly maintains the H level. Therefore, an extra clock edge does not occur in the internal clock signal CK ′ compared with the external clock signal CK, and the data at the time T1 is held in the master latch 10. When the power source VDD1 of the combinational circuit is turned on again and the external control signal POFF changes to the L level, the held data is supplied to the combinational circuit via the slave latch 20 and the output buffer unit 30. Therefore, even when the power supply VDD1 is turned off for a certain period and turned on again, the logical operation processing can be resumed without initializing the data.

However, at the timing shown in FIG. 6B, when the external control signal POFF signal changes from the L level to the H level at time T0, the signal level of the internal clock signal CK ′ changes from the L level to the H level. The signal level of the external clock signal CK remains unchanged at the L level. Therefore, an extra clock edge is generated in the internal clock signal CK ′ as compared with the external clock signal CK. As a result, the data is shifted excessively and the data at the time when the power supply VDD1 is cut off is not held. In order to avoid such data change, as shown in FIG. 6A, the input timing of the external control signal POFF so that the external control signal POFF signal is input within the H level period of the external clock signal CK. Must be controlled.
JP 2001-251180 A

  In order to retain data at the time of power-off of the combinational circuit in the conventional flip-flop circuit, it is necessary to input the external control signal POFF while the external clock signal CK is at the H level, and the timing setting is difficult. there were.

  In the conventional flip-flop circuit, when the reset signal is input, the data of the flip-flop circuit is reset regardless of other input signals. Therefore, if the reset signal is erroneously input during the period in which the data of the flip-flop circuit is retained, there is a problem that the retained data is reset.

The present invention supplies a master clock signal and a slave clock signal having opposite phases to a master latch and a slave latch connected in series to the master latch, thereby shifting data input to the master latch to the slave latch. In the flip-flop circuit configured to be provided, means for fixing the signal level of the master clock signal and the slave clock signal to the same value by input of an external control signal is provided.
Alternatively, the flip-flop circuit includes means for invalidating a reset signal by inputting the external control signal.
Alternatively, in a semiconductor device including a combinational circuit that performs predetermined logical operation processing, and a flip-flop circuit that separates the combinational circuit from a power source and holds data input to and output from the combinational circuit, the flip-flop circuit includes: A master clock signal and a slave clock signal having opposite phases to each other are supplied to a latch and a slave latch connected in series to the master latch, thereby shifting data inputted to the master latch to the slave latch. It is characterized by having means for fixing the signal level of the master clock signal and the slave clock signal to the same value by the input of an external control signal.

  The flip-flop circuit of the present invention can simultaneously deactivate the master latch and the slave latch by fixing the signal level of the master clock and the slave clock to the same value in response to the input of the external control signal. Therefore, there is an advantage that data of the flip-flop circuit immediately before the combination circuit is turned off can be held regardless of the input timing of the external control signal.

  In addition, even when a reset signal is erroneously input while an external control signal is being input, the data held in the flip-flop circuit is not destroyed and the operation of the semiconductor IC becomes stable.

  The purpose of holding the data of the flip-flop circuit immediately before the power supply of the combinational circuit is cut off regardless of the input timing of the external control signal is realized with a simple circuit configuration.

  FIG. 1 is a flip-flop circuit showing an embodiment of the present invention. The flip-flop circuit includes a master latch 10 and a slave latch 20 connected in series to the master latch 10, an output buffer unit 30, a clock generation unit 40, and a NOR circuit 50. Of these, the master latch 10 and the slave latch 20, The output buffer unit 30 has the same configuration as the conventional flip-flop circuit shown in FIG.

  The clock generation unit 40 includes inverters 41, 43, 45, a NAND circuit 42, and a NOR circuit 44. When the external control signal POFF and the external clock signal CK are input, the master clock signal CKM, its inverted signal xCKM, and the slave clock A signal CKS and its inverted signal xCKS are generated and supplied to the master latch 10 and the slave latch 20, respectively.

  The NOR circuit 50 receives a reset signal xR and an external control signal POFF. The output of the NOR circuit 50 is input to the NOR circuit 13 of the master latch 10 and the NOR circuit 23 of the slave latch 20.

  The reset signal xR is input asynchronously with the external clock signal CK, and the data of the master latch 10 and the slave latch 20 can be reset regardless of the external clock signal CK. The external control signal POFF is input asynchronously with the external clock signal CK and immediately before the combination circuit is powered off.

  FIGS. 2A and 2B are timing diagrams for explaining the operation of the flip-flop circuit when the external control signal POFF is input, and correspond to FIGS. 6A and 6B described above, respectively. FIG. As in FIGS. 6A and 6B, the external control signal POFF is input at time T0, and the power supply VDD1 of the combinational circuit is disconnected at time T1 immediately after that. FIG. 6A shows the case where the external control signal POFF is input during the H level period of the external clock signal CK, and FIG. 6B shows the case where the external control signal POFF is input during the L level period of the external clock signal CK. Show.

  During the period when the external control signal POFF is set to L level before time T0, the master clock signal CKM and its inverted signal xCKM generated by the clock generator 40 are transferred to the master latch 10 and the slave clock signal CKS and its inverted signal. xCKS is input to the slave latch 20, and the data D is shifted from the master latch 10 to the slave latch 20 at the clock edge.

  When the external control signal POFF is input at time T0 and the signal level changes from the L level to the H level, both the master clock signal CKM and the slave clock signal CKS are fixed to the L level. Even when the external control signal POFF is input during either the H level or L level period of the external clock signal CK, as shown in FIGS. 2A and 2B, the power source VDD1 of the combinational circuit is disconnected. At time T1, no extra clock edge is generated in the master clock signal CKM with respect to the external clock signal CK. Therefore, the data when the power supply VDD1 of the combinational circuit is disconnected is held in the flip-flop circuit. That is, the data of the flip-flop circuit can be held without depending on the timing at which the external control signal POFF is input.

  In the flip-flop circuit, during the period when the external control signal POFF is input, the output of the NOR circuit 50 is fixed at the L level regardless of the reset signal xR, and the data is not reset. That is, since the reset signal is invalidated by the input of the external control signal POFF, even if the reset signal is erroneously input during the period of holding the data of the flip-flop circuit, the data is not reset. IC operation becomes stable.

  In the above embodiment, the combinational circuit and the flip-flop circuit operate in the positive logic. However, in the case of operating in the negative logic, the signal levels of the master clock signal and the slave clock signal are set to H by the input of the external control signal POFF. It only has to be fixed to the level.

  Since the timing setting for holding data in the flip-flop circuit becomes simple, the design of the semiconductor IC with low power consumption becomes easy.

It is a figure which shows the structure of the flip-flop circuit based on the Example of this invention. (A), (b) It is a timing diagram explaining operation | movement of the flip-flop circuit based on the Example of this invention. It is a figure which shows the circuit structure of semiconductor IC. It is a figure which shows the structure of the conventional flip-flop circuit. It is a figure which shows the structure of a clocked inverter. (A), (b) It is a timing diagram explaining operation | movement of the conventional flip-flop circuit.

Explanation of symbols

10 Master latch
11, 12, 21, 22 Clocked inverter
13, 23, 44, 50, 71 NOR circuit
20 Slave latch
30 Output buffer section
31, 32, 33, 41, 43, 45, 60, 72 Inverter
40, 70 clock generator
42 NAND circuit
60 Combination circuit
61 Flip-flop circuit

Claims (3)

  A master clock signal and a slave clock signal having opposite phases to each other are supplied to the master latch and the slave latch connected in series to the master latch, thereby shifting the data input to the master latch to the slave latch. In the flip-flop circuit, a means for fixing the signal level of the master clock signal and the slave clock signal to the same value by inputting an external control signal is provided.   2. The flip-flop circuit according to claim 1, further comprising means for invalidating a reset signal upon input of the external control signal. In a semiconductor device including a combinational circuit that performs a predetermined logical operation process, and a flip-flop circuit that holds data to be input to and output from the combinational circuit by separating the combinational circuit and a power source,
The flip-flop circuit supplies a master clock signal and a slave clock signal having opposite phases to a master latch and a slave latch connected in series to the master latch, and thereby the data input to the master latch is transmitted to the slave latch. And a means for fixing the signal level of the master clock signal and that of the slave clock signal to the same value by the input of an external control signal.

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