JP2007006290A - Digital integrated circuit and control method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit having a communication interface and characterized in that power consumption is reducible by eliminating a leak current by actualizing power gating by an easy method without following a special procedure. <P>SOLUTION: The semiconductor integrated circuit is equipped with an interface which communicates with an external circuit when an enable signal inputted from an external circuit is turned on; a power supply control unit which controls supply electric power to the interface, and a core which is connected to the interface to perform various processing; and the power supply control unit supplies the electric power to the interface when the enable signal is turned on, and stops the supply of the electric power to the interface when the enable signal is turned off. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit and a control method thereof, and more particularly to a semiconductor integrated circuit having a communication interface and a control method thereof.

  Conventionally, various technological developments related to reduction in power consumption of semiconductor integrated circuits have been promoted. In semiconductor integrated circuits, the power consumption is reduced by the circuit configuration based on CMOS elements, but in particular, in the field of portable electronic devices, etc., it is often driven by a battery. Is required.

  On the other hand, as the semiconductor miniaturization technology and the operating voltage are reduced, the proportion of the leakage current in the current consumption of the entire circuit is not negligible even in a CMOS circuit. For this reason, techniques relating to reduction of leakage current have also been developed.

  For example, Patent Document 1 discloses a technique for reducing the leakage current of a CMOS gate by turning off the CMOS gate circuit with an NMOS transistor having a deep threshold voltage when the chip is disabled.

  In Patent Document 2, data retention is maintained by intermittently floating at least one of the two power lines of the flip-flop constituting the data retention circuit during standby. A technique for reducing the off-leakage current of a transistor is disclosed.

In addition, in Patent Document 3, power is supplied to the combinational circuit only when the flip-flop circuit connected to the output terminal of the combinational circuit captures data according to the control signal, and power is supplied to the combinational circuit at other times. A technique for reducing leakage current by not supplying is disclosed.
JP 07-161190 A JP 09-185887 A JP 2002-110920 A

  The most effective method for preventing leakage current in the semiconductor integrated circuit is a method called power gating that stops the power supply itself to the corresponding circuit portion when it does not operate. That is, when there are a plurality of blocks inside a semiconductor integrated circuit and a specific block does not operate for a specific period, it is unnecessary by controlling power supply to the specific block only during the non-operating period. It is intended to eliminate a leak current.

  Power gating is an effective method in general. However, when trying to apply to an entire semiconductor integrated circuit having individual specific functions and circuit structures, a control method for effectively stopping the power supply while maintaining the operation of individual blocks that are complexly related to each other is found. It is not easy.

  Even if a control method can be found, if it is applied to the entire semiconductor integrated circuit, the circuit itself for generating the control signal may be complicated and large-scale.

  The present invention has been made in view of the above circumstances. In a semiconductor integrated circuit having a communication interface, power gating is realized by a very simple method without taking a special procedure, thereby eliminating leakage current and reducing power consumption. An object of the present invention is to provide a semiconductor integrated circuit and a control method thereof.

  In order to solve the above problem, a semiconductor integrated circuit according to the present invention provides an interface unit that communicates with the external circuit when an enable signal input from the external circuit is on, as described in claim 1, A power supply control unit that controls supply of power to the interface unit; and a core unit that is connected to the interface unit and performs various processes. The power supply control unit includes the interface when the enable signal is on. The power supply to the interface unit is supplied, and the power supply to the interface unit is stopped when the enable signal is off.

  In order to solve the above-described problem, a semiconductor integrated circuit according to the present invention includes an interface unit that communicates with the external circuit when an enable signal input from the external circuit is on. A power supply control unit that controls supply of power to the interface unit, a core unit that is connected to the interface unit and performs various processes, and a data holding unit that is provided at a connection part of the interface unit and the core unit The power supply control unit supplies power to the interface unit when the enable signal is on, stops supplying power to the interface unit when the enable signal is off, and the data The holding unit holds transmission data from the interface unit to the core unit immediately before the enable signal is turned off. To.

  According to another aspect of the present invention, there is provided a method for controlling a semiconductor integrated circuit, wherein, in order to solve the above-described problem, the external signal is input via an interface unit when an enable signal input from an external circuit is on. A communication step for communicating with a circuit; a power supply control step for controlling supply of power to the interface unit; and a processing step for performing various processes in a core unit connected to the interface unit. The control step is characterized in that power is supplied to the interface unit when the enable signal is on and supply of power to the interface unit is stopped when the enable signal is off.

  According to another aspect of the present invention, there is provided a method for controlling a semiconductor integrated circuit, wherein, in order to solve the above-described problem, the external signal is input via an interface unit when an enable signal input from an external circuit is on. A communication step for communicating with a circuit; a power supply control step for controlling supply of power to the interface unit; a processing step for performing various processes in a core unit connected to the interface unit; A data transmission step of transmitting data to and from the core unit via a data holding unit, wherein the power supply control step supplies power to the interface unit when the enable signal is on, and the enable signal When it is off, the supply of power to the interface unit is stopped, and the data transmission step includes the enable signal. There characterized in that from the interface unit immediately before turned off to hold the transmission data to the core unit to the data holding unit.

  According to the semiconductor integrated circuit and the control method thereof according to the present invention, in a semiconductor integrated circuit having a communication interface, leakage current is eliminated by realizing power gating by a very simple method without taking a special procedure. Electric power can be reduced.

  Embodiments of a semiconductor integrated circuit and a control method thereof according to the present invention will be described with reference to the accompanying drawings.

(1) Configuration FIG. 1 is a diagram illustrating a configuration example of a semiconductor integrated circuit 1 according to an embodiment of the present invention.

  The type and application of the semiconductor integrated circuit 1 according to the embodiment of the present invention are not particularly limited. For example, the semiconductor integrated circuit 1 is used as various digital control ICs such as an optical disc control IC and various signal processing ICs.

  The semiconductor integrated circuit 1 is connected to an interface unit 3 that communicates with an external circuit, a power supply control unit 2 that controls supply of power to the interface unit 3, and a core unit 4 that performs various controls and various processes. It is comprised with.

  Further, the data holding unit 5 may be provided between the interface unit 3 and the core unit 4.

  For example, the interface unit 3 uses the enable signal EN and the clock signal CK supplied from an external circuit as control signals, and exchanges the data signal DT with the external circuit.

  Buffer circuits are appropriately provided in the input / output portions of the enable signal EN, the clock signal CK, and the data signal DT, respectively. For example, buffer circuits 6a and 6b are provided for the enable signal EN, a buffer circuit 7 is provided for the clock signal CK, and bidirectional buffer circuits 8a and 8b are provided for the data signal DT.

  As schematically shown in FIG. 1, the interface unit 3 includes, for example, an interface unit logic circuit 30 and flip-flops 31, 32, and 33.

  The interface unit logic circuit 30 includes various logic circuits such as a parallel / serial conversion circuit, for example. The data transmitted from the core unit 4 is finally converted into serial data and output to the external circuit as a data signal DT. The flip-flops 31 and 32 are provided for outputting the data signal DT in synchronization with the clock signal CK from the external circuit.

  On the other hand, the flip-flop 33 is provided for taking in the data signal DT inputted from the external circuit in synchronization with the clock signal CK.

  Power is supplied from the power supply control unit 2 to each circuit of the interface unit 3. An interface unit power supply line is connected to the power supply control unit 2 and supplies power to each circuit of the interface unit 3 under the control of the enable signal EN.

  The core unit 4 includes various logic circuit groups, performs various controls and processes based on data received from the interface unit 3, and transmits the results to the interface unit 3. The power for each circuit of the core unit 4 is directly supplied from the core unit power line.

  The data holding unit 5 is a latch circuit, for example, and is configured to hold the output data of the flip-flop 33 at the falling timing of the enable signal EN.

(2) Operation The operation of the semiconductor integrated circuit 1 configured as described above will be described.

  FIG. 2 schematically shows an example of a timing chart of the enable signal EN, the clock signal CK, and the data signal DT input to the power supply control unit 2 and the interface unit 3 of the semiconductor integrated circuit 1.

  The enable signal EN is input from an external circuit in order to transmit the timing for performing communication from the external circuit to the semiconductor integrated circuit 1. During the period when the enable signal EN is on (active), a communication control signal such as a clock signal CK required for communication and a data signal DT are transmitted and received from an external circuit. Conversely, communication with an external circuit is not performed while the enable signal EN is off (inactive).

  In the example of FIG. 2, the periods indicated by “A” and “C” are periods in which the enable signal EN is OFF, and no communication is performed between the external circuit and the semiconductor integrated circuit 1 during this period.

  On the other hand, a period indicated by “B” is a period in which the enable signal EN is ON, and communication is performed between the external circuit and the semiconductor integrated circuit 1 during this period.

  FIG. 2 shows an example in which communication using 8-bit serial data “d0” to “d7” as the data signal DT is transmitted from the external circuit to the semiconductor integrated circuit 1 together with the clock signal CK.

  3 to 5 show the operating states of the semiconductor integrated circuit 1 corresponding to the on / off periods of the enable signal EN.

  FIG. 3 shows the state of the semiconductor integrated circuit 1 when the enable signal EN is off (period “A” in FIG. 2) before communication. The power supply control unit 2 is configured to stop power supply to each circuit of the interface unit 3 (Power Gating) when the enable signal EN is off. With this function of the power supply control unit 2, when the enable signal EN is off, power supply to each circuit of the interface unit 3 is stopped as shown by hatching in FIG.

  FIG. 4 shows the state of the semiconductor integrated circuit 1 during communication, which corresponds to the ON state of the enable signal EN (period “B” in FIG. 2). The power supply control unit 2 is configured to supply power to each circuit of the interface unit 3 when the enable signal EN is on. Accordingly, during the period when the enable signal EN is on, power is supplied to each circuit of the interface unit 3 to perform normal operation. Specifically, the data signal DT (serial data) is taken into the interface unit 3 in synchronization with the clock signal CK and sequentially transmitted to the core unit 4 via the data holding unit 5.

  FIG. 5 shows the state of the semiconductor integrated circuit 1 after communication, and the enable signal EN is turned off again (period “C” in FIG. 2). The power supply control unit 2 stops the power supply to each circuit to the interface unit 3 in response to the enable signal EN being turned off again.

  The data holding unit 5 is, for example, a latch circuit, and holds the output of the flip-flop 33 when the enable signal EN is switched from on to off. This holding function of the data holding unit 5 prevents an indefinite signal from the interface unit 3 to the core unit 4 even when the power supply to the interface unit 3 is stopped.

  In the example of FIG. 2, the last bit of the 8-bit serial data is “d7”, and this data “d7” is transferred from the flip-flop 33 to the data holding unit 5 at the timing when the enable signal EN is switched from on to off. The data “d7” is held in the data holding unit 5. For this reason, even if the power of the interface unit 3 is turned off, the operation of the core unit 4 is guaranteed.

  According to the semiconductor integrated circuit 1 according to the present embodiment, the power supply to each circuit of the interface unit 3 is controlled by the enable signal EN indicating the communication period. As a result, it is possible to stop all the power supply to each circuit of the interface unit 3 during the communication period, and to reduce the leakage current of the interface unit 3 to the limit. For this reason, the power consumption of the semiconductor integrated circuit 1 as a whole can be reduced.

  Further, according to the semiconductor integrated circuit 1 of the present embodiment, the control signal for power supply is the enable signal EN. The enable signal EN is a signal generally used in communication between devices. For this reason, it is not necessary to add a new control signal or the like for power supply control.

  Further, since the power supply control target part is the communication interface unit 3, there is no unexpected adverse effect on the entire semiconductor integrated circuit 1. Therefore, a user (designer or the like) of the semiconductor integrated circuit 1 can use the power supply control function (Power Gating function) almost without being aware of it.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the components without departing from the scope of the invention in the implementation stage. For example, in the above description, the communication interface has been described as serial communication. However, the present invention is not limited to this, and parallel communication or a combination of parallel communication and serial communication may be used.

  In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, the constituent elements over different embodiments may be appropriately combined.

The figure which shows the structural example of embodiment of the semiconductor integrated circuit which concerns on this invention. The figure which shows an example of the timing of the communication interface in embodiment of the semiconductor integrated circuit which concerns on this invention. The figure which shows the example of the power supply state before communication in embodiment of the semiconductor integrated circuit which concerns on this invention. The figure which shows the example of the power supply state in communication in embodiment of the semiconductor integrated circuit which concerns on this invention. The figure which shows the example of the power supply state after communication in embodiment of the semiconductor integrated circuit which concerns on this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit 2 Power supply control part 3 Interface part 4 Core part 5 Data holding part 30 Interface part logic circuit 31, 32, 33 Flip-flop EN Enable signal CK Clock signal DT Data signal

Claims (6)

An interface unit that communicates with the external circuit when an enable signal input from the external circuit is on;
A power supply control unit for controlling supply of power to the interface unit;
A core unit connected to the interface unit for performing various processes;
With
The power supply control unit supplies power to the interface unit when the enable signal is on, and stops supplying power to the interface unit when the enable signal is off. circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the communication with the external circuit is based on at least one of a serial interface and a parallel interface. An interface unit that communicates with the external circuit when an enable signal input from the external circuit is on;
A power supply control unit for controlling supply of power to the interface unit;
A core unit connected to the interface unit for performing various processes;
A data holding unit provided at a connection portion between the interface unit and the core unit;
With
The power supply control unit supplies power to the interface unit when the enable signal is on, and stops supplying power to the interface unit when the enable signal is off,
The data holding unit holds transmission data from the interface unit to the core unit immediately before the enable signal is turned off.
A semiconductor integrated circuit. 4. The semiconductor integrated circuit according to claim 3, wherein the communication with the external circuit is based on at least one of a serial interface and a parallel interface. A communication step of communicating with the external circuit via the interface unit when an enable signal input from the external circuit is on;
A power supply control step for controlling power supply to the interface unit;
Processing steps for performing various processes in the core unit connected to the interface unit;
With
The power supply control step supplies power to the interface unit when the enable signal is on, and stops supplying power to the interface unit when the enable signal is off. Circuit control method. A communication step of communicating with the external circuit via the interface unit when an enable signal input from the external circuit is on;
A power supply control step for controlling power supply to the interface unit;
Processing steps for performing various processes in the core unit connected to the interface unit;
A data transmission step of transmitting data between the interface unit and the core unit via a data holding unit;
With
The power supply control step supplies power to the interface unit when the enable signal is on, and stops supplying power to the interface unit when the enable signal is off,
In the data transmission step, transmission data from the interface unit to the core unit immediately before the enable signal is turned off is held in the data holding unit.
A method for controlling a semiconductor integrated circuit.

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